Topic
Latency (engineering)
About: Latency (engineering) is a research topic. Over the lifetime, 3729 publications have been published within this topic receiving 39210 citations. The topic is also known as: lag.
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TL;DR: An algorithm for modeling CAC in an area served by the three categories of services in a 5G access network, mainly based on minimum energy consumption is suggested, which will allow connected objects that consume low energy to connect to the network with an adequate quality of service and enable the development of the Internet of Things.
Abstract: The International Telecommunications Union defines in its IMT‐2020 recommendations three types of use of 5G services: mMTC (massive Machine‐type Communications), eMBB (enhanced Mobile Broadband), and uRLLC (ultra‐Reliable Low Latency Communications). The mMTC service allows a considerable number of machines and devices to communicate while guaranteeing a good quality of service. The eMBB service allows very high data throughput, even at the cell border. The uRLLC service is used for ultra‐reliable communication for critical needs requiring very low latency. These services are provided separately in a given cell. However, the number of connected objects is starting to increase rapidly as well as the bit rates and energy consumption. The 5G network must make it possible to provide access to a vast number of users of its different service categories. Call admission control (CAC) techniques focus more on availability in terms of bit rate and coverage. In this article, we suggest an algorithm for modeling CAC in an area served by the three categories of services in a 5G access network, mainly based on minimum energy consumption. This technique will allow connected objects that consume low energy to connect to the network with an adequate quality of service and enable the development of the Internet of Things.
16 citations
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11 Oct 1992
TL;DR: Some of the issues arising in the design of the T9000 transputer, which integrates a complete computer in a single VLSI chip of over two million transistors, are discussed.
Abstract: Some of the issues arising in the design of the T9000 transputer, which integrates a complete computer in a single VLSI chip of over two million transistors, are discussed. High performance has been achieved by extensive use of caching and a novel processor implementation. The processor uses a fat pipeline and dispatches several dependent instructions into the pipeline each cycle. The resulting processor is able to saturate a 25-MFLOP floating-point unit. The processor is supported by a communications system that supports communications at high speed and low latency. >
16 citations
TL;DR: This paper presents a deadline-aware flow scheduling (DAFS), which aims at decreasing the deadline mismatch and blocking probabilities, hence improving the average application throughput and an analytical queuing model is formulated herein to capture the datacenter’s network dynamics and evaluate its performance when operating under DAFS.
Abstract: Real-time interactive application workloads (e.g., Web search, social networking, and so on) appear in the form of a large number of mini requests and responses flowing over the datacenters’ networks. They end up being sewed all together to constitute a user-requested task or computation (e.g., display a complete Facebook timeline). Applications as such strictly impose low latency flow completion, since the service’s quality is decreed by quick aggregation of responses to the largest possible fraction of requests and their delivery back to the user. This paper presents a deadline-aware flow scheduling (DAFS). In addition to reducing the average flow completion time (FCT), DAFS aims at decreasing the deadline mismatch and blocking probabilities, hence improving the average application throughput. An analytical queuing model is formulated herein to capture the datacenter’s network dynamics and evaluate its performance when operating under DAFS. The model is validated through extensive simulations whose results also show that DAFS outperforms existing multi-queue-based priority mechanisms by 52% in terms of the average FCT and a range of 7%–29% in terms of the average throughput.
16 citations
30 May 2018
TL;DR: This paper proposes an overlay architecture that features a novel Network-on-Chip (NoC) infrastructure making flexible, with no limitation, the placement of hardware tasks and eases the reconfiguration of desired areas on the fabric at runtime.
Abstract: One of the major obstacles to the adoption of FPGAs in high-performance computing is their programmability. It requires hardware design skills and long compilation times. Overlays have been proposed as a way to abstract FPGA resources. Unfortunately, most of the time, the topologies they use to connect computing cores impose restrictions on where tasks are placed and how they communicate. In this paper, we propose an overlay architecture designed for efficiency and flexibility. It features a novel Network-on-Chip (NoC) infrastructure making flexible, with no limitation, the placement of hardware tasks. The presented architecture allows tasks to communicate with a low latency and eases the reconfiguration of desired areas on the fabric at runtime. After prototyping the proposed architecture on an Altera Cyclone V FPGA, a maximum frequency of 282 MHz has been reached and a speedup ranging from 4x to 195x has been observed in some applications compared to the native execution.
16 citations
TL;DR: A new data dissemination protocol for wireless sensor networks, that basically pulls some additional knowledge about the network in order to subsequently improve data forwarding towards the sink, showing that it significantly outperforms well known relevant solutions in the state of the art.
16 citations