Latency (engineering)

About: Latency (engineering) is a research topic. Over the lifetime, 3729 publications have been published within this topic receiving 39210 citations. The topic is also known as: lag.

Dynamic interval polling and pipelined post I/O processing for low-latency storage class memory

Abstract: Emerging non-volatile memory technologies as a disk drive replacement raise some issues of software stack and interfaces, which have not been considered in disk-based storage systems. In this work, we present new cooperative schemes including software and hardware to address performance issues with deploying storage-class memory technologies as a storage device. First, we propose a new polling scheme called dynamic interval polling to avoid the unnecessary polls and reduce the burden on storage system bus. Second, we propose a pipelined execution between storage device and host OS called pipelined post I/O processing. By extending vendor-specific I/O interfaces between software and hardware, we can improve the responsiveness of I/O requests with no sacrifice of throughput.

High Reliability, Low Latency and Cost Effective Network Planning for Industrial Wireless Mesh Networks

Abstract: In this paper, we study high reliability, low latency and cost effective network planning for industrial wireless mesh networks. Based on the requirements of routing reliability, minimum end-to-end delay and reduced deployment cost in wireless mesh networks, such as WirelessHART network, we propose three network planning approaches following the principles of the shortest hops, the least routers and balance of the shortest hops and the least routers, respectively. We then implement the proposed algorithms respectively to generate the network deployment for a given factory layout. Simulation results show that there exists a performance trade-off between these three algorithms. The proposed algorithms have also been implemented and validated in an NS-2 WirelessHART network simulator.

A 2Gbps 21ch low-latency transceiver circuit for inter-processor communication

Abstract: A 20-data-channel transceiver with a control channel allows uncoded data transfer with 13ns latency. A digital DLL (Delay Locked Loop) with a ring-interpolator tracks phase with 20ps resolution. A pre-emphasis driver enables 2Gbps transmission per channel over a 7m cable at 1.5V supply. The effective full-duplex bandwidth reaches 10GB/s.

Design and analysis of a reconfigurable XOR/OR logic gate using 2D photonic crystals with low latency

Abstract: Realization of logical gates in the optical domain is a crucial part of current research to take the advantages of light speed in future demands, an example optical computer motherboard. Here, this paper proposed a simple reconfigurable XOR/OR gate using Two-Dimensional (2D) Photonic crystal structure. The performance of the device is analyzed using 2D finite difference time domain method. The dimension of the proposed crystal structure is 12.5 µm × 12 µm. The field distribution has been measured and displayed to indicate the performance of the logic gates. The proposed structure is very compact with a low latency of 120 fs.

Practical Enhancement and Evaluation of a Low-Latency Network Model Using Mobile Edge Computing

Abstract: Most of latency-sensitive mobile applications require computational resources provided through a cloud computing service. The problem of relying on cloud computing is that, sometimes, the physical locations of cloud servers are distant from mobile users and the communication latency is long. As a result, the concept of distributed cloud service, called mobile edge computing (MEC), is being introduced in the 5G network. However, MEC can reduce only the communication latency. The computing latency in MEC must also be considered to satisfy the required total latency of services. In this research, we study the impact of both latencies in MEC architecture with regard to latency-sensitive services. We also consider a centralized model, in which we use a controller to manage flows between users and mobile edge resources to analyze MEC in a practical architecture. The simulation results show that the controller interval and hop delay lead some blocking and error in the system. However the permissive system which relaxes latency constrains and chooses an edge server by the lowest total latency can improve the system performance impressively.