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Latency (engineering)

About: Latency (engineering) is a research topic. Over the lifetime, 3729 publications have been published within this topic receiving 39210 citations. The topic is also known as: lag.


Papers
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Proceedings ArticleDOI
06 Nov 2018
TL;DR: In this paper, an integrated laser neuron can exhibit extraordinary low latency (<1ns) and speed (∼1 × 1012 MACs/s per device) compared to state-of-the-art processors in digital electronics.
Abstract: We show that an integrated laser neuron can exhibit extraordinary low latency (<1ns) and speed (∼1 × 1012 MACs/s per device) compared to state-of-the-art processors in digital electronics. We experimentally demonstrate positive (excitatory) and negative (inhibitory) inputs with 8× wavelength channels, and efficiency (<1pJ/MAC) during closed-loop operation.

12 citations

01 Jan 2013
TL;DR: A novel architecture for Single Input Single Output (SISO) 1x1, Multiple Input Single output (MISO) 4x1), Multiple Input Multiple Output (MIMO)4x2 for Physical Downlink Control Channels of LTE is proposed.
Abstract: Long Term Evolution (LTE) of UMTS Terrestrial Radio Access and Radio Access Network is a Fourth Generation wireless broadband technology which is capable of providing backward compatibility with 2G (Second Generation) and 3G (Third Generation) technologies. LTE is able to deliver high data rate and low latency with reduced cost This paper proposes a novel architecture for Single Input Single Output(SISO) 1x1, Multiple Input Single Output (MISO) 4x1, Multiple Input Multiple Output (MIMO)4x2 for Physical Downlink Control Channels of LTE. The physical downlink channel processing involves as scrambling, modulation, layer mapping, precoding, data mapping to resource elements at transmitter and demapping from resource elements, decoding, delayer mapping, demodulation and descrambling at receiver. In the proposed architecture, these steps are carried out in a single architecture comprises of all the data and control channels. Based on simulation and implementation, results are discussed in terms of Register Transfer Level (RTL) design, Field Programmable Gate Arrays (FPGA) editor, power estimation and resource estimation. To simulate all the modules of all control channels, ModelSim is used. For synthesis and implementation of the above architecture PlanAhead 13.2 tool on Virtex-5, xc5vlx50tff1136-1 device board is used.

12 citations

Proceedings ArticleDOI
01 Dec 2016
TL;DR: In this article, the authors provide analytical bounds of latency-aware caching policies and evaluate their performance by network simulations, showing that the proposed mechanisms can halve the mean and standard deviation of content delivery time with respect to approximations of LFU as leave a copy probabilistically.
Abstract: 5G has loudly ambitioned to achieve extremely low latency in mobile networks. To this aim, we have recently introduced two novel latency-aware caching heuristics, LAC and LAC+ and we showed through simulations in Information-Centric Networks their good performance figures. In this paper, we present an insight on their operations: a mathematical analysis of these caching systems led us to novel results that we validate in simulation. The advantages of these algorithms come (i) on one side from the fact they are distributed and lightweight and (ii) from the ability to quickly adapt to content popularity and network congestion, with no signaling nor explicit coordination between the network nodes. In this paper we provide analytical bounds of latency aware caching policies and evaluate their performance by network simulations. The proposed mechanisms can halve the mean and standard deviation of content delivery time with respect to approximations of LFU as leave a copy probabilistically.

12 citations

Journal ArticleDOI
TL;DR: iCASM, an ICN-based network architecture for wide area smart grid communications achieves low latency and 100% data delivery even during network congestion by leveraging multiple available paths; thus significantly improving communication resiliency in comparison to an IP-based approach.
Abstract: Wide Area Measurement Systems (WAMS) use an underlying communication network to collect and analyze data from devices in the power grid, aimed to improve grid operations. For WAMS to be effective, the communication network needs to support low packet latency and low packet losses. Internet Protocol (IP), the pervasive technology used in today's communication networks uses loop-free best-paths for data forwarding, which increases the load on these paths causing delays and losses in delivery. Information-Centric Networking (ICN), a new networking paradigm, designed to enable a data-centric information sharing, natively supports the concurrent use of multiple transmission interfaces, in-networking caching, as well as per-packet security and can provide better application support. In this paper, we present iCASM, an ICN-based network architecture for wide area smart grid communications. We demonstrate through simulations that iCASM achieves low latency and 100% data delivery even during network congestion by leveraging multiple available paths; thus significantly improving communication resiliency in comparison to an IP-based approach. iCASM can be used immediately on today's Internet as an overlay.

12 citations

Journal Article
Abstract: Network slicing is a promising approach for enabling low latency computation offloading in edge computing systems. In this paper, we consider an edge computing system under network slicing in which ...

12 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202210
2021692
2020481
2019389
2018366
2017227