Latency (engineering)

About: Latency (engineering) is a research topic. Over the lifetime, 3729 publications have been published within this topic receiving 39210 citations. The topic is also known as: lag.

An Ultra-low-power Medium Access Control Protocol for Body Sensor Network

Abstract: In this paper, a medium access control (MAC) protocol designed for body sensor network (BSN-MAC) is proposed. BSN-MAC is an adaptive, feedback-based and IEEE 802.15.4-compatible MAC protocol. Due to the traffic coupling and sensor diversity characteristics of BSNs, common MAC protocols can not satisfy the unique requirements of the biomedical sensors in BSN. BSN-MAC exploits the feedback information from the deployed sensors to form a closed-loop control of the MAC parameters. A control algorithm is proposed to enable the BSN coordinator to adjust parameters of the IEEE 802.15.4 superframe to achieve both energy efficiency and low latency on energy critical nodes. We evaluate the performance of BSN-MAC using energy efficiency as the primary metric

Latency and Reliability Aware Edge Computation Offloading via an Intelligent Reflecting Surface

Abstract: Despite the advantages of multi-access edge computing in enabling latency-sensitive services and extending the limited computing capabilities of network devices, access communication issues are still often causing the quality of the wireless channels to be severely degraded, preventing the edge resources from being efficiently utilized. Through the deployment of low-cost passive reflecting elements, the recent studies of intelligent reflecting surfaces (IRSs) in wireless networks have shown a great potential for enhancing the quality of the wireless channels and the transmission rates. In this work, motivated by the recent findings, we study the use of an IRS-aided edge computing system for enabling low latency and high reliability computation offloading in the context of a single-user network. Specifically, we optimize the phase shift of the IRS elements along with the device’s transmit power and offloading decision, with the objective of minimizing the device’s energy consumption. Due to the non-convexity of the problem, we propose a customized sub-optimal solution based on the alternating optimization approach, utilizing novel successive convex approximation techniques. Numerical analysis demonstrates the energy reduction and saving in network resources provided by the optimized use of the IRS, especially for offloading services with higher reliability.

CMOS implementation of a new high speed, glitch-free 5-2 compressor for fast arithmetic operations

Abstract: This paper presents a new high speed, low power 5-2 compressor which is constructed according to a sensible combination of pass transistor logics and static logics. The 5-2 compressor is designed based on a new truth table that is obtained by performing some changes on its conventional truth table. So simple structures are obtained in which capacitances of middle stages are decreased. Therefore, a reduction of power dissipation and a reduction of overall latency are achieved. Also, the input and internal driving problems have been decreased, considerably. Because of similar paths from inputs to the outputs, there will be no need for extra buffers in low latency paths to equalize the delays. Therefore, the power dissipation will be decreased and the output waveforms will be glitch-free. Furthermore, utilizing voltage full swing logics in these architectures has enhanced the speed of cascaded operations. The total latency and power dissipation of the proposed 5-2 compressor are about 302 ps and 248.62 μw, respectively, which is simulated by HSPICE using TSMC 0.18 μm CMOS technology.