Latency (engineering)

About: Latency (engineering) is a research topic. Over the lifetime, 3729 publications have been published within this topic receiving 39210 citations. The topic is also known as: lag.

Shielded processors: guaranteeing sub-millisecond response in standard Linux

Abstract: The low latency and preemption patches provide significant progress making standard Linux into a more responsive system for real-time applications. These patches allow guarantees on worst case interrupt response time at slightly above a millisecond. However, these guarantees can only be met when there is no networking or graphics activity in the system. This paper describes the implementation of shielded processors in RedHawk Linux and their benefits. It also presents the results of real time performance benchmarks. Interrupt response time guarantees are significantly below one millisecond and can be guaranteed even in the presence of networking and graphics activity.

Ultra-low latency lte reference signal transmission

Abstract: Various aspects described herein relate to communicating in a wireless network. A resource grant comprising an indicator of whether to transmit a demodulation reference signal (RS) for an uplink control channel or an uplink data channel can be received from a network entity. It can be determined whether to transmit the RS in at least one transmission time interval (TTI) based at least in part on the indicator.

High capacity, low-latency multiplexer

Abstract: A method for multiplexing compressed video data streams where the time for sending portions of a video frame are adjusted to reduce latency. If a compressed frame cannot be delivered in the appropriate frame time, due to bandwidth limitations, the frame is broken into parts and a part is sent in an earlier frame time. This method allows complete frames to be available at a receiver at the correct time. Accurate methods of deriving clock signals from the data stream are also described.

FPGA based hardware implementation of AES Rijndael algorithm for Encryption and Decryption

Abstract: AES algorithm or Rijndael algorithm is a network security algorithm which is most commonly used in all types of wired and wireless digital communication networks for secure transmission of data between two end users, especially over a public network. This paper presents the hardware implementation of AES Rijndael Encryption and Decryption Algorithm by using Xilinx Virtex-7 FPGA. The hardware design approach is entirely based on pre-calculated look-up tables (LUTs) which results in less complex architecture, thereby providing high throughput and low latency. There are basically three different formats in AES. They are AES-128, AES-192 and AES-256. The encryption and decryption blocks of all the three formats are efficiently designed by using Verilog-HDL and are synthesized on Virtex-7 XC7VX690T chip (Target Device) with the help of Xilinx ISE Design Suite-14.7 Tool. The synthesis tool was set to optimize speed, area and power. The power analysis is made by using Xilinx XPower Analyzer. Pre-calculated LUTs are used for the implementation of algorithmic functions, namely S-Box and Inverse S-Box transformations and also for GF (28) i.e. Galois Field Multiplications involved in Mix-Columns and Inverse Mix-Columns transformations. The proposed architecture is found to be having good efficiency in terms of latency, throughput, speed/delay, area and power.