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Latency (engineering)

About: Latency (engineering) is a research topic. Over the lifetime, 3729 publications have been published within this topic receiving 39210 citations. The topic is also known as: lag.


Papers
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Proceedings ArticleDOI
01 Nov 2021
TL;DR: In this article, the authors present Atoll, a serverless platform that overcomes the challenges of serverless platforms via a ground-up redesign of the control and data planes.
Abstract: With user-facing apps adopting serverless computing, good latency performance of serverless platforms has become a strong fundamental requirement. However, it is difficult to achieve this on platforms today due to the design of their underlying control and data planes that are particularly ill-suited to short-lived functions with unpredictable arrival patterns. We present Atoll, a serverless platform, that overcomes the challenges via a ground-up redesign of the control and data planes. In Atoll, each app is associated with a latency deadline. Atoll achieves its per-app request latency goals by: (a) partitioning the cluster into (semi-global scheduler, worker pool) pairs, (b) performing deadline-aware scheduling and proactive sandbox allocation, and (c) using a load balancing layer to do sandbox-aware routing, and automatically scale the semi-global schedulers per app. Our results show that Atoll reduces missed deadlines by ~66x and tail latencies by ~3x compared to state-of-the-art alternatives.

36 citations

Patent
19 Jan 2001
TL;DR: In this paper, the authors propose a sub-frame structure for variable high data rates with the flexibility to efficiently carry lower data rate, lower latency frames using sub-framing, where each voice customer is allotted one or more frames or portions of frames within the superframe, called sub-frames, as is needed to deliver the lower latency voice communication.
Abstract: A frame structure that is ordinarily optimized for providing variable high data rates also includes the flexibility to efficiently carry lower data rate, lower latency frames using sub-framing. Superframes, each comprised of a predetermined number of frames, carry voice and data communications at one or more variable data rates. The size of a superframe is limited, such as by the delay tolerance for voice transmission, typically 20 ms. Each voice customer is allotted one or more frames or portions of frames within the superframe, called sub-frames, as is needed to deliver the lower data rate, low latency voice communication. The allocation for the voice customers is not fixed, but varies as the data rate varies over time. Any bits in a frame that are not needed to carry voice communication are assigned to carry data having compatible data rate requirements. Additionally, the subframing concept may be extended to include ATM cells.

36 citations

Journal ArticleDOI
TL;DR: Simulation results show that the proposed protocol outperforms SMAC protocol in both energy consumption and packet latency.
Abstract: Reducing unnecessary and redundant handshake frame is considered as a promising way to reduce the end-to-end delay and energy consumption. Here, a protocol named compressed handshake media access control (CH-MAC) is presented. CH-MAC introduces a new handshake mechanism with implicit RTS to achieve the object of low delivery latency and an initiative sleeping mechanism to settle the hidden terminal problem. Simulation results show that the proposed protocol outperforms SMAC protocol in both energy consumption and packet latency.

36 citations

Proceedings ArticleDOI
31 Aug 2010
TL;DR: This study compares three pipelined adder architectures: the classical pipelining ripple-carry adder, a variation that reduces register count, and an FPGA-specific implementation of the carry-select adder capable of providing lower latency additions at a comparable price.
Abstract: Integer addition is a universal building block, and applications such as quad-precision floating-point or elliptic curve cryptography now demand precisions well beyond 64 bits. This study explores the trade-offs between size, latency and frequency for pipelined large-precision adders on FPGA. It compares three pipelined adder architectures: the classical pipelined ripple-carry adder, a variation that reduces register count, and an FPGA-specific implementation of the carry-select adder capable of providing lower latency additions at a comparable price. For each of these architectures, resource estimation models are defined, and used in an adder generator that selects the best architecture considering the target FPGA, the target operating frequency, and the addition bit width.

36 citations

Journal ArticleDOI
Kun Ren1, Dennis Li, Daniel J. Abadi
01 Jul 2019
TL;DR: Experiments find that SLOG can reduce latency by more than an order of magnitude relative to state-of-the-art strictly serializable geo-replicated database systems such as Spanner and Calvin, while maintaining high throughput under contention.
Abstract: For decades, applications deployed on a world-wide scale have been forced to give up at least one of (1) strict serializability (2) low latency writes (3) high transactional throughput. In this paper we discuss SLOG: a system that avoids this tradeoff for workloads which contain physical region locality in data access. SLOG achieves high-throughput, strictly serializable ACID transactions at geo-replicated distance and scale for all transactions submitted across the world, all the while achieving low latency for transactions that initiate from a location close to the home region for data they access. Experiments find that SLOG can reduce latency by more than an order of magnitude relative to state-of-the-art strictly serializable geo-replicated database systems such as Spanner and Calvin, while maintaining high throughput under contention.

36 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202210
2021692
2020481
2019389
2018366
2017227