Latency (engineering)

About: Latency (engineering) is a research topic. Over the lifetime, 3729 publications have been published within this topic receiving 39210 citations. The topic is also known as: lag.

Power-Efficient and High-Performance Multi-level Hybrid Nanophotonic Interconnect for Multicores

Abstract: Network-on-Chips (NoCs) are becoming the defacto standard for interconnecting the increasing number of cores in chip multiprocessors (CMPs) by overcoming the scalability and wire delay problems of shared buses. However, recent research has shown that future NoCs will be limited by power dissipation and reduced performance forcing architects to explore other technologies that are complementary metal oxide semiconductor (CMOS) compatible. In this paper, we propose ET-PROPEL (Extended Token based Photonic Reconfigurable On-Chip Power and Area-Efficient Links) architecture to utilize the emerging nanophotonic technology to design a high-bandwidth, low latency and low power multi-level hybrid interconnect that balances cost and performance. We develop our interconnect at three levels: at the first level (x) we design a fully connected network for exploiting locality; at the second level(y), we design a shared channel using optical tokens to reduce power while providing full connectivity and at the third level (z), we propose a novel nanophotonic crossbar that provides scalable bisection bandwidth. The first two levels are combined into T-PROPEL(token-PROPEL, 64 cores) and four separate T-PROPELs are combined into ET-PROPEL (256 cores). We have simulated both T-PROPEL and ET-PROPEL using synthetic and SPLASH-2 traffic, where our results indicate that T-PROPEL and ET-PROPEL significantly reduce power(10-fold) and increase performance (3-fold) over other well known electrical and photonic networks.

Rendering-Aware VR Video Caching Over Multi-Cell MEC Networks

Abstract: Delivering high fidelity virtual reality (VR) video over mobile networks is very challenging since VR applications usually require very high bandwidth and ultra low latency. With the evolution of 5G mobile networks, multi-cell multi-access edge computing (MEC) networks enable low latency data communication. However, even in this setting, the requirements of VR applications are tough to meet. To optimize the end-to-end latency for VR video delivery over multi-cell MEC networks, we propose a rendering-aware tile caching scheme. As a first step we propose collaborative tile caching in 5G MEC networks by enabling multiple cell sites to share caches so that the network caching performance is improved. Hence, the amount of redundant data delivered and eventually the latency are both significantly reduced. Second, our scheme offloads viewport rendering of VR video to the MEC server and closely couples this with cache placement, allowing thus the rendering-induced latency to be reduced. Finally, a low-delay request routing algorithm is integrated with the proposed cache placement scheme to further optimize the end-to-end latency of VR video delivery. Extensive simulation results show that the proposed rendering-aware caching scheme can achieve better latency performance than the state-of-the-art decoupled caching/rendering schemes.

Real-Time Speech Recognition for IoT Purpose using a Delta Recurrent Neural Network Accelerator

Abstract: This paper describes a continuous speech recognition hardware system that uses a delta recurrent neural network accelerator (DeltaRNN) implemented on a Xilinx Zynq-7100 FPGA to enable low latency recurrent neural network (RNN) computation. The implemented network consists of a single-layer RNN with 256 gated recurrent unit (GRU) neurons and is driven by input features generated either from the output of a filter bank running on the ARM core of the FPGA in a PmodMic3 microphone setup or from the asynchronous outputs of a spiking silicon cochlea circuit. The microphone setup achieves 7.1 ms minimum latency and 177 frames-per-second (FPS) maximum throughput while the cochlea setup achieves 2.9 ms minimum latency and 345 FPS maximum throughput. The low latency and 70 mW power consumption of the DeltaRNN makes it suitable as an IoT computing platform.

Tree-model based mapping for energy-efficient and low-latency Network-on-Chip

Abstract: With the NoC size growing constantly, efficient algorithms are needed to provide power/performance-aware task mapping on massively parallel systems. In this paper a novel tree-model based mapping algorithm is proposed, to achieve high energy efficiency and low latency on NoC platforms. A NoC is abstracted as a tree composed of a root node and median nodes at different levels. By mapping tasks starting from the root of the tree, our algorithm minimizes the communication cost and consequently reduces the energy consumption and network delay. Experimental results show that the run-time of our algorithm is decreased by 90% on average compared to the Greedy Incremental (GI) algorithm. Full system simulation also shows that for Radix traffic, compared to the original random mapping, the GI achieves 18.7% and 17.3% reduction in energy consumption and average network latency respectively, while our algorithm achieves 24.7% and 40.8% reduction respectively.