LDMOS

About: LDMOS is a research topic. Over the lifetime, 3444 publications have been published within this topic receiving 28955 citations.

Dynamic behavioral modeling of 3G power amplifiers using real-valued time-delay neural networks

Abstract: In this paper, we propose a novel real-valued time-delay neural network (RVTDNN) suitable for dynamic modeling of the baseband nonlinear behaviors of third-generation (3G) base-station power amplifiers (PA) Parameters (weights and biases) of the proposed model are identified using the back-propagation algorithm, which is applied to the input and output waveforms of the PA recorded under real operation conditions Time- and frequency-domain simulation of a 90-W LDMOS PA output using this novel neural-network model exhibit a good agreement between the RVTDNN behavioral model's predicted results and measured ones along with a good generality Moreover, dynamic AM/AM and AM/PM characteristics obtained using the proposed model demonstrated that the RVTDNN can track and account for the memory effects of the PAs well These characteristics also point out that the small-signal response of the LDMOS PA is more affected by the memory effects than the PAs large-signal response when it is driven by 3G signals This RVTDNN model requires a significantly reduced complexity and shorter processing time in the analysis and training procedures, when driven with complex modulated and highly varying envelope signals such as 3G signals, than previously published neural-network-based PA models

Modeling of the on-resistance of LDMOS, VDMOS, and VMOS power transistors

Abstract: Power MOS transistors have recently begun to rival bipolar devices in power-handling capability. This new capability has arisen primarily through the use of double-diffusion techniques to achieve short active channels and the incorporation of a lightly doped drift region between the channel and the drain contact, which largely supports the applied voltage. Many different structures have been proposed to implement these new devices. This paper considers three of the most common-LDMOS, VDMOS, and VMOS. Structural differences which result in on-resistance and transconductance differences between the devices are described. Quantitative models, suitable for device design, are developed for the on-resistance of each type of structure. These models are developed directly from the physical structure (geometry and doping profiles) so that they are useful in optimizing a particular device structure or in quantitatively comparing structures for a particular application.

Design of Varactor-Based Tunable Matching Networks for Dynamic Load Modulation of High Power Amplifiers

Abstract: In this paper, the design of varactor-based tunable matching networks for dynamic load modulation of high power amplifiers (PAs) is presented. Design guidelines to overcome the common breakdown, and tunability problems of the varactors for high power applications are proposed. Based on the guidelines, using commercially available abrupt junction silicon varactors, a tunable matching network is built and measured. The matching network is then used for load modulation of a 1-GHz 7-W class-E LDMOS PA. Static measurements of the load modulated PA show that the power-added efficiency of the PA is improved by an absolute value of 10% at 10-dB backoff. This promising result proves, for the first time, the feasibility of load modulation techniques for high-power applications in the gigahertz frequency range.

Modeling and Characterization of RF and Microwave Power FETs

Abstract: © Cambridge University Press 2007 and Cambridge University Press, 2009.This 2007 book is a comprehensive exposition of FET modeling, and is a must-have resource for seasoned professionals and new graduates in the RF and microwave power amplifier design and modeling community. In it, you will find descriptions of characterization and measurement techniques, analysis methods, and the simulator implementation, model verification and validation procedures that are needed to produce a transistor model that can be used with confidence by the circuit designer. Written by semiconductor industry professionals with many years' device modeling experience in LDMOS and III-V technologies, this was the first book to address the modeling requirements specific to high-power RF transistors. A technology-independent approach is described, addressing thermal effects, scaling issues, nonlinear modeling, and in-package matching networks. These are illustrated using the current market-leading high-power RF technology, LDMOS, as well as with III-V power devices.

High-power time-domain measurement system with active harmonic load-pull for high-efficiency base-station amplifier design

Abstract: A measurement system combining vector corrected waveform measurements with active harmonic load-pull extends, for the first time, real-time experimental waveform engineering up to the 30-W power level. The vector correction procedure is presented in this paper. A novel harmonic load-pull approach based on the real-time measurement capability of the system is demonstrated on a 4-W LDMOS device. A 20% increase in maximum output power to 4.7 W without degrading gain and efficiency is realized. Waveform analysis at various drive and load conditions directly identifies nonlinear capacitance effects being a key design issue for the design of highly efficient power amplifier.