Leakage (electronics)

About: Leakage (electronics) is a research topic. Over the lifetime, 32751 publications have been published within this topic receiving 312149 citations. The topic is also known as: leakage current & charge leakage.

Molecular self-assembled monolayers and multilayers for organic and unconventional inorganic thin-film transistor applications

Abstract: Principal goals in organic thin-film transistor (OTFT) gate dielectric research include achieving: (i) low gate leakage currents and good chemical/thermal stability, (ii) minimized interface trap state densities to maximize charge transport efficiency, (iii) compatibility with both p- and n- channel organic semiconductors, (iv) enhanced capacitance to lower OTFT operating voltages, and (v) efficient fabrication via solution-phase processing methods. In this Review, we focus on a prominent class of alternative gate dielectric materials: self-assembled monolayers (SAMs) and multilayers (SAMTs) of organic molecules having good insulating properties and large capacitance values, requisite properties for addressing these challenges. We first describe the formation and properties of SAMs on various surfaces (metals and oxides), followed by a discussion of fundamental factors governing charge transport through SAMs. The last section focuses on the roles that SAMs and SAMTs play in OTFTs, such as surface treatments, gate dielectrics, and finally as the semiconductor layer in ultra-thin OTFTs.

A review of methods for leakage management in pipe networks

Abstract: Leakage in water distribution systems is an important issue which is affecting water companies and their customers worldwide. It is therefore no surprise that it has attracted a lot of attention by both practitioners and researchers over the past years. Most of the leakage management related methods developed so far can be broadly classified as follows: (1) leakage assessment methods which are focusing on quantifying the amount of water lost; (2) leakage detection methods which are primarily concerned with the detection of leakage hotspots and (3) leakage control models which are focused on the effective control of current and future leakage levels. This paper provides a comprehensive review of the above methods with the objective to identify the current state-of-the-art in the field and to then make recommendations for future work. The review ends with the main conclusion that despite all the advancements made in the past, there is still a lot of scope and need for further work, especially in area of rea...

Leakage aware dynamic voltage scaling for real-time embedded systems

Abstract: A five-fold increase in leakage current is predicted with each technology generation. While Dynamic Voltage Scaling (DVS) is known to reduce dynamic power consumption, it also causes increased leakage energy drain by lengthening the interval over which a computation is carried out. Therefore, for minimization of the total energy, one needs to determine an operating point, called the critical speed. We compute processor slowdown factors based on the critical speed for energy minimization. Procrastination scheduling attempts to maximize the duration of idle intervals by keeping the processor in a sleep/shutdown state even if there are pending tasks, within the constraints imposed by performance requirements. Our simulation experiments show that the critical speed slowdown results in up to 5% energy gains over a leakage oblivious dynamic voltage scaling. Procrastination scheduling scheme extends the sleep intervals to up to 5 times, resulting in up to an additional 18% energy gains, while meeting all timing requirements.

Silicon Device Scaling to the Sub-10-nm Regime

Abstract: In the next decade, advances in complementary metal-oxide semiconductor fabrication will lead to devices with gate lengths (the region in the device that switches the current flow on and off) below 10 nanometers (nm), as compared with current gate lengths in chips that are now about 50 nm. However, conventional scaling will no longer be sufficient to continue device performance by creating smaller transistors. Alternatives that are being pursued include new device geometries such as ultrathin channel structures to control capacitive losses and multiple gates to better control leakage pathways. Improvement in device speed by enhancing the mobility of charge carriers may be obtained with strain engineering and the use of different crystal orientations. Here, we discuss challenges and possible solutions for continued silicon device performance trends down to the sub-10-nm gate regimes.

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

Abstract: In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased W eff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at L g =12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.