Showing papers on "Link-state routing protocol published in 1987"

Deadlock-Free Message Routing in Multiprocessor Interconnection Networks

Abstract: A deadlock-free routing algorithm can be generated for arbitrary interconnection networks using the concept of virtual channels. A necessary and sufficient condition for deadlock-free routing is the absence of cycles in a channel dependency graph. Given an arbitrary network and a routing function, the cycles of the channel dependency graph can be removed by splitting physical channels into groups of virtual channels. This method is used to develop deadlock-free routing algorithms for k-ary n-cubes, for cube-connected cycles, and for shuffle-exchange networks.

A classification scheme for vehicle routing and scheduling problems

Abstract: A classification scheme is proposed for a class of models that arise in the area of vehicle routing and scheduling and illustrated on a number of problems that have been considered in the literature. The classification scheme may serve as a first step towards the development of a model and algorithm management system in this area.

A Detailed Router Based on Incremental Routing Modifications: Mighty

Abstract: For the macrocell design style and for routing problems in which the routing regions are irregular, two-dimensional routers are often necessary. In this paper, a new routing technique that can be applied for general two-layer detailed routing problems, including switchboxes, channels, and partially routed areas, is presented. The routing regions that can be handled are very general: the boundaries can be described by any rectilinear edges, the pins can be on or inside the boundaries of the region, and the obstructions can be of any shape and size. The technique is based on an algorithm that routes the nets in the routing region incrementally and intelligently, and allows modifications and rip-up of nets when an existing shortest path is "far" from optimal or when no path exists. The modification steps (also called weak modification) relocate some segments of nets already routed to find a shorter path or to make room for a blocked net. The rip-up and reroute steps (called strong modifiction) remove segments of nets already routed to make room for a blocked connection; these steps are invoked only if weak modification fails. The algorithm has been rigorously proven to complete in finite time and its complexity has been analyzed. The algorithm has been implemented in the "C" programming language. Many test cases have been run, and on all the examples known in the literature the router has performed as well as or better than existing algorithms. In particular, Burstein's difficult switchbox example has been routed using one less column than the original data. In addition, the router has routed difficult channels such as Deutsch's in density and has performed better than or as well as YACR-II on all the channels available to us.

A new look at fault-tolerant network routing

Abstract: We model a communication network as a graph in which a processor is a node and a communication link is an edge. A routing for such a network is a fixed path, or route, between each pair of nodes. Given a network with a predefined routing, we study the effects of faulty components on the routing. Of particular interest is the number of routes along which a message must travel between any two non-faulty nodes. This problem is analyzed for specific families of graphs and for classes of routings. We also give some bounds for general versions of the problem. Finally, we conclude with one of the most important contributions of this paper, a list of interesting and apparently difficult open problems.

Geometrical Compaction in One Dimension for Channel Routing

Abstract: A channel router which is to be effective for general-purpose automatic routing must be able to use different sets of routing criteria priorities, in a controllable manner. We present an approach to channel routing with compaction in which channel compaction is adaptable to several routing criteria priorities. We show how overall channel routing performance can be improved by taking advantage of this versatility in channel compaction. We indicate some routing capabilities which cannot be effectively achieved by simply post-processing the output of a traditional gridded channel router. Our solution to this problem is outlined and some results obtained from our router are compared with those of other published channel routers.

A Preliminary Investigation into Parallel Routing on a Hypercube Computer

Abstract: This paper describes an experiment in which parallel routing is performed on a medium grained hypercube parallel processor having 64 processing elements. Each node is a complete 32-bit computer with 128 K-bytes of memory and is connected to the other nodes via a direct hypercube interconnection network. A new parallel routing algorithm was developed to exploit this parallel structure. It is a three step algorithm consisting of a global routing step, a boundary crossing placement step, and a detailed routing step. All steps can be performed in parallel. When applied to a standard benchmark it was able to route 95 % of the wires. The algorithm was also executed on a large mainframe computer using the same benchmark. The execution time was compared to that for the hypercube. The hypercube was about three times as fast.

Comparison of Routing Procedures for Circuit-Switched Traffic in Nonhierarchical Networks

Abstract: In this paper, we compare the use of different types of routing procedures for circuit-switched traffic in nonhierarchical networks. The main performance criterion used is the end-to-end blocking probability. The results show that if the network traffic is light, alternate routing performs better than nonalternate routing, but if the network traffic is heavy, the situation is reversed. To improve the performance of networks using alternate routing, different types of strategies varying from fixed control to dynamic control are introduced. A comparison based on numerical examples shows the improvement in performance attained by using a dynamic control strategy compared to fixed control. Good control techniques result in nonalternate routing under heavy traffic loads; nonalternate routing is the most viable alternative in nonhierarchical networks under heavy traffic conditions.

An optimal randomized routing algorithm for the mesh and a class of efficient mesh-like routing networks

Abstract: We present an optimal oblivious randomized algorithm for permutation routing on the MIMD version of Mesh. Our routing algorithm routes n2 elements on an n×n Mesh in 2n+O(log n) parallel communication steps with very high probability. Further, the maximum queue length at any node at any time is at the most O(log n) with the same probability. Since 2n is the distance bound for the Mesh, our algorithm is indeed optimal. Generalization of this result to k-dimensional (for any k) Meshes yields an algorithm that runs in time equal to the diameter of the Mesh. A lower bound result of [Schnorr and Shamir 86] states that sorting of n2 elements takes at least 3n steps on an n × n MIMD Mesh (for indexing schemes of practical interest). Thus our algorithm demonstrates that routing is easier than sorting on the MIMD Mesh.

Asymptotic optimality of shortest path routing algorithms

Abstract: Many communication networks use adaptive shortest path routing. By this we mean that each network link is periodically assigned a length that depends on its congestion level during the preceding period, and all traffic generated between length updates is routed along a shortest path corresponding to the latest link lengths. We show that in certain situations, typical of networks involving a large number of small users and utilizing virtual circuits, this routing method performs optimally in an asymptotic sense. In other cases, shortest path routing can be far from optimal.

General Purpose Router

Abstract: Numerous solutions to the problem of detailed routing of wires on a chip have been proposed for two routing layers but few are general enough to also handle switchboxes, more than two layers, variable channel widths, or multiple-layer problems with stacked terminals (3-D routing) without extensive modifications. We propose a different routing approach that not only can solve the two layer problem but the other problems as well. The inherent parallelism of the approach lead to a coarse-grained parallel algorithm.

Abstract Routing of Logic Networks for Custom Module Generation

Abstract: This paper describes a switchbox-type router for custom VLSI module generation as performed by a module planner. A module is decomposed into abstract cells consisting of global routes and boolean functional specifications. Each abstract cell is given to a cell synthesizer which generates the circuit layout and through-the-cell routing. Abstract routing for a module planner is in some sense similar to switchbox routing to the degree that all of the routes are generated internally within a rectangular boundary (routes are coming from four sides). The principle difference with respect to standard switchbox routing is at the geometric level, where a cell synthesizer generates the routing conduction layers along with circuit devices for each abstract cell within this rectangular region. The aspects of this paper which are thought to be novel contributions are 1) a relative pin assignment algorithm for the abstract cells; 2) a global routing penalty function which not only considers previous routes, but also considers gate complexity within the cells; 3) an efficient optimization algorithm for minimizing the number of tracks running through the module.

An architecture for network-layer routing in OSI

Abstract: Work on the standardization of routing protocols for OSI is in progress. The envisioned set of routing protocols is expected to work in nearly all of the environments which constitute OSI networks. Behind these routing protocols is an architecture which outlines problems and goals, establishes a framework upon which to base the development of protocols, and provides a conceptual baseline for continued work on unsolved problems. This architecture defines routing in the OSI network layer, functionally partitions the problem into its components, defines a routing hierarchy and an address hierarchy and discusses their relationship, and discusses arms-length routing relationships between differently administered networks. This paper presents that architecture, and discusses problems which remain to be solved as work progresses towards a global OSI network.

Delay and Routing in Interconnection Networks

Abstract: A very brief introduction to interconnection networks is given. It is then shown that, in a restricted sense, an ideal N-by-N crossbar switch can be simulated with slowdown factor logdN by a fully extended omega network built from d-by-d switches. Next, lower bounds are given for the product of the average traffic per link and the number of network links. The bounds are valid for interconnection networks with an upperbound on the number of links coming out of each node. Finally, it is shown that in a probabalistic sense, the peak traffic per link can be made close to the bound by using a slightly extended omega network. Randomized routing plays a key role in reducing congestion.

Efficient routing algorithm

Abstract: The line expansion algorithm provided by Heynes was a new kind of routing algorithm that took advantage of both Lee's algorithm and linear expansion algorithms, and hence was more efficient. However, it was less efficient in two layer routing situations. In this paper, this problem is analysed and several ways of solving it are proposed. Three criteria are provided in the paper, and these are used in the development of a modified line expansion algorithm. The modified algorithm is not only fast but also consumes less memory in two layer routing situations. Based on this algorithm, a Fortran printed circuit board routing system is built that can solve two layer routing problems with up to 2600 connection lines on a microcomputer with 64 kbyte RAM.

Hierarchical Loose Routing for Gate Arrays

Abstract: In this paper, we present a new, quasi-parallel approach to the loose routing problem for gate array LSI design. It is based on a new modeling for the decomposition problem of each net using a compact net graph which maps sets of feed-throughs instead of individual ones. The loose routing is done by calculation of a minimum spanning tree in this net graph and by a proper embedding of the tree as a set of single-channel subnets and feed-throughs. Moreover, a hierarchical approach is proposed, leading to a quasi-parallel embedding of all nets. It also allows different routing priorities for single connections within multiterminal nets. The hierarchical loose routing concept presented here is implemented in the fully integrated gate array design system MEGA and has been successfully tested on several industrial design examples.

Packet routing algorithms for integrated switching networks

Abstract: Repeated studies have shown that a single switching technique, either circuit or packet switching, cannot optimally support a heterogeneous traffic mix composed of voice, video and data. Integrated networks support such heterogeneous traffic by combining circuit and packet switching in a single network. To manage the statistical variations of network traffic, we introduce a new, adaptive routing algorithm called hybrid, weighted routing. Simulations show that hybrid, weighted routing is preferable to other adaptive routing techniques for both packet switched networks and integrated networks.

Evaluation of Point-to-Point Network Routing Algorithms

Abstract: A sampling of routing algorithms is evaluated through simulation. The algorithms selected are random walk, fixed directory, split traffic, isolated shortest queue (hot potato) and backward learning. Backward learning exhibited the most desirable characteristics, approaching fixed directory routing in delay and path length, while adapting to link failures.

A New Approach to Hierarchical Routing in Large Networks

Abstract: The overhead of an adaptive routing algorithm becomes prohibitive in a network with numerous nodes (in the order of hundreds or more) and a flat organization. In this paper, we present and analyze a new hierarchical routing algorithm for large networks. The algorithm is based on (1) the definition and maintenance of a hierarchical addressing scheme that is in turn based on the names of nodes that are well known in the network or within regions of the network, and (2) an extension of a new distributed routing algorithm first proposed by the author for flat networks.

An adaptive routing method for computer networks by electric‐circuit modeling

Abstract: The computer network and multiprocessor system have been developed and studied. They are based on a network composed of nodes containing processors, aiming at the improvement of performance by distributed processing as well as the improvement of reliability by resource distribution. To realize high system performance, adequate routing and flow controls are required in the communication of information among nodes. This paper proposes a new routing control scheme to be used in the packet communication in the computer network or multiprocessor system. The scheme is called potential routing, which models the computer network by an electric circuit, and the packet routing from the source node to the destination node is performed to the potential difference between the adjacent nodes. The node potential is determined first by Kirchhoff's law and is modified dynamically according to the traffic situation during the routing procedure, providing an adequate criterion for the routing. The proposed scheme has a feature in that ping-pong and loop phenomena, which cause traffic congestion, are not produced in principle. It was verified by simulation that the transmission delay is reduced when the traffic is high or unbalanced.