List decoding

About: List decoding is a research topic. Over the lifetime, 7251 publications have been published within this topic receiving 151182 citations.

Bidirectional sequential decoding

Abstract: The main drawback of sequential decoding is the variability of its decoding effort which could cause decoding erasures. We propose and analyze an efficient bidirectional sequential decoding (BSD) technique to alleviate this drawback. In the proposed BSD, two decoders are used; one is called a forward decoder (FD), and is used to search the tree from the forward direction; while the other is called a backward decoder (BD), and is used for the backward search of the tree. Forward decoding and backward decoding are performed simultaneously, and stop whenever the FD and BD merge at a common encoder state somewhere in the tree. The relationships between backward coding and forward coding are examined in detail. Good rate 1/2 convolutional codes, with memory m ranging from 2 to 25, suitable for bidirectional decoding found through extensive computer search, are provided. These codes possess the same distance properties from both forward and backward directions. It is found, by means of extensive computer simulations as well as a heuristic argument, that the advantage of the BSD appears as a substantial decrease of the computational variability of the sequential decoding. Our findings suggest that the Pareto exponent of unidirectional sequential decoding (USD) can be practically doubled by using BSD.

Bit-interleaved space-time coded modulation with iterative decoding

Abstract: Bit-interleaved space-time coded modulation (BI-STC), which combines serial concatenation of bit-interleaved coded modulation (BICM) with space-time block codes, can effectively exploit the available diversity in space and time under various fading conditions. In this letter, we propose to use iterative decoding to further improve the performance of BI-STC by exploiting the concatenating structure of the codes. The decoding metric is therefore modified to fit for the iterative process, and the derived error bounds suggest that set-partition labeling instead of gray labeling should be used when considering iterative decoding.

Low-complexity, full-diversity space-time-frequency block codes for MIMO-OFDM

Abstract: We present a new class of space-time-frequency block codes (STFBC) for multiantenna orthogonal frequency division multiplexing (MIMO-OFDM) transmissions over frequency selective Rayleigh fading channels. We show that these codes admit symbol-by-symbol decoding (decoupled decoding) when the number of nonzero taps of the channel impulse response is equal to two and they admit reduced complexity (1/2 of that of known schemes) for more than two channel taps. We also present simulation results to show that our codes perform better than the known codes.

Efficient memory mapping of a huffman coded list suitable for bit-serial decoding

Abstract: What is disclosed is a method that consists of constructing a bit-serial decoding table for a list of variable length codewords without the use of a binary decoding tree, and decoding using the decoding table, in a bit serial fashion, a bitstream encoded using those variable length codewords.

FPGA design of high throughput LDPC decoder based on imprecise Offset Min-Sum decoding

Abstract: This paper first proposes two new LDPC decoding algorithms that may be seen as imprecise versions of the Offset Min-Sum (OMS) decoding: the Partially OMS, which performs only partially the offset correction, and the Imprecise Partially OMS, which introduces a further level of impreciseness in the check-node processing unit. We show that they allow significant reduction in the memory (25% with respect to the baseline) and interconnect, and we further propose a cost-efficient check-node unit architecture, yielding a cost reduction of 56% with respect to the baseline. We further implement FPGA-based layered decoder architectures using the proposed algorithms as decoding kernels, for a (3, 6)-regular Quasi-Cyclic LDPC code of length 1296 bits, and evaluate them in terms of cost, throughput and decoding performance. Implementation results on Xilinx Virtex 6 FPGA device show that they can achieve a throughput between 1.95 and 2.41 Gbps for 20 decoding iterations (48% to 83% increase with respect to OMS), while providing decoding performance close to the OMS decoder, despite the impreciseness introduced in the processing units.