List decoding

About: List decoding is a research topic. Over the lifetime, 7251 publications have been published within this topic receiving 151182 citations.

Reduced complexity Schnorr-Euchner decoding algorithms for MIMO systems

Abstract: A new reduced-complexity Schnorr-Euchner decoding algorithm is proposed in this letter for uncoded multi-input multi-output systems with q-QAM (q=4,16,...) modulation. Furthermore, a Fano-like metric bias is introduced to the algorithm from the perspective of sequential decoding, as well as an early termination technique. Simulation results show that these modifications reduce the algorithm complexity efficiently, with only a small degradation in bit error rate at high signal to noise ratios.

Algebraic decoding of the (32, 16, 8) quadratic residue code

Abstract: An algebraic decoding algorithm for the 1/2-rate (32, 16, 8) quadratic residue (QR) code is found. The key idea of this algorithm is to find the error locator polynomial by a systematic use of the Newton identities associated with the code syndromes. The techniques developed extend the algebraic decoding algorithm found recently for the (32, 16, 8) QR code. It is expected that the algebraic approach developed here and by M. Elia (1987) applies also to longer QR codes and other BCH-type codes that are not fully decoded by the standard BCH decoding algorithm. >

Applications of list decoding to tracing traitors

Abstract: We apply results from algebraic coding theory to solve problems in cryptography, by using recent results on list decoding of error-correcting codes to efficiently find traitors who collude to create pirates. We produce schemes for which the traceability (TA) traitor tracing algorithm is very fast. We compare the TA and identifiable parent property (IPP) traitor tracing algorithms, and give evidence that when using an algebraic structure, the ability to trace traitors with the IPP algorithm implies the ability to trace with the TA algorithm. We also demonstrate that list decoding techniques can be used to find all possible pirate coalitions. Finally, we raise some related open questions about linear codes, and suggest uses for other decoding techniques in the presence of additional information about traitor behavior.

Constructions of Rank Modulation Codes

Abstract: Rank modulation is a way of encoding information to correct errors in flash memory devices as well as impulse noise in transmission lines. Modeling rank modulation involves construction of packings of the space of permutations equipped with the Kendall tau distance. As our main set of results, we present several general constructions of codes in permutations that cover a broad range of code parameters. In particular, we show a number of ways in which conventional error-correcting codes can be modified to correct errors in the Kendall space. Our constructions are nonasymptotic and afford simple encoding and decoding algorithms of essentially the same complexity as required to correct errors in the Hamming metric. As an example, from binary Bose-Chaudhuri-Hocquenghem codes, we obtain codes correcting t Kendall errors in n memory cells that support the order of n!/(log2n!)t messages, for any constant t=1,2,.... We give many examples of rank modulation codes with specific parameters. Turning to asymptotic analysis, we construct families of rank modulation codes that correct a number of errors that grows with n at varying rates, from Θ(n) to Θ(n2). One of our constructions gives rise to a family of rank modulation codes for which the tradeoff between the number of messages and the number of correctable Kendall errors approaches the optimal scaling rate.

Sliced Message Passing: High Throughput Overlapped Decoding of High-Rate Low-Density Parity-Check Codes

Abstract: The efficient implementation of high-rate high-throughout low-density parity-check (LDPC) code decoding presents challenges to both fully parallel decoding and memory-sharing partially parallel decoding schemes. In this paper, a new decoding scheme, sliced message passing (SMP), is introduced. The key idea is to slice the total set of N variable-to-check messages into equal-sized p chunks, then to perform check-node computation sequentially chunk by chunk. This new decoding scheme can break the sequential tie between the check- and variable-node update stages and thus greatly improve the throughput. The hardware architectures of SMP decoding are introduced. Each check-node processing unit of the proposed register-based architecture has only c/p inputs instead of c inputs. By remapping the variable-node and check-node processing unit decoding blocks, the optimized SMP decoding units can reduce the overall hardware cost, shorten the critical-path delay, and improve the hardware-usage efficiency. An optimized SMP decoder has been further implemented for a 2048-bit (6, 32) LDPC decoder of the emerging IEEE 10 GBase-T standard in an IBM CMOS 90-nm process. Implementation results from synthesis and post layout simulation have shown the effectiveness of the proposed SMP scheme.