Lithography

About: Lithography is a research topic. Over the lifetime, 23507 publications have been published within this topic receiving 348321 citations.

Fabrication of large area 100 nm pitch grating by spatial frequency doubling and nanoimprint lithography for subwavelength optical applications

Abstract: In this article we report on the fabrication of 100 nm pitch gratings over a large area (∼10 cm2) using a simple, low-cost, fast process. This method includes (1) generation of the grating pattern using interferometric lithography and spatial frequency doubling and (2) pattern replication using nanoimprint lithography. The form birefringence of a 100 nm pitch Si grating was studied using ellipsometry. Measurements show an index difference of Δn>0.9 at a wavelength of 632.8 nm. The experimental data are in good agreement with effective medium theory. This indicates the possibility of using these structures for wave plates and other subwavelength optical devices operating in the visible.

High aspect subdiffraction-limit photolithography via a silver superlens.

Abstract: Photolithography is the technology of choice for mass patterning in semiconductor and data storage industries. Superlenses have demonstrated the capability of subdiffraction-limit imaging and been envisioned as a promising technology for potential nanophotolithography. Unfortunately, subdiffraction-limit patterns generated by current superlenses exhibited poor profile depth far below the requirement for photolithography. Here, we report an experimental demonstration of sub-50 nm resolution nanophotolithography via a smooth silver superlens with a high aspect profile of ~45 nm, as well as grayscale subdiffraction-limit three-dimensional nanopatterning. Theoretical analysis and simulation show that smooth interfaces play a critical role. Superlens-based lithography can be integrated with conventional UV photolithography systems to endow them with the capability of nanophotolithography, which could provide a cost-effective approach for large scale and rapid nanopatterning.

Photon-beam lithography reaches 12.5nm half-pitch resolution

Abstract: We have printed dense line/space patterns with half-pitches as small as 12.5nm in a negative-tone calixarene resist using extreme ultraviolet (EUV) interference lithography. The EUV interference setup which is based on transmission diffraction gratings is illuminated with spatially coherent radiation from a synchrotron source. The results show the extendibility of EUV lithography to printing features measuring less than 15nm in size. We discuss the potential impact of effects such as photoelectron blur and shot noise in high-resolution EUV lithography.

Interferometric lithography of sub‐micrometer sparse hole arrays for field‐emission display applications

Abstract: Interferometric lithography, the use of interactions between coherent laser beams to define sub‐ wavelength patterns, is well adapted to the periodic nature of field‐emitter structures. Techniques to fabricate sparse (hole diameter to pitch ratio of 1:3 or larger) emitter arrays to improve reliability and lifetime are presented. These include: multiple exposures at two different pitches; integration of interferometric and optical imaging lithography; and various multiple beam techniques that both provide a sparse array and result in a two dimensional pattern in a single exposure. Moire alignment techniques are demonstrated to provide a simple process for aligning multiple levels. Manufacturing related issues such as process latitude and photoresist profiles and their suitability for subsequent processing are also discussed. Exposure‐dose process control using latent image monitoring is demonstrated.

Patterning with spacer for expanding the resolution limit of current lithography tool

Abstract: Double Exposure Technology (DET) is one of the main candidates for expanding the resolution limit of current lithography tool. But this technology has some bottleneck such as controlling the CD uniformity and overlay of both mask involved in the lithography process. One way to solve this problem and still maintain the resolution advantage of DET is using spacers. Patterning with a spacer not only expands the resolution limit but also solves the problems involved with DET. This method realizes the interconnection between the cell and peripheral region by "space spacer" instead of "line spacer" as usually used. Spacer process involves top hard mask etch, nitride spacer, oxide deposition, CMP, and nitride strip steps sequentially. Peripheral mask was additionally added to realize the interconnection region. With the use of spacers, it was possible to realize the NAND flash memory gate pattern with less than 50nm feature only using 0.85NA (ArF).