Lithography

About: Lithography is a research topic. Over the lifetime, 23507 publications have been published within this topic receiving 348321 citations.

Electron beam lithography for 0.13 μm manufacturing

Abstract: General requirements for the use of electron beam lithography in direct write manufacturing of silicon integrated circuits are discussed. 50 keV is suggested as an optimum beam energy, since this is the minimum beam energy that can achieve high aspect ratio structures (4:1) in single layer resists in a manufacturing environment. Higher beam energies result in an inefficient exposure process requiring larger currents; this combination will lead to excessive resist and wafer heating. Lower voltages will require the use of top surface imaging or multilayer resists, which have concerns of processing complexity, resist charging, and defects. At 50 keV, some form of proximity correction is required to achieve reasonable control of critical dimensions. While one of the principle arguments for low voltage lithography is that it avoids the need for proximity correction, proximity correction is a solvable problem for large chips and is therefore a less risky approach than developing a reliable surface imaging resis...

Lithography computer aided design technology for embedded memory in logic

Abstract: We have developed an optical proximity effect correction (OPC) flow for both, the repetitive memory cell patterns by a simulation-based method and for the random logic application specific IC (ASIC) patterns by a rule-based method. Application results for a 0.28 µm static random access memory (SRAM) cell and 0.25 µm ASIC devices have shown that correction time and final data size were feasible for conventional layout design flow and mask fabrication. Also, our system has achieved significant improvement with respect to pattern printing fidelity between designed and printed resist patterns. In addition to this, an automatic alternative phase shift mask (PSM) pattern layout tool has been developed. Using the tool with a double exposure method, 0.16 µm gate patterns for both logic and dynamic random access memory (DRAM) have been obtained with a positive photoresist. The developed lithography computer aided design (CAD) technology has improved the accuracy of pattern formation for state of the art device fabrication. The fabricated patterns have satisfied the required linewidth accuracy, within ±10% of the design value, ones under the practical exposure-focus window.

Field emitter array mask patterning using laser interference lithography

Abstract: We have fabricated uniform arrays of 120‐nm‐diam dot masks on 300 nm centers using laser interference lithography. Chrome, cobalt, nickel, and germanium dot arrays have been fabricated. The density of these arrays is ≳109 dots/cm2. The standard deviation of the average dot diameter is 7.4% over a 5‐cm‐diam silicon substrate. The center‐to‐center spacing of the dot mask is determined by the laser wavelength and interference angle. Some control over the dot diameter is possible by varying the angle of the substrate during the metal deposition prior to liftoff. We have used a reactive ion etch with these metal dot masks to form single crystal silicon pedestals demonstrating that these structures are suitable for self‐aligned gated field emitter array fabrication.

The physics of submicron lithography

Abstract: Forming Electron Beams of Submicron Cross Section. The Physics of the Interactions Between Fast Electrons and Matter. The Physics of Ion Beam Lithography. The Physics of X-Ray Microlithography. Optical Lithography. Proceedures for Processing Exposed Resist Films and Resist Mask Topography. Index.

Enhanced polymeric lithography resists via sequential infiltration synthesis

Abstract: Etch resistance of two commonly used lithography resists is increased significantly by sequential infiltration synthesis (SIS). Exposing films to trimethyl-aluminum and water with long dosage times infiltrates the bulk of the film with alumina, which renders them dramatically more resistant to plasma etching with no degradation to the patterns. Enhanced etch resistance eliminates the need for an intermediate hard mask and the concomitant costs and pattern fidelity losses. Moreover, by allowing for thinner resist films, this approach can improve the final pattern resolution.