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Logical effort
About: Logical effort is a research topic. Over the lifetime, 183 publications have been published within this topic receiving 2661 citations.
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01 Jan 1999TL;DR: In this article, the authors derived the method of logical effort from design examples and calculated the logical effort of gates, and then calibrated the model to achieve equal rising and falling delays.
Abstract: 1 The Method of Logical Effort 2 Design Examples 3 Deriving the Method of Logical Effort 4 Calculating the Logical Effort of Gates 5 Calibrating the Model 6 Asymmetric Logic Gates 7 Unequal Rising and Falling Delays 8 Circuit Families 9 Forks of Amplifiers 10 Branches and Interconnect 11 Wide Structures 12 Conclusions A Cast of Characters B Reference process parameters C Logical Effort Tools D Solutions
646 citations
11 Mar 2001
TL;DR: The GasP family of asynchronous circuits provides controls for simple pipelines, for branching and joining pipelines, with assurance of uniform gate delays permits use of self-resetting logic forms that have very low logical effort.
Abstract: The GasP family of asynchronous circuits provides controls for simple pipelines, for branching and joining pipelines, for round-robin scatter and gather for data dependent scatter and gather and for join on demand through arbitration. The family is designed so that each stage operates at the speed of a three-inverter ring oscillator Test chips in 0.35 micron technology exhibit throughput in excess of 1.5 giga data items per second (GDI/s). Between GasP pipeline stages a single wire carries both request and acknowledge messages, also recording the FULL or EMPTY state of each pipeline stage. GasP control circuits rely on careful choice of transistor widths to equalize the delay in logic gates. Assurance of uniform gate delays permits use of self-resetting logic forms that have very low logical effort.
265 citations
01 Jan 2016
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137 citations
TL;DR: This work presents an IEEE floating-point adder design that achieves a low latency by combining various optimization techniques such as a nonstandard separation into two paths, a simple rounding algorithm, unification of rounding cases for addition and subtraction, and sign-magnitude computation of a difference based on one's complement subtraction.
Abstract: We present an IEEE floating-point adder (FP-adder) design. The adder accepts normalized numbers, supports all four IEEE rounding modes, and outputs the correctly normalized rounded sum/difference in the format required by the IEEE Standard. The FP-adder design achieves a low latency by combining various optimization techniques such as: a nonstandard separation into two paths, a simple rounding algorithm, unification of rounding cases for addition and subtraction, sign-magnitude computation of a difference based on one's complement subtraction, compound adders, and fast circuits for approximate counting of leading zeros from borrow-save representation. We present technology-independent analysis and optimization of our implementation based on the Logical Effort hardware model and we determine optimal gate sizes and optimal buffer insertion. We estimate the delay of our optimized design at 30.6 FO4 delays for double precision operands (15.3 FO4 delays per stage between latches). We overview other IEEE FP addition algorithms from the literature and compare these algorithms with our algorithm. We conclude that our algorithm has shorter latency (-13 percent) and cycle time (-22 percent) compared to the next fastest algorithm.
106 citations
TL;DR: The proposed design methodology permits to optimize FFs under constraints within the energy-delay space through extensive adoption of the Logical Effort method, which also allows for defining the bounds in the design space search.
Abstract: In this paper, a general and complete design flow for nanometer flip-flops (FFs) is presented. The proposed design methodology permits to optimize FFs under constraints within the energy-delay space through extensive adoption of the Logical Effort method, which also allows for defining the bounds in the design space search. Transistors sizing is rigorously discussed by referring to cases that occur in practical designs. Appropriate metrics with clear physical meaning are proposed and various interesting properties are derived from circuit analysis. A well-defined design procedure is derived that can be easily automated with commercial CAD tools. In contrast to previous works, the impact of local interconnections is explicitly accounted for in the design loop, as is required in nanometer CMOS technologies. A case study is discussed in detail to exemplify the application of the proposed methodology. Extensive simulations for a typical FF in a 65-nm CMOS technology are presented to show the whole design procedure and validate the underlying assumptions.
94 citations