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Topic

Low-dropout regulator

About: Low-dropout regulator is a(n) research topic. Over the lifetime, 9101 publication(s) have been published within this topic receiving 117117 citation(s). The topic is also known as: LDO regulator.
Papers
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Patent
Milton E. Wilcox1, Randy G Flatness1Institutions (1)
22 Mar 1994-
Abstract: A circuit and method for controlling a switching voltage regulator having (1) a switch including one or more switching transistors and (2) an output adapted to supply current at a regulated voltage to a load including an output capacitor. The circuit and method generates a control signal to turn said one or more switching transistors OFF under operating conditions when the voltage at the output is capable of being maintained substantially at the regulated voltage by the charge on the output capacitor. Such a circuit and method increases the efficiency of the regulator circuit particularly at low average current levels.

672 citations


Journal ArticleDOI
Peter Hazucha1, Tanay Karnik1, B.A. Bloechel1, C. Parsons1  +2 moreInstitutions (1)
Abstract: We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the regulator enables a 90 mV/sub P-P/ output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small regulator area of 0.008 mm/sup 2/ and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm/sup 2/.

471 citations


Journal ArticleDOI
Abstract: Detailed models are presented for the stationary and synchronous sine-triangle current regulators. Analytical and test results are compared for purposes of model verification and regulator evaluation. The results demonstrate the limitations of the two most often used current regulators and the robustness of the synchronous current regulator. The stationary sine-triangle and hysteretic current regulators are shown to have steady-state characteristics that depend on slip, operating frequency, and motor impedance. In contrast the synchronous regulator, because it lacks these dependencies, exhibits ideal steady-state current regulator characteristics without sacrificing bandwidth. Moreover, the complexities traditionally associated with the synchronous regulator are overcome with a simple equivalent implementation.

460 citations


Patent
John R. Spencer1Institutions (1)
30 Jan 2009-
Abstract: Regulating voltages At least some of the illustrative embodiments are systems including a switching circuit configured to produce an intermediate voltage signal from an input voltage signal, and a first voltage regulator coupled the switching circuit and configured to produce a first regulated voltage signal from the intermediate voltage signal The switching circuit is configured to create the intermediate voltage signal based on a switching signal having a duty cycle, and wherein the duty cycle of the switching signal is open-loop with respect the intermediate voltage signal and the first regulated voltage signal

446 citations


Journal ArticleDOI
Abstract: This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (AC) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-mum CMOS technology, consuming only 65 muA of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures.

446 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20221
202151
2020121
2019136
2018139
2017259