Topic
Low-dropout regulator
About: Low-dropout regulator is a research topic. Over the lifetime, 9101 publications have been published within this topic receiving 117117 citations. The topic is also known as: LDO regulator.
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Papers
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TL;DR: In this paper, the impact of supply voltage, input DC level, transistor sizing, and temperature on the input offset voltage was investigated for a latch-type voltage sense amplifier with a high-impedance differential input stage.
Abstract: A quantitative yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It investigates the impact of supply voltage, input DC level, transistor sizing, and temperature on the input offset voltage. The input DC level turns out to be most significant. Also, an analytical expression for the sensing delay is derived which shows low sensitivity on the input DC bias voltage. A figure of merit indicates that an input dc level of 0.7 V/sub DD/ is optimal regarding speed and yield. Experimental results in 130-nm CMOS technology confirm that the yield can be significantly improved by lowering the input DC voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19 to 8.5 mV without affecting the delay.
450 citations
Patent•
30 Jan 2009TL;DR: In this paper, a switching circuit is configured to create the intermediate voltage signal based on a switching signal having a duty cycle, and wherein the duty cycle of the switching signal is open-loop with respect the intermediate signal and the first regulated voltage signal.
Abstract: Regulating voltages At least some of the illustrative embodiments are systems including a switching circuit configured to produce an intermediate voltage signal from an input voltage signal, and a first voltage regulator coupled the switching circuit and configured to produce a first regulated voltage signal from the intermediate voltage signal The switching circuit is configured to create the intermediate voltage signal based on a switching signal having a duty cycle, and wherein the duty cycle of the switching signal is open-loop with respect the intermediate voltage signal and the first regulated voltage signal
446 citations
TL;DR: In this article, a distributed adaptive droop mechanism is proposed for secondary/primary control of dc microgrids, where the conventional secondary control that adjusts the voltage set point for the local droop mechanisms is replaced by a voltage regulator.
Abstract: A distributed-adaptive droop mechanism is proposed for secondary/primary control of dc microgrids. The conventional secondary control that adjusts the voltage set point for the local droop mechanism is replaced by a voltage regulator. A current regulator is also added to fine-tune the droop coefficient for different loading conditions. The voltage regulator uses an observer that processes neighbors' data to estimate the average voltage across the microgrid. This estimation is further used to generate a voltage correction term to adjust the local voltage set point. The current regulator compares the local per-unit current of each converter with the neighbors' on a communication graph and, accordingly, provides an impedance correction term. This term is then used to update the droop coefficient and synchronize per-unit currents or, equivalently, provide proportional load sharing. The proposed controller precisely accounts for the transmission/distribution line impedances. The controller on each converter exchanges data with only its neighbor converters on a sparse communication graph spanned across the microgrid. Global dynamic model of the microgrid is derived with the proposed controller engaged. A low-voltage dc microgrid prototype is used to verify the controller performance, link-failure resiliency, and the plug-and-play capability.
372 citations
23 Jul 2007
TL;DR: In this paper, a low-dropout regulator (LDO) with an impedance-attenuated buffer for driving the pass device was proposed. But the buffer was not used to reduce the output voltage.
Abstract: This paper presents a low-dropout regulator (LDO) for portable applications with an impedance-attenuated buffer for driving the pass device. Dynamically-biased shunt feedback is proposed in the buffer to lower its output resistance such that the pole at the gate of the pass device is pushed to high frequencies without dissipating large quiescent current. By employing the current-buffer compensation, only a single pole is realized within the regulation loop unity-gain bandwidth and over 65deg phase margin is achieved under the full range of the load current in the LDO. The LDO thus achieves stability without using any low-frequency zero. The maximum output-voltage variation can be minimized during load transients even if a small output capacitor is used. The LDO with the proposed impedance-attenuated buffer has been implemented in a 0.35-mum twin-well CMOS process. The proposed LDO dissipates 20-muA quiescent current at no-load condition and is able to deliver up to 200-mA load current. With a 1-muF output capacitor, the maximum transient output-voltage variation is within 3% of the output voltage with load step changes of 200 mA/100 ns.
353 citations
TL;DR: In this article, a voltage lift technique has been successfully employed in design of DC/DC converters, e.g., four series Luo converters. However, the output voltage increases in arithmetic progression.
Abstract: The voltage lift technique has been successfully employed in design of DC/DC converters, e.g., four series Luo converters. However, the output voltage increases in arithmetic progression. This paper introduces a novel approach-super-lift technique that implements the output voltage increasing in geometric progression. It effectively enhances the voltage transfer gain in power law.
349 citations