Low-k dielectric

About: Low-k dielectric is a research topic. Over the lifetime, 1302 publications have been published within this topic receiving 23254 citations.

Origin of the dielectric dead layer in nanoscale capacitors

Abstract: New theoretical work nails down the microscopic origin of 'dead layers' in nanometre-scale capacitors and demonstrates that it is an intrinsic effect. The results provide practical guidelines for minimizing the deleterious effects of the dielectric dead layer, for example regarding the choice of electrode. Capacitors are a mainstay of electronic integrated circuits and devices, where they perform essential functions such as storing electrical charge, and blocking direct current while allowing alternating currents to propagate. Because they are often the largest components in circuits, extensive efforts are directed at reducing their size through the use of high-permittivity insulators such as perovskite-structure SrTiO3 (refs 1, 2), which should provide more capacitance per unit area of device. Unfortunately, most experiments on thin-film SrTiO3 capacitors have yielded capacitance values that are orders of magnitude smaller than expected3. The microscopic origin of this reduced capacitance, which is often discussed in terms of a low-permittivity interfacial ‘dead layer’4, is not well understood. Whether such a dead layer exists at all, and if so, whether it is an intrinsic property of an ideal metal–insulator interface or a result of processing issues such as defects and strains, are controversial questions. Here we present fully ab initio calculations of the dielectric properties of realistic SrRuO3/SrTiO3/SrRuO3 nanocapacitors, and show that the observed dramatic capacitance reduction is indeed an intrinsic effect. We demonstrate the existence of a dielectric dead layer by calculating the dielectric profile across the interface and analyse its origin by extracting the ionic and electronic contributions to the electrostatic screening. We establish a correspondence between the dead layer and the hardening of the collective SrTiO3 zone-centre polar modes, and determine the influence of the electrode by repeating our calculations for Pt/SrTiO3/Pt capacitors. Our results provide practical guidelines for minimizing the deleterious effects of the dielectric dead layer in nanoscale devices.

Integrated low k dielectrics and etch stops

Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects

Method of depositing a low k dielectric with organo silane

Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organo silane film can also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organo silane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organo silane film is produced by reaction of methyl silane, CH3SiH3, and N2O.

Low-k dielectric materials

Abstract: Performance improvements in microelectronic integrated circuits (ICs) over the past few decades have, for the most part, been achieved by increasing transistor speed, reducing transistor size, and packing more transistors onto a single chip. Smaller transistors work faster, so ICs have become faster and more complex. An emerging factor that may disrupt this trend is the slowing speed of signal propagation within the chip. Signal delays, caused by the interconnection wiring, increase with each generation of scaling and may soon limit the overall performance of the integrated system.