Showing papers on "Low-pass filter published in 1994"

Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages

Abstract: The implementation of analog CMOS circuits that operate in the very low power supply voltage range (1 V to 2 V) becomes more important nowadays. Most accurate filter circuits are designed in the switched-capacitor technique. The existing design techniques require, however, the on-chip generation of a higher voltage by means of a voltage multiplier. In this paper, a novel technique, derived from the standard switched-capacitor technique, is presented. It is called switched-opamp because it is based on the replacement of the critical switches with opamps which are turned on and off. This technique results in a true, very low voltage operation without the need for voltage multipliers. As an example, a second order lowpass switched-capacitor filter is implemented in the switched-opamp technique. This filter operates with only a 1.5 V power supply. It is realized in a 2.4-/spl mu/m CMOS process with V/sub T/=/spl plusmn/0.9 V. It has a measured total harmonic distortion of -60 dB for a signal swing of 600 mV/sub ptp/ and a powerdrain of only 110 /spl mu/W. >

Optimum loop filter in hybrid coders

Abstract: Examines the role of the loop/interpolation filter in the motion compensation loop of hybrid coders. Using the Wiener filtering concept and the statistical model developed by Chen and Pang (1992), the optimum filter that minimises the prediction error has been found. The result is expressed in an explicit form in terms of a correlation parameter, /spl rho/ and an inaccuracy parameter, /spl alpha/. It explains many current practices in MPEG and H.261 coders, as well as the leakage predictor, 3-tap versus 8-tap filters and other related issues. The analysis shows that minimum bit rate can only be achieved if the loop filter matches the statistical characteristic of the motion-compensated signal. Furthermore, since the motion noise characteristic could be very different in the horizontal and vertical direction for many sequences, the decision to deploy the optimum filter should be made separately in the two directions. The paper also derives the scalar loop filter in DCT domain. The scalar filter is sub-optimal, but it requires less computational load than the spatial domain filter (64 versus 484 multiplications per 8/spl times/8 block). Experiments show that it performs almost as efficiently as the optimum 3-tap spatial domain filter, thus ascertaining that its performance has not been significantly compromised by the scalar requirement. Experimental simulations on test sequences confirm the theoretical optimum results, and indirectly show that the simple statistical model used in the derivation is adequate. >

A Remez exchange algorithm for orthonormal wavelets

Abstract: Compactly supported orthonormal wavelets are obtained from two-band paraunitary FIR filter bank solutions, with the additional "flatness" constraint that the low-pass filter should have K zeroes at half the sampling frequency. This constraint is set to obtain "regular" wavelets. However, it is somewhat in contradiction with the usual requirement for good frequency selectivity, since it is well known that maximally flat filters (yielding Daubechies wavelets) have poor frequency selectivity. An efficient procedure for designing maximally frequency selective filter banks under a given flatness constraint is described in this paper. Classical Remez exchange algorithms, based on the alternation theorem, can no longer be used in this case. Linear programming techniques are capable of setting up constraints of this type, but require high memory storage and computation time. First, a variation of the alternation theorem adapted to this new situation is derived. Then, a modified Remez exchange algorithm for the design of "wavelet" filters is derived in the spirit of the Parks-McClellan algorithm. The efficiency of the algorithm is greatly improved as compared to linear programming techniques, and optimum filters are generally obtained after 3 or 4 iterations. A MATLAB listing is provided. >

Delta-sigma ADC with multi-stage decimation filter and gain compensation filter

Abstract: An analog-to-digital conversion circuit is described which includes a front end sigma-delta modulator circuit, a multi-stage digital decimation filter circuit, and a digital compensation filter circuit. An overrange detect circuit is also provided.

Frequency-response masking approach for digital filter design: complexity reduction via masking filter factorization

Abstract: It has been reported in several recent publications that the frequency response masking technique is eminently suitable for synthesizing filters with very narrow transition-width The major advantages of the frequency response masking approach are that the resulting filter has a very sparse coefficient vector and that the resulting filter length is only slightly longer than that of the theoretical (Remez) minimum The system of filters produced by the frequency response masking technique consists of a sparse coefficient filter with periodic frequency response and one or more pairs of masking filters Each pair of the masking filters consist of two filters whose frequency responses are similar except at frequencies near the band-edges In this paper, we present three methods for reducing the complexity of the masking filters The success of our technique is due to the fact that each pair of the masking filters can be realized as a cascade of a common subfilter and a pair of equalizers >

A high-quality analog oscillator using oversampling D/A conversion techniques

Abstract: This paper describes a high-quality analog oscillator for low-frequency applications, which uses a combination of over-sampling and delta-sigma modulation. With the exception of a lowpass filter and a 1-bit D/A, the proposed circuit is entirely digital, providing accurate control over the oscillation frequency and amplitude. At the core of the oscillator is a digital simulation of an LC-tank circuit consisting of two cascaded integrators. This arrangement guarantees oscillation by constraining the poles of the resonator to locations on the z-plane unit-circle, even in a finite-precision implementation. To minimize circuit complexity, the entire oscillator is operated at the oversampled rate, thereby eliminating the associated interpolation filter. Furthermore, the incorporation of a delta-sigma modulator inside the resonator loop leads to a very efficient implementation requiring only 4 multi-bit adders and a 2-input multiplexor. The desired analog signal may be recovered by lowpass filtering the 1-bit output of the delta-sigma modulator. Experiments performed thus far have indicated an effective dynamic range exceeding 80 dB. >

Analysis of fibre transfer function and determination of receiver frequency response for dispersion supported transmission

Abstract: It is shown that a frequency modulated optical transmitter at 1.5 µm in conjunction with a standard singlemode fibre can have highpass transfer characteristics. Equalising this frequency response, the characteristics of the receiver lowpass filter can be determined that are required for the method of dispersion supported transmission.

Voltage-mode notch, lowpass and bandpass filter using current-feedback amplifiers

Abstract: A voltage-mode filter employing three current-feedback amplifiers, two grounded capacitors and three floating resistors is presented. The proposed circuit offers the following advantages: realisation of notch, lowpass and bandpass signals from the same configuration, no requirements for component matching conditions, orthogonal control of ωo and Q, and the use of two grounded capacitors ideal for IC implementation, and low active and passive sensitivities and cascadability.

Double sampled biquad switched capacitor filter

Abstract: A biquad switched capacitor filter is preferably utilized as the output filter in a sigma delta digital-to-analog converter. The switched capacitor filter uses a cross-coupled switched capacitor circuit which delivers charge to the capacitors on both phases of the clock. As a result, the sizes of the capacitors can be reduced by a factor of two, while delivering the same charge as a single sampling circuit. By using the cross-coupled switching circuit everywhere in the filter, the sensitivity to capacitor mismatches is substantially reduced. The clock phases applied to the stages of the filter are alternated so that there is a one clock cycle delay around each loop containing two filter stages, thereby insuring the stability of the filter.

Frequency content of whole body gait kinematic data

Abstract: The authors analyzed the frequency content of camera image plane data for markers on each body segment during gait. For each segment, they determined the low-pass filter cutoff frequency that balanced the amount of signal distortion and the amount of random noise passed. The frequency content of the data as measured by the cutoff frequency differed for different body segments, being higher for the lower limb segments and lower for the head. This result supports the hypothesis that the frequency content of the kinematics of segments decreases caudal to rostral. >

A zero crossing algorithm for the estimation of the frequency of a single sinusoid in white noise

Abstract: Presents a new algorithm for the estimation of the frequency of a single sinusoid in white noise, based on the computation of the interval between zero crossings. It is shown that for a high signal-to-noise ratio, the output error spectrum is concentrated in the high-frequency region. Theoretically, the desired precision can be achieved using a proper low-pass filter. The spectrum of the error due to the interpolation of the zero crossing is computed. Simulation results show that a precision of 10/sup -7/-10/sup -8/ can be obtained with modest computational effort. >

High spectral purity digital waveform synthesizer

Abstract: A digital waveform synthesizer (10) comprises a direct digital synthesizer (12) for providing a digitally synthesized input frequency signal. Further provided is a reference frequency generator (25) for providing clock and predetermined frequency reference signals. An upconverter and divider circuit (18, 18a) is coupled to the direct digital synthesizer (12) for upconverting and dividing the synthesized input frequency signal to provide a divided synthesized frequency signal. Said upconverter and divider circuit (18, 18a) comprises a mixer (14) having an input coupled to the direct digital synthesizer (12) for receiving the synthesized input frequency signal, and having a second input coupled to the reference signal generator (25) for receiving a first predetermined reference frequency signal; a bandpass filter (15) coupled to the mixer (14), a divide by N divider circuit (16), where N is the divide number, coupled to the bandpass filter (15); and a low pass filter (17) coupled to the divide by N divider circuit (16). An output upconverter circuit (21) is coupled to the upconverter and divider circuit (18, 18a) and to the reference frequency generator (25) for upconverting the divided synthesized frequency signal to provide a desired upconverter synthesized output frequency signal.

Microstrip filter design using direct EM field simulation

Abstract: For the first time, we present minimax filter design with electromagnetic (EM) simulations driven directly by a gradient-based optimizer. Challenges of efficiency, discretization of geometrical dimensions, and continuity of optimization variables are overcome by a three-stage attack: 1) efficient on-line response interpolation with respect to geometrical dimensions of microstrip structures simulated with fixed grid sizes; 2) smooth and accurate gradient evaluation for use in conjunction with the proposed interpolation; and 3) storing the results of expensive EM simulations in a dynamically updated database. Simulation of a lowpass microstrip filter illustrates the conventional use of EM simulation for design validation. Design optimization of a double folded stub bandstop filter and of a millimeter-wave 26-40 GHz interdigital capacitor bandpass microstrip filter illustrates the new technique. >

Hybrid series active/parallel passive power line conditioner with controlled harmonic injection

Abstract: A power line conditioner includes an active filter coupled, in series, and a passive filter coupled, in parallel, to a three-phase power distribution network The three-phase power distribution network includes a voltage source that induces three-phase input currents at a first end of the three-phase power distribution network A load, circulating three-phase load currents, is positioned at a second end of the three-phase power distribution network The active filter controller of the invention uses synchronous transformations to identify selected harmonic reference components corresponding to individual harmonics of the three-phase load currents The selected harmonic reference components are multiplied by a predetermined factor corresponding to a permissible percentage of the individual harmonics that may be injected into the supply voltage This results in active filter reference signal components that are applied to the active filter In response to the active filter reference signal components, the active filter injects a permissible percentage of harmonics into the supply voltage so as to reduce the voltage distortion at the passive filter By reducing voltage distortion, the controlled injection of harmonics into the supply allows for a simplified passive filter design Consequently, the passive filter may be implemented as a power factor correction capacitor

An analog multi-tone signal generator for built-in-self-test applications

Abstract: This paper presents the design of an analog oscillator capable of generating multi-tone signals by encoding the information in an oversampled delta-sigma modulated bit-stream. With the exception of an imprecise lowpass filter, the proposed design is completely digital allowing accurate control of the amplitude, frequency, and phase of all sinusoids making up the multi-tone signal. Simulations and FPGA experiments performed to date have verified the performance of the proposed design which is envisioned to open new directions in the mixed analog/digital testing field.

Artificial neural network method and architecture adaptive signal filtering

Abstract: An architecture and data processing method for a neural network that can approximate any mapping function between the input and output vectors without the use of hidden layers. The data processing is done at the sibling nodes (second row). It is based on the orthogonal expansion of the functions that map the input vector to the output vector. Because the nodes of the second row are simply data processing stations, they remain passive during training. As a result the system is basically a single-layer linear network with a filter at its entrance. Because of this it is free from the problems of local minima. The invention also includes a method that reduces the sum of the square of errors over all the output nodes to zero (0.000000) in fewer than ten cycles. This is done by initialization of the synaptic links with the coefficients of the orthogonal expansion. This feature makes it possible to design a computer chip which can perform the training process in real time. Similarly, the ability to train in real time allows the system to retrain itself and improve its performance while executing its normal testing functions. Because the second synaptic link values represent the frequency spectrum of the signal appearing on a given output node, by training the ONN with all N sibling nodes and using only some of them in testing, we can create a low pass, a high pass or a band pass filter.

Near homodyne radio frequency receiver

Abstract: A radio frequency receiver and method for operating one is disclosed. The receiver includes a tuning unit, an inphase-quadrature (I/Q) mixer, and a calibrated image rejection processor. The tuning unit selectably tunes to a tuning frequency close but not equal to an input modulated radio frequency and creates thereby a periodic signal having the tuning frequency. The I/Q mixer convolves the modulated radio frequency signal with inphase and quadrature versions of the periodic signal and low pass filters the resultant signals. The calibrated image rejection processor corrects at least one of the filtered resultant signals and performs image rejection on the corrected signals.

Video signal processor and method for secondary images

Abstract: A processing unit (13) for providing secondary images in a video display system (10) in accordance with a choice of scaling ratios. The processing unit (13) scales the luminance component of an analog input signal by first using an analog low pass filter (22) for anti-aliasing, and then sampling (23) the data at a rate appropriate for the selected scaling ratio. The sampled data is processed by a digital filter (24), on a line-by-line basis, which provides weighted average values derived from the sampled data, on a line-by-line basis. A formatter (25) combines sampled chrominance data with the filtered luminance data, and selects lines for inclusion in the secondary image.

Arithmetic-free digital interpolation filter architecture

Abstract: A low precision Finite Impulse Response filter (FIR) is provided for filtering in a digital interpolation operation. The interpolation operation is comprised of two steps, a sampling rate conversion operation for interspersing zeroes between samples in an input sequence and a filtering step of filtering out images that result from this operation. The filtering operation utilizes a FIR filter that utilizes a low precision set of filter coefficients that are selected to tune the frequency response such that the low end frequency response including the pass band, the transition band, and the portion of the stop band immediately after the transition band provides a response equivalent to that commensurate with substantially higher precision FIR filter coefficients. A second, low pass filter section is provided for filtering the high frequency image energy at the output of the FIR filter to provide an overall filter response commensurate to that utilizing substantially higher precision FIR coefficients. The FIR filter coefficients utilized are restricted to the set of {-1, 0, +1} such that an arithmetic-free realization is provided wherein data is stored in a random access memory (68), with the non-zero coefficients for any interpolator output limited to a predetermined number. This predetermined number equals the maximum clock rate divided by the output sampling frequency. For each interpolator output, addresses of the associated data are stored in a ROM (72), which is operable to sequentially generate the addresses for accessing of data from a RAM (68). The sign is then changed, depending upon a sign change bit in the ROM (72), and then accumulated in an output accumulator (82). After all data is accessed from the RAM (68) for a given interpolator output, the accumulator (82) provides this output to the delta-sigma converter.

On the location error of curved edges in low-pass filtered 2-D and 3-D images

Abstract: The authors study the location error of curved edges in two- and three-dimensional images after analog and digital low-pass filtering. The zero crossing of a second derivative filter is a well-known edge localization criterion. The second derivative in gradient direction (SDGD) produces a predictable bias in edge location towards the centers of curvature while the linear Laplace filter produces a shift in the opposite direction. Their sum called PLUS (PLUS=Laplace+SDGD) leads to an edge detector that finds curved edges one order more accurately than its constituents. This argument holds irrespective of the dimension. The influence of commonly used low-pass filters (such as the PSF originating from diffraction limited optics using incoherent light (2-D), the Gaussian filter with variable cutoff point (D-D), and the isotropic uniform filter (D-D)) is studied. >

Interpolation filter with reduced set of filter coefficients

Abstract: An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise. A circuit determining the output to input sample rate ratios can also be provided to scale coefficient addresses and resulting output samples to allow for decimation. This circuit includes a form of digital hysteresis to eliminate noise. The ROM coefficients are reduced by relying on the symmetry of the impulse response of the interpolation filter and by utilizing a variable step size forward and backward linear interpolation.

Tuning circuit for an RC filter

Abstract: A tuning circuit (202) uses a precision current reference (Iref) along with an analog-to-digital converter (218) to produce a digital output (228) to represent variations of internal resistance values. The precision current reference (Iref) is fed to an internal tuning resistor (R210) in order to provide an analog voltage signal to the analog-to-digital converter (218). The analog voltage signal changes in accordance with the variations in the tuning resistor value over process and temperature. The digital output (228) controls programmable capacitor arrays (C220, C222) which are included in the tuning circuit (202) as well as in an active RC filter (208) whose bandwidth is controlled by the programmable capacitor arrays (C220, C222) and internal resistors (R212, R214, R216).

Hybrid series active, parallel passive, power line conditioner for harmonic isolation between a supply and a load

Abstract: The apparatus includes an active filter, coupled in series, and a passive filter, coupled in parallel, to a power distribution network. The power distribution network includes a voltage source that induces input currents at a first end of the power distribution network. Nonlinear loads and other conditions on the power distribution network cause unbalanced power signals. The active filter controller of the invention uses synchronous transformations on the input currents to identify a negative sequence fundamental signal and a positive sequence fundamental signal, while filtering all harmonic components within the input currents. The negative sequence fundamental signal and the positive sequence fundamental signal are combined to form an active filter reference signal which is applied to the active filter. In response to the active filter reference signal, the active filter operates as a current controlled harmonic voltage source, carrying only the fundamental current, while only injecting harmonic voltages. Consequently, the active filter is operated as a harmonic isolator between the supply and load.

A hybrid filter bank approach to analog-to-digital conversion

Abstract: This paper presents a novel approach to high-speed, high-resolution analog-to-digital (A/D) conversion using a hybrid filter bank with an array of slower speed A/D converters (ADCs). The hybrid filter bank is a new class of filter bank that employs continuous-time analysis filters to allocate a frequency band to each ADC in the array and discrete-time synthesis filters to reconstruct the digitized signal. The filter bank improves the speed and resolution of the A/D conversion by reducing the effects of mismatches between the ADCs in the array. This paper presents a filter design algorithm which minimizes mean-squared reconstruction error for the M-channel hybrid filter bank. A near-perfect-reconstruction, two-channel hybrid filter bank which introduces 0.00095 dB average deviation from 0 dB distortion and -108 dB average aliasing is developed. >

Temp. sensor function control system

Abstract: The temp. sensor function control system responds to a given temp. rise indicated by the evaluation circuit for the temp. sensor signal, to allow a superimposed AC voltage providing self-heating to be disconnected. Pref. the temp. sensor (1) is coupled to the evaluation circuit via a low pass filter (29).The AC voltage source (25) is connected to the line between the sensor and the filter, via a capacitor (28). The AC voltage source pref. comprises a variable oscillator, controlled via a NOR logic (21) coupled at one input to a comparator (17) comparing the output voltages of the filter and the evaluation circuit.

Low-pass filter for computing the transition density in digital circuits

Abstract: Estimating the power dissipation and the reliability of integrated circuits is a major concern of the semiconductor industry. Previously, we showed that a good measure of power dissipation and reliability is the extent of circuit switching activity, called the transition density (see ibid., vol. 12, no. 2, p. 310-23, 1993). However, the algorithm for computing the density in the afore-mentioned paper is very basic and does not take into account the effect of inertial delays of logic gates. Thus, as we will show in this paper, the transition density may be severely overestimated in high-frequency applications. To overcome this problem, we model the effect of gate delay on logic signals in the form of a conceptual low-pass filter module that does not allow unacceptably short logic pulses to propagate. Using a stochastic model of logic signals, we then derive the equations required to propagate the transition density through the filter. We will present experimental results that illustrate the validity and importance of these results. >

A fast active power filter to correct line voltage sags

Abstract: An active power filter for compensating voltage sags that occur on a weak AC power system is described. The proposed active power filter is especially suitable in situations where sensitive data processing and other critical loads are to be operated on a weak AC system. The proposed filter is fast acting and simple in design. A design procedure based on IEEE/ANSI voltage withstand tolerance (IEEE standard 446-1987) is proposed. Laboratory tests on a prototype filter show fast response and linear correction characteristics. >

Advanced in-plane rotation-invariant correlation filters

Abstract: Advanced correlation filter synthesis algorithms to achieve rotation invariance are described. We use a specified form for the filter as the rotation invariance constraint and derive a general closed-form solution for a multiclass rotation-invariant filter that can recognize a number of different objects. By requiring the filter to minimize the average correlation plane energy, we produce a multiclass rotation invariant (RI) RI-MACE filter, which controls correlation plane sidelobes and improves discrimination against false targets. To improve noise performance, we require the filter to minimize a weighted sum of correlation plane signal and noise energy. Initial test results of all filters are provided. >

Robust servo for disk-shift compensation in rotating storage system

Abstract: A method and apparatus, in a direct access storage device including a head positioned for interaction with a data storage medium mounted on a rotating spindle, an actuator for positioning the head, and a servo control loop for positioning the actuator. The improvement comprises: a narrow band gain enhancing filter for connection in the servo control loop. The filter has a response frequency related to the rotational frequency of the spindle. The filter has programmable initial states. Also provided is a switch for switching in the narrow band filter as the head approaches a target position on the data storage medium. Initial states of the filter are determined and supplied to program the filter. At least one additional filter having a peak response frequency at a harmonic of the frequency of rotation of the spindle, may be provided. Initial states of the additional filters are determined and supplied to program the additional filter. The filter may include successive delay circuits for inputs to the filter, which circuits provide delayed outputs; multipliers for multiplying selected delayed outputs by a constant; and a summer for summing the delay outputs after the delayed outputs are multiplied by the multipliers. The initial states may be stored as phase, frequency and amplitude of a sine function.

A new approach to phase cancellation in repetitive control

Abstract: Effective repetitive control requires that the q-filter, placed within the internal model loop for robustness, have zero phase shift and that the phase shift of the plant be cancelled in the feedforward loop. Previously reported methods of phase cancellation use a moving average q-filter and zero-phase error tracking techniques for plant phase cancellation and are memory and processor intensive. The theory and methods of using a new method to cancel plant and filter phase shift in a repetitive control system are described. This method uses a tunable time advance and enables an analog/digital repetitive control loop to be used. Comparison with previously reported methods shows that it provides good phase cancellation, reduces low frequency repetitive disturbances, is easily tunable based on the closed-loop frequency response of the system without repetitive control, is less memory intensive, and is more easily implemented. >