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Showing papers on "Low-power electronics published in 1998"


Proceedings ArticleDOI
10 Aug 1998
TL;DR: Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits.
Abstract: Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The standby leakage current model has been verified by IISPICE. We demonstrate that the dependence of leakage power on primary input combinations can be accounted for by this model. Based on our analysis we can determine good bounds for leakage power in the standby mode. As a by-product of this analysis, we can also determine the set of input vectors which can put the circuits in the low-power standby mode. Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits.

372 citations


Proceedings ArticleDOI
Yuan Taur1, C. Wann, David J. Frank
06 Dec 1998
TL;DR: In this article, the authors explored the limit of bulk (or partially depleted SOI) CMOS scaling and showed that the delay performance of 25 nm CMOS is 3/spl times/ higher than 100 nm and that the nFET f/sub T/ exceeds 250 GHz.
Abstract: This paper explores the limit of bulk (or partially-depleted SOI) CMOS scaling. A feasible design for 25 nm (channel length) CMOS, without continued scaling of oxide thickness and power supply voltage, is presented. A highly 2D nonuniform profile (super-halo) is shown to yield low off-currents while delivering a significant performance advantage for a 1.0 V power supply. Several key issues, including source-drain doping requirements, band-to-band tunneling, and poly depletion effects, are examined and quantified. It is projected, based on Monte-Carlo simulations, that the delay performance of 25 nm CMOS is 3/spl times/ higher than 100 nm CMOS, and that the nFET f/sub T/ exceeds 250 GHz.

255 citations


Book
01 Jan 1998

144 citations


Proceedings ArticleDOI
10 Aug 1998
TL;DR: This paper proposes a framework for describing the power behavior of system-level designs that consists of a set of resources, an environmental workload specification, and a power management policy, which serves as the heart of the system model.
Abstract: Most work to date on power reduction has focused at the component level, not at the system level. In this paper, we propose a framework for describing the power behavior of system-level designs. The model consists of a set of resources, an environmental workload specification, and a power management policy, which serves as the heart of the system model. We map this model to a simulation-based framework to obtain an estimate of the system's power dissipation. Accompanying this, we propose an algorithm to optimize power management policies. The optimization algorithm can be used in a tight loop with the estimation engine to derive new power-management policy algorithms for a given system-level description. We tested our approach by applying it to a real-life low-power portable design, achieving a power estimation accuracy of /spl sim/10%, and a 23% reduction in power after policy optimization.

137 citations


Proceedings ArticleDOI
10 Aug 1998
TL;DR: A low power SRAM is proposed using an effective method called "ABC-MT-CMOS", which controls the backgates to reduce the leakage current when theSRAM is not activated (sleep mode) while retaining the data stored in the memory cells.
Abstract: We have been proposed a low power SRAM using an effective method called “ABC-MT-CMOS” [1]. It controls the backgates to reduce the leakage current when the SRAM is not activated (sleep mode) while retaining the data stored in the memory cells. We also adopted a “CSB Scheme” which clamps both the source lines of the memory cell array and the bit lines. We designed and fabricated test chips containing a 32K-bit gate array SRAM. The experimental results show that the leakage current is reduced to 1/1000 in sleep mode. The active power is 0.27 mW/MHz at 1 V, which is a reduction of 1/12 of a conventional SRAM with a 3.3 V.

121 citations


Proceedings ArticleDOI
11 May 1998
TL;DR: In this article, a novel design technique which combines a variable supply-voltage scheme and a clustered voltage scaling (VS-CVS) scheme is presented, which enables us to perform chip design in a top-down fashion.
Abstract: A novel design technique which combines a variable supply-voltage scheme and a clustered voltage scaling is presented (VS-CVS scheme). A theory to choose the optimum supply voltages in the VS-CVS scheme is discussed which enables us to perform chip design in a top-down fashion. Level-shifting flip-flops are developed which reduce power, delay and area penalties significantly. Application of this technique to an MPEG4 video codec saves 55% of the power dissipation without degrading circuit performance compared to a conventional CMOS design.

112 citations


Journal ArticleDOI
05 Feb 1998
TL;DR: This stereo /spl Delta//spl Sigma/ DAC for portable digital-audio consumes 4.1 mW at 1.5 V supply and has 90 dB dynamic range over a 20 Hz-20 kHz passband.
Abstract: The paper describes a stereo digital-to-analog converter intended for portable digital-audio which operates at 1.5 V and consumes only 4.1 mW. A 15-level quantization, third-order delta-sigma was employed to reduce digital operation speed, relax out-of-band filtering requirements, and enhance immunity to clock jitter. The use of direct charge transfer switched-capacitor technique in the multibit reconstruction DAC reduces kT/C noise and element mismatch without increase of power dissipation. The data weighted averaging algorithm suppresses nonlinearity caused by capacitor mismatch by first-order noise-shaping, thereby making mismatch-induced noise negligible. The stereo audio DAC achieves 90 dB dynamic range and 81 dB peak signal-to-noise-plus-distortion ratio over a 20 kHz passband. The 5.3 mm/sup 2/ chip is fabricated in a 0.6 /spl mu/m CMOS technology which includes low-threshold devices.

84 citations


Proceedings ArticleDOI
Kouichi Kumagai1, Hiroaki Iwaki, H. Yoshida, H. Suzuki, T. Yamada, S. Kurosawa 
11 Jun 1998
TL;DR: In this article, a virtual power/ground rails clamp (VRC) circuit was proposed to reduce the off-leakage current in a power-down scheme. But the VRC scheme does not need the extra circuits and the timing design for data holding in the sleep mode.
Abstract: In this paper, a novel powering-down scheme with a virtual power/ground rails clamp (VRC) circuit is proposed. It features the 98% off-leakage current reduction, without the operating speed degradation and the high Vt transistors. The VRC scheme does not need the extra circuits and the timing design for data holding in the sleep mode. This effectiveness has been confirmed by the 24-bit multiplier-accumulator, using 0.25 /spl mu/m CMOS double-layer metal technology.

67 citations


Proceedings ArticleDOI
Kaushik Roy1
07 Sep 1998
TL;DR: In this article, the authors present different design techniques such as multiple threshold voltage, dynamic threshold control, substrate biasing, and leakage control using transistor stacking to achieve large improvements in leakage power during both stand-by and active mode of operation.
Abstract: Lowering supply voltage is one of the most effective ways of reducing power dissipation. Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between the leakage current and the transistor threshold voltage in the weak inversion region, static current (and hence, static power power dissipation) can no longer be ignored. In this paper the author presents different design techniques such as multiple threshold voltage, dynamic threshold control, substrate biasing, and leakage control using transistor stacking to achieve large improvements in leakage power during both stand-by and active mode of operation.

64 citations


Journal ArticleDOI
TL;DR: The proposed macro-model predicts not only the cycle-by-cycle power consumption of a module, but also the moving average of power consumption and the power profile of the module over time.
Abstract: In this paper, we present a methodology and techniques for generating cycle-accurate macro-models for register transfer (RT)-level power analysis. The proposed macro-model predicts not only the cycle-by-cycle power consumption of a module, but also the moving average of power consumption and the power profile of the module over time. We propose an exact power function and approximation steps to generate our power macro-model. First-order temporal correlations and spatial correlations of up to order three are considered in order to improve the estimation accuracy. A variable reduction algorithm is designed to eliminate the "insignificant" variables using a statistical sensitivity test. Population stratification is employed to increase the model fidelity. Experimental results show our macro-models with 15 or fewer variables, exhibit <5% error for average power and <20% errors for cycle-by-cycle power estimation compared to circuit simulation results using Powermill.

60 citations


Proceedings ArticleDOI
10 Aug 1998
TL;DR: TSEL is presented, the first energy-recovering logic family that operates with a single-phase clocking scheme and it is indicated that TSEL is an excellent candidate for high-speed and low power VLSI system design.
Abstract: In dynamic logic families that rely on energy recovery to achieve low energy dissipation, the flow of data through cascaded gates is controlled using multi-phase clocks. Consequently, these families require multiple clock generators and can exhibit increased energy consumption on their clock distribution networks. Moreover, they are not attractive for high-speed design due to clock skew management problems. In this paper, we present TSEL, the first energy-recovering logic family that operates with a single-phase clocking scheme. TSEL outperforms previous energy-recovering logic families in terms of energy efficiency and operating speed. In HSPICE simulations with a standard 0.5 /spl mu/m technology from MOSIS, pipelined carry-lookahead adders in TSEL function correctly for operating frequencies exceeding 280 MHz. For operating frequencies above 80 MHz, they dissipate considerably less energy per operation than alternative implementations of the same adder architecture in other energy-recovering logic families. In comparison with their CMOS counterparts, the TSEL adders dissipate about half as much energy at 280 MHz. Our results indicate that TSEL is an excellent candidate for high-speed and low power VLSI system design.

Journal ArticleDOI
TL;DR: A new approach for minimizing the total of the static and the dynamic power dissipation components in a complementary metal-oxide-semiconductor (CMOS) logic network required to operate at a specified clock frequency is demonstrated.
Abstract: This paper demonstrates a new approach for minimizing the total of the static and the dynamic power dissipation components in a complementary metal-oxide-semiconductor (CMOS) logic network required to operate at a specified clock frequency. The algorithms presented can be used to design ultralow-power CMOS logic circuits by joint optimization of supply voltage, threshold voltage and device widths. The static, dynamic and short-circuit energy components are considered and an efficient heuristic is developed that delivers over an order of magnitude savings in power over conventional optimization methods.

Journal ArticleDOI
TL;DR: A new power cost model for state encoding is proposed and encoding techniques that minimize this power cost for two- and multilevel logic implementations are described, compared with those that minimize area or the switching activity at the present state bits.
Abstract: The problem of minimizing power consumption during the state encoding of a finite-state machine is addressed. A new power cost model for state encoding is proposed, and encoding techniques that minimize this power cost for two- and multilevel logic implementations are described. These techniques are compared with those that minimize area or the switching activity at the present state bits. Experimental results show significant improvements.

Proceedings ArticleDOI
14 Dec 1998
TL;DR: This paper will first address the following issues: why a voltage transition causes power dissipation, what causes a transition, what are useful and redundant transitions, how information redundancy may reduce the number of transitions, and how to statistically measure the average number of transitioned activity.
Abstract: This paper will first address the following issues: why a voltage transition causes power dissipation, what causes a transition, what are useful and redundant transitions, how information redundancy may reduce the number of transitions, how to statistically measure the average number of transitions (or activity). In a second part, the paper will show the incidence of scaling down the transistors on power dissipation. The third part will address the question: what is performance. Next, the fourth part will discuss complexity versus dissipation and finally glitch filtering.

Journal ArticleDOI
TL;DR: A novel equivalent capacitance concept is introduced allowing a direct and frequency-independent comparison of the different power components, and a direct link between fanout and input/output slew is studied in order to derive design-oriented analytical macromodels for the internal power components.
Abstract: We present in this paper a novel alternative for the internal power-dissipation estimation of CMOS structures. A first order macromodeling is developed, considering full submicronic additional effects such as input slew dependency of short-circuit currents and input-to-output coupling. We introduce a novel equivalent capacitance concept allowing a direct and frequency-independent comparison of the different power components. A direct link between fanout and input/output slew is studied in order to derive design-oriented analytical macromodels for the internal power components. Validations are presented by comparing simulated values (HSPICE level 6 foundry model 0.65 /spl mu/m) of power components to calculated values over a wide range of inverter configurations and control conditions. Discussion is given on a first-order generalization of this macromodel to gates. Evidence is given in terms of fanout and equivalent capacitance ratio of the controlling slope contribution on the internal power-dissipation components.

Proceedings ArticleDOI
10 Aug 1998
TL;DR: The VCO, by virtue of its high-Q inductive components, displays the lowest reported phase noise for 1 GHz CMOS VCO system for any power dissipation.
Abstract: New applications have recently appeared for a low power, low cost, “embedded radio”. These wireless interfaces for handheld mobile nodes and Wireless Integrated Network Sensors (WINS) must provide spread spectrum signaling for multi-user operation at 902-928 MHz. Cost considerations motivate the development of complete micropower CMOS RF systems operating at previously unexplored low power levels. Micropower CMOS VCO and mixer circuits, developed for these emerging narrow-band communication systems, are reported here. Design methods combining high-Q inductors and weak inversion MOSFET operation enable the lowest reported operating power for RF front end components including a voltage-controlled oscillator (VCO) and mixer operating at frequencies of 400 MHz — 1 GHz. In addition, the VCO, by virtue of its high-Q inductive components, displays the lowest reported phase noise for 1 GHz CMOS VCO system for any power dissipation.

Journal ArticleDOI
TL;DR: Among the bit-level pipelined digit-serial multipliers, it is found that the redundant multiplier offers the best choice in terms of both latency and power consumption.
Abstract: Digit-serial implementation styles are best suited for implementation of digital signal processing systems which require moderate sampling rates. Digit-serial architectures obtained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, an alternative approach for the design of the digit-serial architectures is presented based on a novel design methodology. This methodology permits bit-level pipelining of the digit-serial architectures by moving all feedback loops to the last stage of the design. This enables bit-level pipelining of digit-serial architectures, thereby achieving sample speeds close to corresponding bit-parallel multipliers with lower area. This increased sample speed can be traded with reduction in power supply voltage resulting in significant reduction in power consumption. The proposed approach is applied to the design of various multipliers which form the backbone of digital signal processing computations. The results show that for transformed multipliers with smaller digit sizes (/spl les/4), the singly-redundant multiplier consumes the least power, and for larger digit sizes, the type-I multiplier consumes the least power. It is also found that the optimum digit size for least power consumption in type-I and type-III multipliers is /spl sim//spl radic/(2W), where W represents the word length. Among the bit-level pipelined digit-serial multipliers, it is found that the redundant multiplier offers the best choice in terms of both latency and power consumption.

Proceedings ArticleDOI
10 Aug 1998
TL;DR: This work proposes a new technique for generating a small set of patterns to estimate the maximum power supply noise of deep sub-micron designs using the Genetic Algorithm based on the efficient waveform simulator.
Abstract: We propose a new technique for generating a small set of patterns to estimate the maximum power supply noise of deep sub-micron designs. We first build the charge/discharge current and output voltage waveform libraries for each cell, taking power and ground pin characteristics, the power net RC and other input characteristics as parameters. Based on the cells' current and voltage libraries, the power supply noise of a 2-vector sequence can be estimated efficiently by a cell-level waveform simulator. We then apply the Genetic Algorithm based on the efficient waveform simulator to generate a small set of patterns producing high power supply noise. Finally, the results are validated by simulating the obtained patterns using a transistor level simulator. Our experimental results show that the patterns generated by our approach produce a tight lower bound on the maximum power supply noise.

Journal ArticleDOI
TL;DR: This paper addresses the problem of reducing power dissipation of finite impulse response (FIR) filters implemented on programmable digital signal processors (DSPs) and presents seven transformations to reduce power dissipated in one or more of these sources.
Abstract: This paper addresses the problem of reducing power dissipation of finite impulse response (FIR) filters implemented on programmable digital signal processors (DSPs). We describe a generic DSP architecture and identify the main sources of power dissipation during FIR filtering. We present seven transformations to reduce power dissipated in one or more of these sources. These transformations complement each other and together operate at algorithmic, architectural, logic and layout levels of design abstraction. Each of the transformations is discussed in detail and the results are presented to highlight its effectiveness. We show that the power dissipation can be reduced by more than 40% using these transforms. The transformations have been encapsulated in a framework that provides a comprehensive solution to low-power realization of FIR filters on programmable DSP's.

Proceedings ArticleDOI
13 Sep 1998
TL;DR: In this paper, a transregional model for conventional surface channel inversion MOSFETs with continuous and smooth transitions at regional boundaries is introduced, which describes all regions of operation, namely, subthreshold, linear, and saturation while including the effects of carrier velocity saturation, vertical and lateral high field mobility degradation, and threshold voltage roll-off.
Abstract: A new compact transregional model for conventional surface channel inversion MOSFETs with continuous and smooth transitions at regional boundaries is introduced. The model, verified against MEDICI and HSPICE, describes all regions of operation, namely, subthreshold, linear, and saturation while including the effects of 1) carrier velocity saturation, 2) vertical and lateral high field mobility degradation, and 3) threshold voltage roll-off, all prominent characteristics of sub-micron devices. The key contribution of this model is the physical insight into the on/off current trade-off that ensues with voltage scaling and will be vital to future low power design. Utilizing the model for a complete power-delay analysis of CMOS circuit designs, analytical expressions are derived for: 1) propagation delay, 2) short circuit power (P/sub SC/), and 3) static power (P/sub Static/). Results from the total power (P/sub Total/) consumption analysis indicate that P/sub SC/ and P/sub Static/ may constitute over 1/3 of P/sub Total/ in future low power/high performance CMOS GSI.

Proceedings ArticleDOI
10 Aug 1998
TL;DR: In a speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) circuit, the substrate bias is controlled so that delay in the circuit stays constant, and the fluctuation of the operating frequency was suppressed while the supply-voltages variation was under 0.1 V.
Abstract: In a speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) circuit, the substrate bias is controlled so that delay in the circuit stays constant. Distributions of device speeds are squeezed under fast-operation conditions. With a ring oscillator using 0.25 /spl mu/m CMOS devices as a test circuit, we found that the worst-case operating frequency was improved from 20 MHz to 55 MHz, and the fluctuation of the operating frequency was suppressed from 44% to 15% while the supply-voltage variation was under 0.1 V with a 1.8 V supply voltage.

Proceedings ArticleDOI
14 Dec 1998
TL;DR: The solution here proposed consists of a capacitance multiplier made up of a current conveyor and a current operational amplifier which allows accurate capacitance factors up to 100 to be achieved and, thanks to the use of the current mode approach, low supply voltage operations are obtained.
Abstract: In this work the problem of obtaining capacitance values higher than those normally integratable and/or provided by capacitive transducers has been investigated. The solution here proposed consists of a capacitance multiplier made up of a current conveyor and a current operational amplifier which allows accurate capacitance factors up to 100 to be achieved. Moreover, thanks to the use of the current mode approach, low supply voltage operations (profitable in portable sensor systems) are obtained. The whole topology has been designed in a standard 0.5-/spl mu/m CMOS technology with a 1.5-V supply voltage and micropower consumption. SPICE simulations show a good agreement with the expected results and confirm an accurate multiplication factor for capacitances higher than 1 pF.

Proceedings ArticleDOI
01 Nov 1998
TL;DR: In this paper, a 52.9 GHz static 1/8 divider was demonstrated in an AlInAs/InGaAs HBT process, which is the fastest static divider reported in any semiconductor technology.
Abstract: We have demonstrated a 52.9 GHz static 1/8 divider in an AlInAs/InGaAs HBT technology. To our knowledge this is the fastest static divider reported in any semiconductor technology. The divider was realized in a high yield optical lithography triple mesa HBT process. At maximum speed, power consumption was 40 mW/flip-flop. A second 1/8 divider, designed for lower power but using the same size transistors, consumed 8.6 mW/flip-flop at 35 GHz. Sensitivity was excellent with the high-speed version operating from DC to 48 GHz with less than 0 dBm input power. Uniformity and reproducibility were also demonstrated; all functional dividers operated above 45 GHz on-wafer and the extrapolated yield of dividers indicates that the process is capable of supporting 500-1000 transistor designs. Circuit performance was relatively insensitive to the details of the device epitaxial structure indicating a highly robust and manufacturable process.

Proceedings ArticleDOI
07 Sep 1998
TL;DR: The model has been found effective in evaluating the correlation of leakage power with other performance specs, in particular delay, and it has been shown that an IC with short L, and therefore, with high P/sub LEAK/ will be faster than nominal ones and anIC with long L, with low P/ sub LEAK/, will be slower.
Abstract: A model to statistically characterize the leakage power of CMOS digital circuits is presented. Based on the subthreshold leakage characterization at transistor and cell level, the leakage power consumption of a standard cell circuit is obtained. Also, in order to estimate the leakage power variability for a fixed state, a model of variations due to process is introduced. Using these models, the P/sub LEAK/ distribution is found to be asymmetric around the nominal value showing a long tail for high consuming circuits. The model has been found effective in evaluating the correlation of leakage power with other performance specs, in particular delay. We have shown that an IC with short L, and therefore, with high P/sub LEAK/ will be faster than nominal ones and an IC with long L, and therefore, with low P/sub LEAK/ will be slower. Predicted results are consistent with available experimental data.

Proceedings ArticleDOI
07 Sep 1998
TL;DR: Going to basics leads to a very simple and very linear buffer which shows more than 26 dB THD improvement over conventional designs.
Abstract: A high input impedance, low output impedance, highly linear CMOS buffer is very desirable in many analog CMOS circuits. Conventional buffers employ feedback which severely limits bandwidth and linearity at even medium range frequencies. A recent open loop buffer, although linear, suffers from large power supply voltage requirement. This makes it undesirable for low voltage deep submicron processes. Here going to basics leads us to a very simple and very linear buffer which shows more than 26 dB THD improvement over conventional designs.

Proceedings ArticleDOI
11 May 1998
TL;DR: A methodology for automatic generation of gating conditions and synthesis of gated control signals from the RTL description of a design is presented, which has very low overheads in terms of area, power, and designer effort.
Abstract: This paper presents a practical technique for saving power dissipation in large datapaths by reducing unnecessary switching activity on wide buses. Control signals on a datapath module are gated by the observability don't care condition of the bus driven by that module to stop unnecessary switching activity on the bus. A methodology for automatic generation of gating conditions and synthesis of gated control signals from the RTL description of a design is presented. The technique has very low overheads in terms of area, power, and designer effort. It was applied to one of the integer execution units of a 64-bit super-scalar RISC microprocessor. Experimental results of running various application programs on the microprocessor show on an average 26.6% reduction in dynamic switching power in the integer execution unit, with no increase in path delays.

Proceedings Article
01 Jan 1998

Proceedings ArticleDOI
10 Aug 1998
TL;DR: Multi-Voltage CMOS (MVCMOS) is a design methodology for very low power supply voltages that uses low-threshold transistors in series with the supply rails to reduce the standby current.
Abstract: Multi-Voltage CMOS (MVCMOS) is a design methodology for very low power supply voltages that uses low-threshold transistors in series with the supply rails. The control voltages on the gating transistors need to be outside of the V/sub dd/-V/sub ss/ range (hence the name MVCMOS) in order to reduce the standby current, but the resulting circuits operate at lower supply voltages and have a lower area overhead than the previously proposed Multi-Threshold CMOS (MTCMOS).

Proceedings ArticleDOI
10 Aug 1998
TL;DR: A power optimization method considering glitch reduction by gate sizing that improves the accuracy of statistical glitch estimation method and a device gate sizing algorithm that utilizes perturbations for escaping a bad local solution.
Abstract: We propose a power optimization method considering glitch reduction by gate sizing. Our method reduces not only the amount of capacitive and short-circuit power consumption but also the power dissipated by glitches which has not been exploited previously. In the optimization method, we improve the accuracy of statistical glitch estimation method and a device gate sizing algorithm that utilizes perturbations for escaping a bad local solution. The effect of our method is verified experimentally using 12 benchmark circuits with a 0.5 /spl mu/m standard cell library. Gate sizing reduces the number of glitch transitions by 38.2% on average and by 63.4% maximum. This results in the reduction of total transitions by 12.8% on average. When the circuits are optimized for power without delay constraints, the power dissipation is reduced by 7.4% on average and by 15.7% maximum further from the minimum-sized circuits.

Proceedings ArticleDOI
13 Sep 1998
TL;DR: In this paper, a new layout style of standard cells to be used in ASIC designs is proposed to effectively exploit the advantages afforded by the multiple-supply-voltage (MSV) scheme.
Abstract: ASIC design utilizing the multiple-supply-voltage (MSV) scheme has been shown to be efficient in reducing the power consumption. A new layout style of standard cells to be used in ASIC designs is proposed to effectively exploit the advantages afforded by the MSV scheme. Each standard cell is designed to use two power rails that are fed with different supply voltages. Then, the cells can be butted together arbitrarily no matter whether the cells are supplied from a high or low voltage, and the existing P&R tool can place and route the circuit as usual. As compared to the design with only one supply voltage, the average saving of power consumption of the new design (using the new cells and adopting the MSV scheme) is over 30%, but the average area overhead is only about 8%. Meanwhile, the average interconnection length is only increased by about 7.5%.