Showing papers on "Low-power electronics published in 2001"

Device scaling limits of Si MOSFETs and their application dependencies

Abstract: This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

Vibration-to-electric energy conversion

Abstract: A system is proposed to convert ambient mechanical vibration into electrical energy for use in powering autonomous low power electronic systems. The energy is transduced through the use of a variable capacitor. Using microelectromechanical systems (MEMS) technology, such a device has been designed for the system. A low-power controller IC has been fabricated in a 0.6-/spl mu/m CMOS process and has been tested and measured for losses. Based on the tests, the system is expected to produce 8 /spl mu/W of usable power. In addition to the fabricated programmable controller, an ultra low-power delay locked loop (DLL)-based system capable of autonomously achieving a steady-state lock to the vibration frequency is described.

Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS

Abstract: This paper describes the design and optimization of VCOs with quadrature outputs. Systematic design of fully integrated LC-VCOs with a high inductance tank leads to a cross-coupled double core LC-VCO as the optimal solution in terms of power consumption. Furthermore, a novel fully differential frequency tuning concept is introduced to ease high integration. The concepts are verified with a 0.25-/spl mu/m standard CMOS fully integrated quadrature VCO for zero- or low-IF DCS1800, DECT, or GSM receivers. At 2.5-V power supply voltage and a total power dissipation of 20 mW, the quadrature VCO features a worst-case phase noise of -143 dBc/Hz at 3-MHz frequency offset over the tuning range. The oscillator is tuned from 1.71 to 1.99 GHz through a differential nMOS/pMOS varactor input.

Scaling of stack effect and its application for leakage reduction

Abstract: Technology scaling demands a decrease in both V/sub dd/ and V/sub t/ to sustain historical delay reduction, while restraining active power dissipation. Scaling of V/sub t/ however leads to substantial increase in the sub-threshold leakage power and is expected to become a considerable constituent of the total dissipated power. It has been observed that the stacking of two off devices has smaller leakage current than one off device. In this paper we present a model that predicts the scaling nature of this leakage reduction effect. Device measurements are presented to prove the model's accuracy. Use of stack effect for leakage reduction and other implications of this effect are discussed.

Very low-voltage digital-audio /spl Delta//spl Sigma/ modulator with 88-dB dynamic range using local switch bootstrapping

Abstract: A 1-V 1-mW 14-bit /spl Delta//spl Sigma/ modulator in a standard CMOS 0.35-/spl mu/m technology is presented. Special attention has been given to device reliability and power consumption in a switched-capacitor implementation. A locally bootstrapped symmetrical switch that avoids gate dielectric overstress is used in order to allow rail-to-rail signal switching. The switch constant overdrive also enhances considerably circuit linearity. Modulator coefficients of a single-loop third-order topology have been optimized for low power. Further reduction in the power consumption is obtained through a modified two-stage opamp. Measurement results show that for an oversampling ratio of 100, the modulator achieves a dynamic range of 88 dB, a peak signal-to-noise ratio of 87 dB and a peak signal-to-noise-plus-distortion ratio of 85 dB in a signal bandwidth of 25 kHz.

Rotary traveling-wave oscillator arrays: a new clock technology

Abstract: Rotary traveling-wave oscillators (RTWOs) represent a new transmission-line approach to gigahertz-rate clock generation. Using the inherently stable LC characteristics of on-chip VLSI interconnect, the clock distribution network becomes a low-impedance distributed oscillator. The RTWO operates by creating a rotating traveling wave within a closed-loop differential transmission line. Distributed CMOS inverters serve as both transmission-line amplifiers and latches to power the oscillation and ensure rotational lock. Load capacitance is absorbed into the transmission-line constants whereby energy is recirculated giving an adiabatic quality. Unusually for an LC oscillator, multiphase (360/spl deg/) square waves are produced directly. RTWO structures are compact and can be wired together to form rotary oscillator arrays (ROAs) to distribute a phase-locked clock over a large chip. The principle is scalable to very high clock frequencies. Issues related to interconnect and field coupling dominate the design process for RTWOs. Taking precautions to avoid unwanted signal couplings, the rise and fall times of 20 ps, suggested by simulation, may be realized at low power consumption. Experimental results of the 0.25-/spl mu/m CMOS test chip with 950-MHz and 3.4-GHz rings are presented, indicating 5,5-ps jitter and 34-dB power supply rejection ratio (PSRR). Design errors in the test chip precluded meaningful rise and fall time measurements.

Low-voltage low-power CMOS full adder

Abstract: Low-power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronics products. In this regard many innovative designs for basic logic functions using pass transistors and transmission gates have appeared in the literature recently. These designs relied on the intuition and cleverness of the designers, without involving formal design procedures. Hence, a formal design procedure for realising a minimal transistor CMOS pass network XOR-XNOR cell, that is fully compensated for threshold voltage drop in MOS transistors, is presented. This new cell can reliably operate within certain bounds when the power supply voltage is scaled down, as long as due consideration is given to the sizing of the MOS transistors during the initial design step. A low transistor count full adder cell using the new XOR-XNOR cell is also presented.

Robust subthreshold logic for ultra-low power operation

Abstract: Digital subthreshold logic circuits can be used for applications in the ultra-low power end of the design spectrum, where performance is of secondary importance. In this paper, we propose two different subthreshold logic families: 1) variable threshold voltage subthreshold CMOS (VT-Sub-CMOS) and 2) subthreshold dynamic threshold voltage MOS (Sub-DTMOS) logic. Both logic families have comparable power consumption as regular subthreshold CMOS logic (which is up to six orders of magnitude lower than that of normal strong inversion circuit) with superior robustness and tolerance to process and temperature variations than that of regular subthreshold CMOS logic.

Run-time power estimation in high performance microprocessors

Abstract: Power concerns are becoming increasingly pressing in high-performance processors. Building power-aware and even power-adaptive computer architectures requires being able to track power consumption and attribute energy consumption to the portions of the chip that are responsible for it. This paper presents the Castle project which aims to deduce the actual runtime power dissipated by different processor units on the CPU chip by leveraging existing hardware. Namely, we examine the use of hardware performance counters as proxies for power meters. We discuss which performance counters count power-relevant events, and how to estimate event counts for power-relevant events not well supported by current, commonly available performance counters. We also discuss sampling-based approaches for estimating signal transition activity within the processor. Overall, we find that these performance counters can be quite useful in providing good power apportionment estimates for programs as they run.

A 2.4 GHz CMOS transceiver for Bluetooth

Abstract: A fully integrated CMOS transceiver tuned to 2.4 GHz consumes 46 mA in receive mode and 47 mA in transmit mode from a 2.7-V supply. It includes all the receive and transmit building blocks, such as frequency synthesizer, voltage-controlled oscillator (VCO), power amplifier, and demodulator. The receiver uses a low-IF architecture for higher level of integration and lower power consumption. It achieves a sensitivity of -82 dBm at 0.1% BER, and a third-order input intercept point (IIP3) of -7 dBm. The direct-conversion transmitter delivers a GFSK modulated spectrum at a nominal output power of 4 dBm. The on-chip voltage controlled oscillator has a close-in phase-noise of -120 dBc/Hz at 3-MHz offset.

LVDS I/O interface for Gb/s-per-pin operation in 0.35-/spl mu/m CMOS

Abstract: This paper presents the design and the implementation of input/output (I/O) interface circuits for Gb/s-per-pin operation, fully compatible with low-voltage differential signaling (LVDS) standard. Due to the differential transmission technique and the low voltage swing, LVDS allows high transmission speeds and low power consumption at the same time. In the proposed transmitter, the required tolerance on the dc output levels was achieved over process, temperature, and supply voltage variations with neither external components nor trimming procedures, by means of a closed-loop control circuit and an internal voltage reference. The proposed receiver implements a dual-gain-stage folded-cascode architecture which allows a 1.2-Gb/s transmission speed with the minimum common-mode and differential voltage at the input. The circuits were implemented in a 3.3-V 0.35-/spl mu/m CMOS technology in a couple of test chips. Transmission operations up to 1.2 Gb/s with random data patterns and up to 2 Gb/s in asynchronous mode were demonstrated. The transmitter and receiver pad cells exhibit a power consumption of 43 and 33 mW, respectively.

Conditional-capture flip-flop for statistical power reduction

Abstract: This paper describes a family of novel low-power flip-flops, collectively called conditional-capture flip-flops (CCFFs). They achieve statistical power reduction by eliminating redundant transitions of internal nodes. These flip-flops also have negative setup time and thus provide small data-to-output latency and attribute of soft-clock edge for overcoming clock skew-related cycle time loss. The simulation comparison indicates that the proposed differential flip-flop achieves power savings of up to 61% with no impact on latency while the single-ended structure provides the maximum power savings of around 67%, as compared to conventional flip-flops. With a typical switching activity of 0.33, the power consumption is reduced by as much as 23-30% with comparable minimum data-to-output latency. It is also indicated that the proposed single-ended structure provides power comparable to the fully static master-slave design with significantly reduced data-to-output latency. An eight-bit counter was fabricated using a 0.35-/spl mu/m CMOS technology, and the experimental results indicate that the counter using the differential CCFF saves the overall power consumption by about 30% as compared to that using the conventional flip-flop.

An analysis of power reduction techniques in scan testing

Abstract: Power consumption during scan testing is becoming a concern. Circuit switching activity during scan shifting is high and results in high average and instantaneous power consumption. This paper presents a scheme for reducing power and provides analysis results on an industrial design.

A low-power low-noise ultrawide-dynamic-range CMOS imager with pixel-parallel A/D conversion

Abstract: A CMOS image sensor with pixel-parallel analog-to-digital (A/D) conversion fabricated with different array sizes and photodiode types in a three-metal 0.5-/spl mu/m process is presented. Nominal power dissipation is 40 nW per pixel at V/sub DD/=3.3 V. A/D conversion results from sampling a free-running photocurrent-controlled oscillator to give a first-order /spl Sigma/-/spl Delta/ sequence. The sensor displays dynamic range capability of greater than 150000:1 and exhibits fixed pattern noise correctable to within 0.1% of signal.

1-V 9-bit pipelined switched-opamp ADC

Abstract: A 9-bit 1.0-V pipelined analog-to-digital converter has been designed using the switched-opamp technique. The developed low-voltage circuit blocks are a multiplying analog-to-digital converter (MADC), an improved common-mode feedback circuit for a switched opamp, and a fully differential comparator. The input signal for the converter is brought in using a novel passive interface circuit. The prototype chip, implemented in a 0.5-/spl mu/m CMOS technology, has differential nonlinearity and integral nonlinearity of 0.6 and 0.9 LSB, respectively, and achieves 50.0-dB SNDR at 5-MHz clock rate. As the supply voltage is raised to 1.5 V, the clock frequency can be increased to 14 MHz. The power consumption from a 1.0-V supply is 1.6 mW.

A modified clock scheme for a low power BIST test pattern generator

Abstract: In this paper, we present a new low power test-per-clock BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation. The proposed low power/energy BIST technique is based on a modified clock scheme for the TPG and the clock tree feeding the TPG. Numerous advantages can be found in applying such a technique during BIST.

A low-power reconfigurable analog-to-digital converter

Abstract: A low-power CMOS reconfigurable analog-to-digital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption is described. The converter achieves the wide operating range by (1) reconfiguring its architecture between pipeline and delta-sigma modes; (2) varying its circuit parameters, such as size of capacitors, length of pipeline, and oversampling ratio, among others; and (3) varying the bias currents of the opamps in proportion to the converter sampling frequency, accomplished through the use of a phase-locked loop (PLL). This converter also incorporates several power-reducing features such as thermal noise limited design, global converter chopping in the pipeline mode, opamp scaling, opamp sharing between consecutive stages in the pipeline mode, an opamp chopping technique in the delta-sigma mode, and other design techniques. The opamp chopping technique achieves faster closed-loop settling time and lower thermal noise than conventional design. At a converter power supply of 3.3 V, the converter achieves a bandwidth range of 0-10 MHz over a resolution range of 6-16 bits, and parameter reconfiguration time of twelve clock cycles. Its PLL lock range is measured at 20 kHz to 40 MHz. In the delta-sigma mode, it achieves a maximum signal-to-noise ratio of 94 dB and second and third harmonic distortions of 102 and 95 dB, respectively, at 10 MHz clock frequency, 9.4 kHz bandwidth, and 17.6 mW power. In the pipeline mode, it achieves a maximum DNL and INL of /spl plusmn/0.55 LSBs and /spl plusmn/0.82 LSBs, respectively, at 11 bits, at a clock frequency of 2.6 MHz and 1 MHz tone with 24.6 mW of power.

A gated clock scheme for low power scan testing of logic ICs or embedded cores

Abstract: Test power is now a big concern in large system-on-chip designs. In this paper, we present a novel approach for minimizing power consumption during scan testing of integrated circuits or embedded cores. The proposed low power technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path. The idea is to reduce the clock rate on scan cells during shift operations without increasing the test time. Numerous advantages can be found in applying such a technique.

An ultralow-power UHF transceiver integrated in a standard digital CMOS process: architecture and receiver

Abstract: A broad range of high-volume consumer applications require low-power battery-operated wireless microsystems and sensors These systems should conciliate a sufficient battery lifetime with reduced dimensions, low cost, and versatility Their design highlights the tradeoff between performance, lifetime, cost, and power consumption Also, special circuit and design techniques are needed to comply with the reduced supply voltage (down to 1 V, for single battery cell operation) These considerations are illustrated by the design of a prototype receiver chip realized in a standard 05-/spl mu/m digital CMOS process with 06-V threshold voltage The chip is dedicated to a distributed sensors network and is based on a direct-conversion architecture The circuit operates at 1-V power supply in the 434-MHz European ISM band and consumes only 1 mW in receive mode It achieves a -95 dBm sensitivity for a data rate of 24 kb/s

A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMIC front-end with a low insertion loss switch

Abstract: This paper describes the design and experimental results of a 1.8-V single-chip CMOS MMIC front-end for 2.4-GHz band short-range wireless communications, such as Bluetooth and wireless LANs. The IC consists of fundamental RF building circuits-a power amplifier (PA), a low-noise amplifier (LNA), and a transmit/receive-antenna switch (SW), including almost all on-chip matching elements. The IC was fabricated using a 0.18-/spl mu/m standard bulk CMOS technology which has no extra processing steps to enhance the RF performances. Two new circuit-design techniques are introduced in the IC in order to minimize the insertion loss of the SW and realize a higher gain for the PA and LNA despite the utilization of the standard bulk CMOS technology. The first is the derivation of an optimum gate width of the SW to minimize the insertion loss based on small-signal equivalent circuit analysis. The other is the revelation of the advantages of interdigitated capacitors (IDCs) over conventional polysilicon to polysilicon capacitors and the successful use of the IDCs in the LNA and PA. The IC achieves the following sufficient characteristics for practical wireless terminals at 2.1 GHz and 1.8 V: a 5-dBm transmit power at a -1-dB gain compression, a 19-dB gain, an 18-mA current for the PA, a 1.5-dB insertion loss, more than 24-dB isolation, an 11-dBm power handling capability for the SW, a 7.5-dB gain, a 4.5-dB noise figure, and an 8-mA current for the LNA.

A low-power CMOS super-regenerative receiver at 1 GHz

Abstract: A low-power and low-voltage super-regenerative receiver operating at 1 GHz and implemented in a 0.35-/spl mu/m CMOS process is described. The receiver includes a low-noise amplifier, a super-regenerative oscillator, an envelope detector, an AGC circuit with sample/hold function, and a baseband amplifier. The die surface is equal to 0.25 mm/sup 2/. The power consumption is less than 1.2 mW at V/sub DD/=1.5 V. A 100-kHz sawtooth quench signal is used to achieve a rejection of -36 dB at 500 KHz from the central frequency.

A CMOS RF power amplifier with parallel amplification for efficient power control

Abstract: This paper introduces a CMOS radio-frequency (RF) power amplifier that uses parallel amplification to provide high efficiency over a broad range of output power. Three binary-weighted class-F unit amplifiers act in conjunction with an efficient power-combination network to provide a digital-to-analog conversion between a 3-b control signal and the amplitude of the output RF signal. The power-combination network is based on quarter-wavelength transmission lines that also serve as class-F harmonic terminations. A pMOS switch to the positive supply rail is used to avoid power dissipation when a unit amplifier is shut down. The parallel-amplifier architecture, integrated in a 0.25-/spl mu/m CMOS technology, occupies an active die area of 0.43 mm/sup 2/, operates at 1.4 GHz from a 1.5-V supply, and provides an output power adjustment range of 7-304 mW. The amplifier achieves a maximum power-added efficiency (PAE) of 49% and maintains a PAE of greater than 43% over the range of 100-300 mW.

QSERL: quasi-static energy recovery logic

Abstract: A new quasi-static energy recovery logic family (QSERL) using the principle of adiabatic switching is proposed in this paper. Most of the previously proposed adiabatic logic styles are dynamic and require complex clocking schemes. The proposed QSERL uses two complementary sinusoidal supply clocks and resembles the behavior of static CMOS. Thus, switching activity is significantly lower than dynamic logic. In addition, QSERL circuits can be directly derived from static CMOS circuits. A high-efficiency clock generation circuitry, which generates two complementary sinusoidal clocks compatible to QSERL, is also presented in this paper. The adiabatic clock circuitry locks the frequency of clock signals, which makes it possible to integrate adiabatic modules into a VLSI system. We have designed an 8/spl times/8 carry-save multiplier using QSERL logic and two phase sinusoidal clocks. SPICE simulation shows that the QSERL multiplier can save 34% of energy over static CMOS multiplier at 100 MHz.

12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1 MS/s

Abstract: Based on a conventional successive approximation ADC architecture, a new and faster solution is presented. The input structure of the new solution consists of transmission gates and capacitors only and there is no need for any active element. A switching circuit is implemented to allow a wider input voltage range of the ADC. Together with a self-timed comparator, the power consumption is noticeably reduced while at the same time the sampling rate is doubled. Smaller input and reference capacitances reduce the requirements on the input and reference sources, respectively. Additionally, a widely clock-duty-cycle-independent control logic improves the applicability of the converter cell, especially for systems on chip. Results of measurements confirm the theoretical improvements.

Micro-transponder systems for medical applications

Abstract: The low power consumption of CMOS electronics with on-chip cointegrated sensors or actuators make it ideal for use in implanted systems that need a very low power consumption. Three examples are presented here, which are powered by the energy of an external RF-field. The first microsystem described is a system for measuring the intraocular pressure (IOP). Second, a system for measuring blood pressure will be introduced The third system is used for stimulating the nerve cells of the retina of patients suffering from retinitis pigmentosa. Typical microsystem chip dimensions are about 2.5 mm /spl times/ 2.5 mm and typical power consumption is about 240 /spl mu/W.

Demonstration of a switched resonator concept in a dual-band monolithic CMOS LC-tuned VCO

Abstract: A switched resonator concept which allows better trade-off between phase noise and power consumption is demonstrated using a dual band VCO. The dual-band VCO operates near 900 MHz and 1.8 GHz with phase noise of -125 and 123 dBc/Hz at a 600-KHz offset and 16-mW power consumption. Compared to a single band 1.8 GHz VCO, the dual-band VCO has almost the same phase noise and power consumption.

Nested Miller compensation in low-power CMOS design

Abstract: First, new stability conditions for low-power CMOS nested Miller compensated amplifiers are given in this brief. Then, an improved structure, which takes the advantages of a feedforward transconductance stage and a nulling resistor, is introduced. Experimental results prove that the proposed structure improves the frequency response, transient response, and power supply rejection ratio without increasing the power consumption and circuit complexity.

A CMOS clock recovery circuit for 2.5-Gb/s NRZ data

Abstract: This paper describes a phase-locked clock recovery circuit that operates at 2.5 Gb/s in a 0.4-/spl mu/m digital CMOS technology. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide range. A sample-and-hold phase detector is also described that combines the advantages of linear and nonlinear phase detectors. The recovered clock exhibits an rms jitter of 10.8 ps for a PRBS sequence of length 2/sup 7/-1 and a phase noise of -80 dBc/Hz at a 5-MHz offset. The core circuit dissipates a total power of 33.5 mW from a 3.3-V supply and occupies an area of 0.8/spl times/0.4 mm/sup 2/.

On gate level power optimization using dual-supply voltages

Abstract: In this paper, we present an approach for applying two supply voltages to optimize power in CMOS digital circuits under the timing constraints. Given a technology-mapped network, we first analyze the power/delay model and the timing slack distribution in the network. Then a new strategy is developed for timing-constrained optimization issues by making full use of stacks. Based on this strategy, the power reduction is translated into the polynomial-time-solvable maximal-weighted-independent-set problem on transitive graphs. Since different supply voltages used in the circuit lead to totally different power consumption, we propose a fast heuristic approach to predict the optimum dual-supply voltages by looking at the lower bound of power consumption in the given circuit. To deal with the possible power penalty due to the level converters at the interface of different supply voltages, we use a "constrained F-M" algorithm to minimize the number of level converters. We have implemented our approach under an SIS environment. Experiment shows that the resulting lower bound of power is tight for most circuits and that the predicted "optimum" supply voltages are exactly or very close to the best choice of actual ones. The total power saving of up to 26% (average of about 20%) is achieved without degrading the circuit performance, compared to the average power improvement of about 7% by the gate sizing technique based on a standard cell library. Our technique provides the power-delay tradeoff by specifying different timing constraints in circuits for power optimization.

Power-aware scheduling under timing constraints for mission-critical embedded systems

Abstract: Power-aware systems are those that must make the best use of available power. They subsume traditional low-power systems in that they must not only minimize power when the budget is low, but also deliver high performance when required. This paper presents a new scheduling technique for supporting the design and evaluation of a class of power-aware systems in mission-critical applications. It satisfies stringent min/max timing and max power constraints. It also makes the best effort to satisfy the min power constraint in an attempt to fully utilize free power or to control power jitter. Experimental results show that our scheduler can improve performance and reduce energy cost simultaneously compared to hand-crafted designs for previous missions. This tool forms the basis of the IMPACCT system-level framework that will enable designers to explore many power-performance trade-offs with confidence.