Showing papers on "Low-power electronics published in 2002"

A low-power, low-noise CMOS amplifier for neural recording applications

Abstract: There is a need among scientists and clinicians for low-noise, low-power biosignal amplifiers capable of amplifying signals in the mHz to kHz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully-implantable multielectrode arrays has created the need for fully-integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudo-resistor to amplify signals down to the mHz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches that limit. The resulting amplifier, built in a standard 1.5/spl mu/m CMOS process, passes signals from 0.1mHz to 7.2kHz with an input-referred noise of 2.2/spl mu/Vrms and a power dissipation of 80/spl mu/W while consuming 0.16mm/sup 2/ of chip area.

Managing power and performance for system-on-chip designs using Voltage Islands

Abstract: This paper discusses Voltage Islands, a system architecture and chip implementation methodology, that can be used to dramatically reduce active and static power consumption for System-on-Chip (SoC) designs. As technology scales for increased circuit density and performance, the need to reduce power consumption increases in significance as designers strive to utilize the advancing silicon capabilities. The consumer product market further drives the need to minimize chip power consumption. Effective use of Voltage Islands for meeting SoC power and performance requirements, while meeting Time to Market (TAT) demands, requires novel approaches throughout the design flow as well as special circuit components and chip powering structures. This paper outlines methods being used today to design Voltage Islands in a rapid-TAT product development environment, and discusses the need for industry EDA advances to create an industry-wide Voltage Island design capability.

A power-optimal repeater insertion methodology for global interconnects in nanometer designs

Abstract: This paper addresses the problem of power dissipation during the buffer insertion phase of interconnect performance optimization. It is shown that the interconnect delay is actually very shallow with respect to both the repeater size and separation close to the minimum point. A methodology is developed to calculate the repeater size and interconnect length which minimizes the total interconnect power dissipation for any given delay penalty. This methodology is used to calculate the power-optimal buffering schemes for various ITRS technology nodes for 5% delay penalty. Furthermore, this methodology is also used to quantify the relative importance of the various components of the power dissipation for power-optimal solutions for various technology nodes.

Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates

Abstract: Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In this paper, we propose a technique to build a total of 41 new 10-transistor full adders using novel XOR and XNOR gates in combination with existing ones. We have done over 10,000 HSPICE simulation runs of all the different adders in different input patterns, frequencies, and load capacitances. Almost all those new adders consume less power in high frequencies, while three new adders consistently consume on average 10% less power and have higher speed compared with the previous 10-transistor full adder and the conventional 28-transistor CMOS adder. One draw back of the new adders is the threshold-voltage loss of the pass transistors.

The flipped voltage follower: a useful cell for low-voltage low-power circuit design

Abstract: In this paper a new basic cell for low-power and/or low-voltage operation is identified. It is shown that different versions of this cell, called "flipped voltage follower", have been used in the past for different applications. New circuits using this cell are also proposed here.

Subthreshold leakage modeling and reduction techniques

Abstract: As technology scales, subthreshold leakage currents grow exponentially and become an increasingly large component of total power dissipation. CAD tools to help model and manage subthreshold leakage currents will be needed for developing ultra low power and high performance integrated circuits. This paper gives an overview of current research to control leakage currents, with an emphasis on areas where CAD improvements will be needed. The first part of the paper explores techniques to model subthreshold leakage currents at the device, circuit, and system levels. Next, circuit techniques such as source biasing, dual Vt partitioning, MTCMOS, and VTCMOS are described. These techniques reduce leakage currents during standby states and minimize power consumption. This paper also explores ways to reduce total active power by limiting leakage currents and optimally trading off between dynamic and leakage power components.

A multigrid-like technique for power grid analysis

Abstract: Modern submicron very large scale integration designs include huge power grids that are required to distribute large amounts of current, at increasingly lower voltages. The resulting voltage drop on the grid reduces noise margin and increases gate delay, resulting in a serious performance impact. Checking the integrity of the supply voltage using traditional circuit simulation is not practical, for reasons of time and memory complexity. The authors propose a novel multigrid-like technique for the analysis of power grids. The grid is reduced to a coarser structure, and the solution is mapped back to the original grid. Experimental results show that the proposed method is very efficient as well as suitable for both de and transient analysis of power grids.

A 175 mV multiply-accumulate unit using an adaptive supply voltage and body bias (ASB) architecture

Abstract: In order to minimize total active power consumption in digital circuits, one must take into account subthreshold leakage currents that grow exponentially as technology scales. This research develops a theoretical model to predict how dynamic power and subthreshold power must be balanced to give an optimal V/sub DD//V/sub t/ operating point that minimizes total active power consumption for different workload and operating conditions. A 175-mV multiply-accumulate test chip using a triple-well technology with tunable supply and body bias values is measured to experimentally verify the tradeoffs between the various sources of power. The test chip shows that there is an optimum V/sub DD//V/sub t/ operating point, although it differs from the theoretical limit because of excessive forward bias currents. Finally, we propose a preliminary automatic supply and body biasing architecture (ASB) that automatically configures a circuit to operate with the lowest possible active power consumption.

A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling

Abstract: A PowerPC system-on-a-chip processor which makes use of dynamic voltage scaling and on-the-fly frequency scaling to adapt to the dynamically changing performance demands and power consumption constraints of high-content, battery powered applications is described. The PowerPC core and caches achieve frequencies as high as 380 MHz at a supply of 1.8 V and active power consumption as low as 53 mW at a supply of 1.0 V. The system executes up to 500 MIPS and can achieve standby power as low as 54 /spl mu/W. Logic supply changes as fast as 10 mV//spl mu/s are supported. A low-voltage PLL supplied by an on-chip regulator, which isolates the clock generator from the variable logic supply, allows the SOC to operate continuously while the logic supply voltage is modified. Hardware accelerators for speech recognition, instruction-stream decompression and cryptography are included in the SOC. The SOC occupies 36 mm/sup 2/ in a 0.18 /spl mu/m, 1.8 V nominal supply, bulk CMOS process.

Charge-pump circuits: power-consumption optimization

Abstract: In this paper, an optimized strategy for designing charge pumps with minimum power consumption is presented. The approach allows designers to define the number of stages that, for a given input, and an output voltage, maximize power efficiency. Capacitor value is then set to provide the current capability required. This approach was analytically developed and validated through simulations and experimental measurements on 0.35-/spl mu/m EEPROM CMOS technology. This approach was then compared with one which minimized the silicon area and it was shown that only a small increase in area is needed to minimize power consumption.

Optimal supply and threshold scaling for subthreshold CMOS circuits

Abstract: With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits have been inadequate for high performance applications, but have been used in applications that require ultra low power dissipation. Many applications including medical and wireless applications, require ultra low power dissipation with low-to-moderate performance (10kHz-100MHz). In this work, using BSIM3 models, the performance and energy dissipation of 0.18-/spl mu/m CMOS circuits for the range of V/sub dd/ = 0.1-0.6V and V/sub th/ = 0-0.6V are analyzed to show that subthreshold CMOS circuits can be used in low performance applications. A simple characterization circuit is introduced which can be used to evaluate the performance and energy dissipation for a given process under varying activity. These results are useful in circuit design by giving insight into optimal voltage supply and threshold voltage operation for a given application specification.

Analysis and comparison on full adder block in submicron technology

Abstract: In this paper the main topologies of one-bit full adders, including the most interesting of those recently proposed, are analyzed and compared for speed, power consumption, and power-delay product. The comparison has been performed on two classes of circuits, the former with minimum transistor size to minimize power consumption, the latter with optimized transistor dimension to minimize power-delay product. The investigation has been carried out with properly defined simulation runs on a Cadence environment using a 0.35-/spl mu/m process, also including the parasitics derived from layout. Performance has been also compared for different supply voltage values. Thus design guidelines have been derived to select the most suitable topology for the design features required. This paper also proposes a novel figure of merit to realistically compare n-bit adders implemented as a chain of one-bit full adders. The results differ from those previously published both for the more realistic simulations carried out and the more appropriate figure of merit used. They show that, except for short chains of blocks or for cases where minimum power consumption is desired, topologies with only pass transistors or transmission gates are not attractive. In contrast, the most interesting implementations in terms of trade off between power and delay are the traditional CMOS and mirror topologies. Moreover, the dual-rail domino and the CPL allow the best speed performance.

Adaptive supply serial links with sub-1-V operation and per-pin clock recovery

Abstract: The application of adaptive power-supply regulation is extended to serial links The adaptive supply maximizes the energy-efficiency of the I/O circuits and serves as a global bias to scale the link properties optimally with the bitrate Parallelism in transceivers and the use of multiphase clocks increase the bitrate to a multiple of the clock frequency and, hence, enable the low frequency low-voltage operation to reduce power while meeting the specified bitrate Two key designs to enable this power saving are presented: parallelized transceivers for low-voltage operation and dual-loop architecture phase/delay-locked loop for multiphase clock distribution A prototype chip fabricated in 025-/spl mu/m CMOS process operates at 065-50 Gb/s while dissipating 97-380 mW

Transconductance amplifier structures with very small transconductances: a comparative design approach

Abstract: A family of CMOS operational transconductance amplifiers (OTAs) has been designed for very small G/sub m/'s (of the order of nanoamperes per volt) with transistors operating in moderate inversion. Several OTA design schemes such as conventional, using current division, floating-gate, and bulk-driven techniques are discussed. A detailed comparison has also been made among these schemes in terms of performance characteristics such as power consumption, active silicon area, and signal-to-noise ratio. The transconductance amplifiers have been fabricated in a 1.2-/spl mu/m n-well CMOS process and operate at a power supply of 2.7 V. Chip test results are in good agreement with theoretical results.

Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

Abstract: Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. This paper presents two techniques for efficient gate clustering in MTCMOS circuits by modeling the problem via Bin-Packing (BP) and Set-Partitioning (SP) techniques. An automated solution is presented, and both techniques are applied to six benchmarks to verify functionality. Both methodologies offer significant reduction in both dynamic and leakage power over previous techniques during the active and standby modes respectively. Furthermore, the SP technique takes the circuit's routing complexity into consideration which is critical for Deep Sub-Micron (DSM) implementations. Sufficient performance is achieved, while significantly reducing the overall sleep transistors' area. Results obtained indicate that our proposed techniques can achieve on average 90% savings for leakage power and 15% savings for dynamic power.

Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints

Abstract: Dynamic voltage scaling (DVS) is a known effective mechanism for reducing CPU energy consumption without significant performance degradation. While a lot of work has been done on inter-task scheduling algorithms to implement DVS under operating system control, new research challenges exist in intra-task DVS techniques under software and compiler control. In this paper we introduce a novel intra-task DVS technique under compiler control using program checkpoints. Checkpoints are generated at compile time and indicate places in the code where the processor speed and voltage should be re-calculated. Checkpoints also carry user-defined time constraints. Our technique handles multiple intra-task performance deadlines and modulates power consumption according to a run-time power budget. We experimented with two heuristics for adjusting the clock frequency and voltage. For the particular benchmark studied, one heuristic yielded 63% more energy savings than the other. With the best of the heuristics we designed, our technique resulted in 82% energy savings over the execution of the program without employing DVS.

DRG-cache: a data retention gated-ground cache for low power

Abstract: In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (transistor threshold voltage) process. We utilize the concept of Gated-Ground [5] (NMOS transistor inserted between Ground line and SRAM cell) to achieve reduction in leakage energy without significantly affecting performance. Experimental results on gated-Ground caches show that data is retained (DRG-Cache) even if the memory are put in the stand-by mode of operation. Data is restored when the gated-Ground transistor is turned on. Turning off the gated-Ground transistor in turn gives large reduction in leakage power. This technique requires no extra circuitry; row decoder itself can be used to control the gated-Ground transistor. The technique is applicable to data and instruction caches as well as different levels of cache hierarchy such as the L1, L2, or L3 caches. We fabricated a test chip in TSMC 0.25m technology to show the data retention capability and the cell stability of DRG-cache. Our simulation results on 100nm and 70nm processes (Berkeley Predictive Technology Model) show 16.5% and 27% reduction in consumed energy in L1 cache and 50% and 47% reduction in L2 cache with less than 5% impact on execution time and within 4% increase in area overhead.

Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies

Abstract: A new high-speed domino circuit, called HS-Domino has been developed. HS-Domino resolves the tradeoff between performance and reliability in conventional CD-domino logic while dissipating low dynamic power with minimal area overhead. HS-Domino, therefore, extends domino's operation in the deep submicron regime. A multithreshold implementation of HS-Domino is also devised to achieve substantially low leakage values during standby, while maintaining high performance and low power during the active mode. Furthermore, the generic multithreshold scheme is applied to differential cascode voltage switch (DDCVS) logic.

Dynamic V/sub TH/ scaling scheme for active leakage power reduction

Abstract: We present a Dynamic V/sub TH/ Scaling (DVTS) scheme to save the leakage power during active mode of the circuit. The power saving strategy of DVTS is similar to that of the Dynamic V/sub DD/ Scaling (DVS) scheme, which adaptively changes the supply voltage depending on the current workload of the system. Instead of adjusting the supply voltage, DVTS controls the threshold voltage by means of body bias control, in order to reduce the leakage power. The power saving potential of DVTS and its impact on dynamic and leakage power when applied to future technologies are discussed. Pros and cons of the DVTS system are dealt with in detail. Finally, a feedback loop hardware for the DVTS which tracks the optimal V/sub TH/ for a given clock frequency, is proposed. Simulation results show that 92% energy savings can be achieved with DVTS for 70 nm circuits.

Load adaptive medium frequency resonant power supply

Abstract: The fast development in low power electronics, micro-systems technology and wireless communication enables totally new system concepts that call for new and cheap supply options. In several applications wired energy transfer is not suitable or possible, for example in robot type applications or in fully automated production machines as well as in medium or high voltage applications with high insulation requirements. There are solutions where nonconventional transformers with, for example, a large air-gap in the magnetic path, are operated with resonant switch mode supplies to supply energy to the load. In this paper we present a resonant supply converter system enabling totally wireless applications by providing auxiliary energy without wires via magnetic fields over distances of up to several meters and covering volumes of e.g. 100 m/sup 3/, suited for the wireless supply of robot applications or highly automated manufacturing machines (sensors, communication, actuators).

Duet: an accurate leakage estimation and optimization tool for dual-V/sub t/ circuits

Abstract: Presents a new approach for the estimation and optimization of standby power dissipation in large MOS digital circuits. We introduce a new approach for accurate and efficient calculation of the average standby or leakage current in large digital circuits by introducing the concepts of "dominant leakage states" and the use of state probabilities. Combined with graph reduction techniques and simplified nonlinear simulation, the method achieves speedups of three to four orders of magnitude over exhaustive SPICE simulations while maintaining very good accuracy. The leakage current calculation is then utilized in a new leakage and performance optimization algorithm for circuits using dual V/sub t/ processes. The approach is the first to consider the assignment of both the V/sub t/ and the width of a transistor, simultaneously. The optimization approach uses incremental calculation of leakage and performance sensitivities and can take into account a partially defined circuit state constraint for the standby mode of the device.

Life is CMOS: why chase the life after?

Abstract: This paper discusses potential solutions to the CMOS device technology scaling at gate lengths approaching 10 nm. Promising circuit and design techniques to control leakage power are described. Energy-efficient microarchitecture trends for general-purpose microprocessors are elucidated.

Controlling peak power during scan testing

Abstract: This paper presents a procedure for modifying a given set of scan vectors so that the peak power during scan testing is kept below a specified limit without reducing fault coverage. The proposed approach works for any conventional full-scan design-no extra design-for-test (DFT) logic is required. If the peak power in a clock cycle during scan testing exceeds a specified limit (which depends on the amount of peak power that can be safely handled without causing a failure that would not occur during normal functional operation) then a "peak power violation" occurs. Given a set of scan vectors, simulation is done to identify and classify the scan vectors that are causing peak power violations during scan testing. The problem scan vectors are then modified in a way that eliminates the peak power violations while preserving the fault coverage. Experimental results indicate the proposed procedure is very effective in controlling peak power.

A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop

Abstract: A 1.5-V 5.5-GHz fully integrated phase-locked loop (PLL) has been implemented in a 0.25-/spl mu/m foundry digital CMOS process. From a 5.5-GHz carrier, the in-band phase noise can be as low as -88 dBc/Hz at a 40-kHz offset, while the phase noise for the free-running VCO is -116 dBc/Hz at an 1-MHz offset. The VCO core current is 4.6 mA. The prescaler is implemented using a variation of the source-coupled logic (SCL) structure to reduce the switching noise, and thus to reduce the PLL side-band spurs. At -18 dBm signal power measured off chip, the switching noise coupled through substrate and metal interconnect generates spurs with power levels less than -99 dBm when the loop is open. A new charge-pump circuit is developed to reduce the current glitch at the output node. By incorporating a voltage doubler, the voltage dynamic range at the charge-pump output and thus the VCO control voltage range is increased from 1.3 to 2.6 V with immeasurable phase noise and spurious level degradation to the PLL. When the loop is closed, the power levels of side-band spurs at the offset frequency equal to the /spl sim/43-MHz reference frequency are < -69 dBc. The total power consumption of the PLL including that for the output buffers is /spl sim/23 mW.

Low-power clock distribution using multiple voltages and reduced swings

Abstract: Clock networks account for a significant fraction of the power dissipation of a chip and are critical to performance. This paper presents theory and algorithms for building a low-power clock tree by distributing the clock signal at a lower voltage and translating it to a higher voltage at the utilization points. Two low-power schemes are used: reduced swing and multiple-supply voltages. We analyze the issue of tree construction and present conclusions relevant to various technology generations according to the NTRS. Our experimental results show that power savings of an average of 45% are possible for a 0.25 /spl mu/m technology using multiple supply voltages, and about 32% using a single external supply voltage.

Power driven chaining of flip-flops in scan architectures

Abstract: Power consumption during scan testing is becoming a primary concern. In this paper, we present a novel approach for scan cell ordering which significantly reduces the power consumed during scan testing. The proposed approach is based on the use of a two-step heuristic procedure that can be exploited by any chip layout program during scan flip-flops placement and routing. The proposed approach works for any conventional scan design and offers numerous advantages compared with existing low power scan techniques. Reductions of average and peak power consumption during scan testing are up to 58% and 24% respectively for experimented ISCAS benchmark circuits.

Evaluating Run-Time Techniques for Leakage Power Reduction

Abstract: While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimizations and are applied at run-time. We focus our study on the latter kind and compare three techniques: input vector control, body bias control and power supply gating. We determine their limits and benefits, in terms of the potential leakage reduction, performance penalty and area and power overhead. The importance of the 'minimum idle time' parameter, as an additional evaluation tool, is emphasized, as well as the feasibility of achieving power supply gating at low levels of granularity. The obtained data supports the formulation of a comprehensive leakage reduction scheme, in which each technique is targeted for certain types of functional units and a given level of granularity depending on the incurred overhead cost and the obtainable savings.

Leakage power analysis and reduction during behavioral synthesis

Abstract: This paper presents a high-level leakage power analysis and reduction algorithm. The algorithm uses device-level models for leakage to precharacterize a given register-transfer level module library. This is used to estimate the power consumption of a circuit due to leakage. The algorithm can also identify and extract the frequently idle modules in the datapath, which may be targeted for low-leakage optimization. Leakage optimization is based on the use of dual threshold voltage (V/sub T/) technology. The algorithm prioritizes modules giving a high-level synthesis system an indication of where most gains for leakage reduction may be found. We tested our algorithm using a number of benchmarks from various sources. We ran a series of experiments by integrating our algorithm into a low-power high-level synthesis system. In addition to reducing the power consumption due to switching activity, our algorithm provides the high-level synthesis system with the ability to detect and reduce leakage power consumption, hence, further reducing total power consumption. This is shown over a number of technology generations. The trend in these generations indicates that leakage becomes the dominant component of power at smaller feature size and lower supply voltages. Results show that using a dual-V/sub T/ library during high-level synthesis can reduce leakage power by an average of 58% for the different technology generations. Total power can be reduced by an average of 15.0%-45.0% for 0.18-0.07 /spl mu/m technologies, respectively. The contribution of leakage power to overall power consumption ranges from 22.6% to 56.2%. Our approach reduced these values to 11.7%-26.9%.

CMOS dynamic comparators for pipeline A/D converters

Abstract: Three different CMOS dynamic comparator topologies for pipeline A/D converters, resistive divider, differential pair, and charge distribution comparators, are analyzed. The topologies considered are fully differential, i.e. both sensing and reference voltage inputs are balanced, consist only of a single stage, and feature zero DC power dissipation with a built-in threshold adjusting input stage. Test structures of the comparators, fabricated in 0.35-/spl mu/m CMOS process, are measured to determine the offset properties of the compared topologies.

4 Gbps high-density AC coupled interconnection

Abstract: AC coupled interconnects enable multi-gigabit-persecond communication data rates between integrated circuits with very high pin counts and low power consumption. AC coupling can be realized with either series capacitive or inductive coupling elements. Capacitive AC coupling offers better performance when low power I/O buffers are required and when there is sufficient area to dedicate to coupling capacitors in the top-level metal of each IC. At a slight expense of circuit complexity, inductive AC coupling can be used to bring I/O pad pitches down to 75 /spl mu/m and maintain a controlled impedance connection. A novel physical structure, buried solder bumps, are used as a solution for providing DC power and ground connections across the same surface as the AC connections. When used in conjunction with NRZ-tolerant receivers, and current-mode signaling, highly effective interconnect structures can be built. As well as presenting both physical and circuit aspects of this work, experimental results are shown.