Showing papers on "Low-power electronics published in 2009"

Low Power Design Methodologies

Abstract: Preface. 1. Introduction J.M. Rabaey, et al. Part I: Technology and circuit design levels. 2. Device and technology impact on low power electronics Chenming Hu. 3. Low power circuit technologies C. Svensson, Dake Liu. 4. Energy-recovery CMOS W.C. Athas. 5. Low power clock distribution J.G. Xi, W.W.-M. Dai. Part II: Logic and module design levels. 6. Logic synthesis and module design levels M. Pedram. 7. Low power arithmetic components T.K. Callawy, E.E. Schwartzlander. 8. Low power memory design K. Itoh. Part III: Architecture and system design levels. 9. Low-power microprocessor design S. Gary. 10. Portable video-on-demand in wireless communication T.H. Meng, et al. 11. Algorithm and architectural level methodologies R. Mehra, et al. Index.

An efficient piezoelectric energy-harvesting interface circuit using a bias-flip rectifier and shared inductor

Abstract: Energy harvesting is an emerging technology with applications to handheld, portable and implantable electronics. Harvesting ambient vibration energy through piezoelectric (PE) means is a popular energy harvesting technique that can potentially supply 10 to 100's of µW of available power [1]. One of the limitations of existing PE harvesters is in their interface circuitry. Commonly used full-bridge rectifiers and voltage doublers [2] severely limit the electrical power extractable from a PE harvesting element. Further, the power consumed in the control circuits of these harvesters reduces the amount of usable electrical power. In this paper, a bias-flip rectifier that can improve upon the power extraction capability of existing full-bridge rectifiers by up to 4.2× is presented. An efficient control circuit with embedded DC-DC converters that can share their filter inductor with the bias-flip rectifier thereby reducing the volume and component count of the overall solution is demonstrated.

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

Abstract: Ultra-low voltage operation of memory cells has become a topic of much interest due to its applications in very low energy computing and communications. However, due to parameter variations in scaled technologies, stable operation of SRAMs is critical for the success of low-voltage SRAMs. It has been shown that conventional 6T SRAMs fail to achieve reliable subthreshold operation. Hence, researchers have considered different configuration SRAMs for subthreshold operations having single-ended 8T or 10T bit-cells for improved stability. While these bit-cells improve SRAM stability in subthreshold region significantly, the single-ended sensing methods suffer from reduced bit-line swing due to bit-line leakage noise. In addition, efficient bit-interleaving in column may not be possible and hence, the multiple-bit soft errors can be a real issue. In this paper, we propose a differential 10T bit-cell that effectively separates read and write operations, thereby achieving high cell stability. The proposed bit-cell also provides efficient bit-interleaving structure to achieve soft-error tolerance with conventional Error Correcting Codes (ECC). For read access, we employ dynamic DCVSL scheme to compensate bitline leakage noise, thereby improving bitline swing. To verify the proposed techniques, a 32 kb array of the proposed 10T bit-cell is fabricated in 90 nm CMOS technology. The hardware measurement results demonstrate that this bit-cell array successfully operates down to 160 mV. For leakage power comparison, we also fabricated 49 kb arrays of the 6T and the proposed 10T bit-cells. Measurement results show that the leakage power of the proposed bit-cell is close to that of the 6T (between 0.96x and 1.22x of 6T).

A 90 nm CMOS Low-Power 60 GHz Transceiver With Integrated Baseband Circuitry

Abstract: This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and 138 mW while receiving. Data transmission up to 5 Gb/s on each of I and Q channels has been measured, as has data reception over a 1 m wireless link at 4 Gb/s QPSK with less than 10-11 BER.

A 300 nW, 15 ppm/ $^{\circ}$ C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs

Abstract: A low-power CMOS voltage reference was developed using a 0.35 mum standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, which was about 745 mV for the MOSFETs we used. The temperature coefficient of the voltage was 7 ppm/degC at best and 15 ppm/degC on average, in a range from - 20 to 80degC. The line sensitivity was 20 ppm/V in a supply voltage range of 1.4-3 V, and the power supply rejection ratio (PSRR) was -45 dB at 100 Hz. The power dissipation was 0.3 muW at 80degC. The chip area was 0.05 mm2 . Our device would be suitable for use in subthreshold-operated, power-aware LSIs.

High Speed, High Stability and Low Power Sensing Amplifier for MTJ/CMOS Hybrid Logic Circuits

Abstract: Densely embedding Magnetic Tunnel Junctions (MTJ) in CMOS logic circuits is considered as one potentially powerful solution to bring non volatility, instant on/off and low standby power in today's programmable logic circuits, in order to overcome major drawbacks while preserving high operation speed. A critical issue in this process is the integration of MTJ electric signal to CMOS electronics, in particular the requirement of ldquozerordquo read/write error for logic applications. In this paper, we propose a new sense amplifier circuit, called Pre-Charge Sense Amplifier (PCSA). This circuit, comprising 7 CMOS transistors at minimum size, is able to read the magnetic configuration of a pair of magnetic tunnel junctions with opposite configurations at high speed (about 200 ps), with very low power and error rate compared to previously proposed solutions. Simulations using a ST Microelectronics 90 nm design kit and a compact model of MTJ demonstrate the performances of PCSA.

The digital silicon photomultiplier — Principle of operation and intrinsic detector performance

Abstract: We developed a fully digital implementation of the Silicon Photomultiplier. The sensor is based on a single photon avalanche photodiode (SPAD) integrated in a standard CMOS process. Photons are detected directly by sensing the voltage at the SPAD anode using a dedicated cell electronics block next to each diode. This block also contains active quenching and recharge circuits as well as a one bit memory for the selective inhibit of detector cells. A balanced trigger network is used to propagate the trigger signal from all cells to the integrated time-to-digital converter (TDC). Photons are detected and counted as digital signals, thus making the sensor less susceptible to temperature variations and electronic noise. The integration with CMOS logic has the added benefit of low power consumption and possible integration of data post-processing. In this paper, we discuss the sensor architecture and present first measurements of the technology demonstrator test chip.

Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits

Abstract: In this paper, novel n- and p-type tunnel field-effect transistors (T-FETs) based on heterostructure Si/intrinsic-SiGe channel layer are proposed, which exhibit very small subthreshold swings, as well as low threshold voltages. The design parameters for improvement of the characteristics of the devices are studied and optimized based on the theoretical principles and simulation results. The proposed devices are designed to have extremely low off currents on the order of 1 fA/mum and engineered to exhibit substantially higher on currents compared with previously reported T-FET devices. Subthreshold swings as low as 15 mV/dec and threshold voltages as low as 0.13 V are achieved in these devices. Moreover, the T-FETs are designed to exhibit input and output characteristics compatible with CMOS-type digital-circuit applications. Using the proposed n- and p-type devices, the implementation of an inverter circuit based on T-FETs is reported. The performance of the T-FET-based inverter is compared with the 65-nm low-power CMOS-based inverter, and a gain of ~104 is achieved in static power consumption for the T-FET-based inverter with smaller gate delay.

A 65 nm Sub- $V_{t}$ Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter

Abstract: Aggressive supply voltage scaling to below the device threshold voltage provides significant energy and leakage power reduction in logic and SRAM circuits. Consequently, it is a compelling strategy for energy-constrained systems with relaxed performance requirements. However, effects of process variation become more prominent at low voltages, particularly in deeply scaled technologies. This paper presents a 65 nm system-on-a-chip which demonstrates techniques to mitigate variation, enabling sub-threshold operation down to 300 mV. A 16-bit microcontroller core is designed with a custom sub-threshold cell library and timing methodology to address output voltage failures and propagation delays in logic gates. A 128 kb SRAM employs an 8 T bit-cell to ensure read stability, and peripheral assist circuitry to allow sub-Vt reading and writing. The logic and SRAM function in the range of 300 mV to 600 mV, consume 27.2 pJ/cycle at the optimal V DD of 500 mV, and 1 muW standby power at 300 mV. To supply variable voltages at these low power levels, a switched capacitor DC-DC converter is integrated on-chip and achieves above 75% efficiency while delivering between 10 muW to 250 muW of load power.

A 52 $\mu$ W Wake-Up Receiver With $-$ 72 dBm Sensitivity Using an Uncertain-IF Architecture

Abstract: A dedicated wake-up receiver may be used in wireless sensor nodes to control duty cycle and reduce network latency. However, its power dissipation must be extremely low to minimize the power consumption of the overall link. This paper describes the design of a 2 GHz receiver using a novel ldquouncertain-IFrdquo architecture, which combines MEMS-based high-Q filtering and a free-running CMOS ring oscillator as the RF LO. The receiver prototype, implemented in 90 nm CMOS technology, achieves a sensitivity of -72 dBm at 100 kbps (10-3 bit error rate) while consuming just 52 muW from the 0.5 V supply.

A Low-Power Low-Cost Fully-Integrated 60-GHz Transceiver System With OOK Modulation and On-Board Antenna Assembly

Abstract: Emerging research on 60GHz RF transceivers has demonstrated extensive usage of short-distance communications. One key application is the fast file-transfer system for consumer products, e.g., video download from a kiosk or link between a digital camera and a laptop, where high-speed (a few Gb/s) and low-power (≪0.3W) wireless communication is required for short distance (≪10cm). Existing 60GHz solutions [1] inheriting the well-developed architecture from 2.4/5GHz systems consume significant power primarily because of the interface (ADCs) and the subsequent baseband circuits (DSPs). This paper presents a compact solution for a 60GHz transceiver system including on-board antennae and on-off-keying (OOK) modulation. This prototype avoids the above issues and achieves error-free operation (BER≪10−12) for 231−1 PRBS of 2.5Gb/s over a distance of 4cm while consuming a total power of only 286mW.

Very-High-Frequency Resonant Boost Converters

Abstract: This paper presents a resonant boost topology suitable for very-high-frequency (VHF, 30-300 MHz) DC-DC power conversion. The proposed design features low device voltage stress, high efficiency over a wide load range, and excellent transient performance. Two experimental prototypes have been built and evaluated. One is a 110-MHz, 23-W converter that uses a high-performance RF lateral DMOSFET. The converter achieves higher than 87% efficiency at nominal input and output voltages, and maintains good efficiency down to 5% of full load. The second implementation, aimed toward integration, is a 50-MHz, 17-W converter that uses a transistor from a 50-V integrated power process. In addition, two resonant gate drive schemes suitable for VHF operation are presented, both of which provide rapid startup and low-loss operation. Both converters regulate the output using high-bandwidth, on-off hysteretic control, which enables fast transient response and efficient light-load operation. The low energy storage requirements of the converters allow the use of aircore inductors in both designs, thereby eliminating magnetic core loss and introducing the possibility of easy integration.

Bilayer PseudoSpin Field-Effect Transistor (BiSFET): A Proposed New Logic Device

Abstract: We propose a new type of graphene-based transistor intended to allow lower voltage, lower power operation than possible with complementary metal-oxide-semiconductor (CMOS) field-effect transistors. Increased energy efficiency is not only important for its own sake, but is also necessary to allow continued device scaling and the resulting increase in computational power in CMOS-like logic circuits. We describe the basic device structure and physics and predicted current-voltage characteristics. Advantages over CMOS in terms of lower voltage and power are discussed.

A Fully Integrated Dual-Mode Highly Linear 2.4 GHz CMOS Power Amplifier for 4G WiMax Applications

Abstract: In recent years, there has been tremendous interest in trying to implement the power amplifier in CMOS, due to its cost and integration benefits. Most of the high power (watt-level) CMOS PAs reported to date have not exhibited sufficient linearity required for next generation wireless standards. In this paper, we report a single-chip linear CMOS PA with sufficient power and linearity for emerging OFDM-based 4G WiMAX applications. This 90 nm 2.4 GHz CMOS linear power amplifier uses a two-stage transformer-based power combiner and produces a saturated output power of 30.1 dBm with 33% PAE and 28 dB small-signal gain. A novel bypass network is introduced to ensure stability without sacrificing gain. The choice of optimal biasing and capacitive compensation produces very flat AM-AM and AM-PM response up to high power. The PA has been tested with OFDM modulated signal and produces EVM better than -25 dB at 22.7 dBm average power. Graceful power back-off is demonstrated through turning off one of the stages, allowing low-power operation with enhanced efficiency.

Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating

Abstract: A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes are promising approaches for low-power design. We propose four novel energy recovery clocked flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. The proposed flip-flops operate with a single-phase sinusoidal clock, which can be generated with high efficiency. In the TSMC 0.25-mum CMOS technology, we implemented 1024 proposed energy recovery clocked flip-flops through an H-tree clock network driven by a resonant clock-generator to generate a sinusoidal clock. Simulation results show a power reduction of 90% on the clock-tree and total power savings of up to 83% as compared to the same implementation using the conventional square-wave clocking scheme and flip-flops. Using a sinusoidal clock signal for energy recovery prevents application of existing clock gating solutions. In this paper, we also propose clock gating solutions for energy recovery clocking. Applying our clock gating to the energy recovery clocked flip-flops reduces their power by more than 1000times in the idle mode with negligible power and delay overhead in the active mode. Finally, a test chip containing two pipelined multipliers one designed with conventional square wave clocked flip-flops and the other one with the proposed energy recovery clocked flip-flops is fabricated and measured. Based on measurement results, the energy recovery clocking scheme and flip-flops show a power reduction of 71% on the clock-tree and 39% on flip-flops, resulting in an overall power savings of 25% for the multiplier chip.

Power conditioning circuit topologies

Abstract: This article provides an overview of PCS architectures and circuit topologies for low-voltage energy source in single-phase grid-tie applications. The discussion was focused on those relatively new but practical system architectures and circuit topologies including dc-dc converters and dc-ac inverters.

Interests and Limitations of Technology Scaling for Subthreshold Logic

Abstract: Subthreshold logic is an efficient technique to achieve ultralow energy per operation for low-to-medium throughput applications. In this paper, the interests and limitations of technology scaling for subthreshold logic are investigated from 0.25 mum to 32 nm nodes. Scaling to 90/65 nm nodes is shown to be highly desirable for medium-throughput applications (1-10 MHz) due to great dynamic energy reduction. However, this interest is limited at 45/32 nm nodes by high static energy due to degraded subthreshold swing and delay variability. Moreover, for low-throughput applications (10-100 kHz), this limitation is worsened by the increase of minimum supply voltage to achieve sufficient functional yield, which results in bad energy efficiency starting at 0.13 mum node. Upsizing the channel length is proposed as a straightforward circuit-level technique to efficiently mitigate these effects. At 32 nm node, this technique reduces energy per operation by 60% at medium throughput and by two orders of magnitude at low throughput.

Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters

Abstract: A very important limitation of high-speed analog-to-digital converters (ADCs) is their power dissipation. ADC power dissipation has been examined several times, mostly empirically. In this paper, we present an attempt to estimate a lower bound for the power of ADCs, based on first principles and using pipeline and flash architectures as examples. We find that power dissipation of high-resolution ADCs is bound by noise, whereas technology is the limiting factor for low-resolution devices. Our model assumes the use of digital error correction, but we also study an example on the power penalty due to matching requirements. A comparison with published experimental data indicates that the best ADCs use about 50 times the estimated minimum power. Two published ADCs are used for a more detailed comparison between the minimum bound and today's designs.

Energy-Efficient Subthreshold Processor Design

Abstract: Subthreshold circuits have drawn a strong interest in recent ultralow power research. In this paper, we present a highly efficient subthreshold microprocessor targeting sensor application. It is optimized across different design stages including ISA definition, microarchitecture evaluation and circuit and implementation optimization. Our investigation concludes that microarchitectural decisions in the subthreshold regime differ significantly from that in conventional superthreshold mode. We propose a new general-purpose sensor processor architecture, which we call the Subliminal Processor. On the circuit side, subthreshold operation is known to exhibit an optimal energy point (Knin)- However, propagation delay also becomes more sensitive to process variation and can reduce the energy scaling gain. We conduct thorough analysis on how supply voltage and operating frequency impact energy efficiency in a statistical context. With careful library cell selection and robust static RAM design, the Subliminal Processor operates correctly down to 200 mV in a 0.13-mum technology, which is sufficiently low to operate at Vmin . Silicon measurements of the Subliminal Processor show a maximum energy efficiency of 2.6 pJ/instruction at 360 mV supply voltage and 833 kHz operating frequency. Finally, we examine the variation in frequency and Vmin across die to verify our analysis of adaptive tuning of the clock frequency and Vmin for optimal energy efficiency.

A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip

Abstract: Networks-on-chip (NoCs) can improve the communication bandwidth and power efficiency of multiprocessor systems-on-chip (MPSoC). However, traditional metallic interconnects consume significant amount of power to deliver even higher communication bandwidth required in the near future. Optical NoCs are based on optical interconnects and optical routers, and have significant bandwidth and power advantages. This paper proposed a high-performance low-power low-cost optical router, Cygnus, for optical NoCs. Cygnus is non-blocking and based on silicon microresonators. We compared Cygnus with other microresonator-based routers, and analyzed their power consumption, optical power insertion loss, and the number of microresonators used in detail. The results show that Cygnus has the lowest power consumption and losses, and requires the lowest number of microresonators. For example, Cygnus has 50% less power consumption, 51% less optical power insertion loss, and 20% less microresonators than the optimized traditional optical crossbar router. Comparing to a high-performance 45nm electronic router, Cygnus consumes 96% less power. Moreover, the passive routing feature of Cygnus guarantees that, while using dimension order routing algorithm, the maximum power consumption to route a packet through a network is a small constant number, regardless of the network size. For example, the maximum power consumption is 4.80fJ/bit under current technologies. We simulated and analyzed an 8x8 2D mesh NoC built from Cygnus and showed the end-to-end delay and network throughput under different offered loads and packet sizes.

A 90-W Peak Power GaN Outphasing Amplifier With Optimum Input Signal Conditioning

Abstract: A 90-W peak-power 2.14-GHz improved GaN outphasing amplifier with 50.5% average efficiency for wideband code division multiple access (W-CDMA) signals is presented. Independent control of the branch amplifiers by two in-phase/quadrature modulators enables optimum outphasing and input power leveling, yielding significant improvements in gain, efficiency, and linearity. In deep-power backoff operation, the outphasing angle of the branch amplifiers is kept constant below a certain power level. This results in class-B operation for the very low output power levels, yielding less reactive loading of the output stages, and therefore, improved efficiency in power backoff operation compared to the classical outphasing amplifiers. Based on these principles, the optimum design parameters and input signal conditioning are discussed. The resulting theoretical maximum achievable average efficiency for W-CDMA signals is presented. Experimental results support the foregoing theory and show high efficiency over a large bandwidth, while meeting the linearity specifications using low-cost low-complexity memoryless pre-distortion. These properties make this amplifier concept an interesting candidate for future multiband base-station implementations.

A Low-Voltage Processor for Sensing Applications With Picowatt Standby Mode

Abstract: Recent progress in ultra-low-power circuit design is creating new opportunities for cubic millimeter computing. Robust low-voltage operation has reduced active mode power consumption considerably, but standby mode power consumption has received relatively little attention from low-voltage designers. In this work, we describe a low-voltage processor called the Phoenix Processor that has been designed at the device, circuit, and architecture levels to minimize standby power. A test chip has been implemented in a carefully selected 0.18 mum process in an area of only 915 times 915 mum2. Measurements show that Phoenix consumes 35.4 pW in standby mode and 226 nW in active mode.

Indoor power harvesting using photovoltaic cells for low power applications

Abstract: Utilization of low power indoor devices such as remote sensors, supervisory and alarm systems, distributed controls, and data transfer system are on steady rise. Due to remote and distributed nature of these systems, it is attractive to avoid using electrical wiring to supply power to them. Primary batteries have been used for this application for many years but they require regular maintenance at usually hard to access places. This paper provides a complete analysis of a PV harvesting system for indoor low power applications. The characteristics of a target load, photovoltaic (PV) cell and power conditioning circuit are discussed. Different choices of energy storage are also explained. Implementation and test results of the system are presented that highlights the practical issues and limitations of the system.

Capacitive Power Management Circuit for Micropower Thermoelectric Generators With a 1.4 $\mu$ A Controller

Abstract: Power autonomy is an important requirement for wireless sensor nodes. Thermoelectric generators can produce sufficient power for low power applications. Due to varying temperature, a power management circuit will be required. This paper presents such a power management circuit, realized in the AMIS I3T80 CMOS technology. It contains a Dickson charge pump with a variable number of stages as a DC/DC converter. A controller optimizes the number of stages of the charge pump, consuming 1.4 muA. The maximum efficiency of the charge pump is 82%, leading to a total efficiency that can reach up to 58%.

A 12-bit vernier ring time-to-digital converter in 0.13μm CMOS technology

Abstract: A novel 12-bit Vernier ring time-to-digital converter (TDC) with 8ps of time resolution for digital-phase-locked-loop applications is presented. The TDC achieves a large detectable range of 32ns. The core of the TDC occupies 0.75 × 0.35 mm2 in a 0.13um CMOS technology. The total power consumption for the entire TDC chip is only 7.5mW with a 1.5V power supply at a sample rate of 15MSps.

A Fully Integrated 900-MHz Passive RFID Transponder Front End With Novel Zero-Threshold RF–DC Rectifier

Abstract: This paper presents a fully integrated CMOS analog front end for a passive 900-MHz radio-frequency identification (RFID) transponder. The power supply in this front end is generated from the received RF electromagnetic energy by using an RF-dc voltage rectifier. In order to improve the compatibility with standard CMOS technology, Schottky diodes in conventional RF-dc rectifiers are replaced by diode-connected MOS transistors with zero threshold. Meanwhile, theoretical analyses for the proposed rectifier are provided and verified by both simulation and measurement results. The design considerations of the pulsewidth-modulation (PWM) demodulator and the backscatter modulator in the front end are also discussed for low-power applications. The proposed front end is implemented in a 0.35-mum 2P4M CMOS technology. The whole chip occupies a die area of 490 times 780 mum2 and consumes only 2.1 muW in reading mode under a self-generated 1.5-V supply voltage. The measurement results show that the proposed rectifier can properly operate with a -14.7-dBm input RF power at a power conversion efficiency of 13.0%. In the proposed RFID applications, this sensitivity corresponds to 10.88-m communication distance at 4-W equivalent isotropically radiated power from a reader base station.

A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS

Abstract: In modern ICs, the trend of integrating more on-chip memories on a die has led SRAMs to account for a large fraction of total area and energy of a chip. Therefore, designing memories with dynamic voltage scaling (DVS) capability is important since significant active as well as leakage power savings can be achieved by voltage scaling. However, optimizing circuit operation over a large voltage range is not trivial due to conflicting trade-offs of low-voltage (moderate and weak inversion) and high-voltage (strong inversion) transistor characteristics. Specifically, low-voltage operation requires various assist circuits for functionality which might severely impact high-voltage performance. Reconfigurable assist circuits provide the necessary adaptability for circuits to adjust themselves to the requirements of the voltage range that they are operating in. This paper presents a 64 kb reconfigurable SRAM fabricated in 65 nm low-power CMOS process operating from 250 mV to 1.2 V. This wide supply range was enabled by a combination of circuits optimized for both subthreshold and above-threshold regimes and by employing hardware reconfigurability. Three different write-assist schemes can be selectively enabled to provide write functionality down to very low voltage levels while preventing excessive power overhead. Two different sense-amplifiers are implemented to minimize sensing delay over a large voltage range. A prototype test chip is tested to be operational at 20 kHz with 250 mV supply and 200 MHz with 1.2 V supply. Over this range leakage power scales by more than 50 X and a minimum energy point is achieved at 0.4 V with less than 0.1 pJ/bit/access.

A High-Speed CMOS Image Sensor With Column-Parallel Two-Step Single-Slope ADCs

Abstract: This paper proposes a column-parallel two-step single-slope (SS) ADC for high-speed CMOS image sensors. Error correction scheme to improve the linearity is proposed as well. A prototype sensor of 320 times 240 pixels has been fabricated with a 0.35-mum CMOS process. Measurement results demonstrate that the proposed ADC can achieve the conversion time of 4 mus , which is ten times faster than the conventional SS ADC. The proposed error correction effectively removes the dead band problem and yields DNL of +0.53/ -0.78 LSB and INL of +1.42/ -1.61 LSB. The power consumption is 36 mW from a supply voltage of 2.8 V.