Showing papers on "Low-power electronics published in 2010"

Low-Voltage Tunnel Transistors for Beyond CMOS Logic

Abstract: Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.

Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits

Abstract: Power has become the primary design constraint for chip designers today. While Moore's law continues to provide additional transistors, power budgets have begun to prohibit those devices from actually being used. To reduce energy consumption, voltage scaling techniques have proved a popular technique with subthreshold design representing the endpoint of voltage scaling. Although it is extremely energy efficient, subthreshold design has been relegated to niche markets due to its major performance penalties. This paper defines and explores near-threshold computing (NTC), a design space where the supply voltage is approximately equal to the threshold voltage of the transistors. This region retains much of the energy savings of subthreshold operation with more favorable performance and variability characteristics. This makes it applicable to a broad range of power-constrained computing segments from sensors to high performance servers. This paper explores the barriers to the widespread adoption of NTC and describes current work aimed at overcoming these obstacles.

A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

Abstract: A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes the reset time of the preamplifier to improve the conversion speed. Measurement results on a 90 nm CMOS prototype operated at 1.2 V supply show 3 mW total power consumption with a peak SNDR of 56.6 dB and a FOM of 77 fJ/conv-step.

A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting

Abstract: This paper presents a low power boost converter for thermoelectric energy harvesting that demonstrates an efficiency that is 15% higher than the state-of-the-art for voltage conversion ratios above 20. This is achieved by utilizing a technique allowing synchronous rectification in the discontinuous conduction mode. A low-power method for input voltage monitoring is presented. The low input voltage requirements allow operation from a thermoelectric generator powered by body heat. The converter, fabricated in a 0.13 ?m CMOS process, operates from input voltages ranging from 20 mV to 250 mV while supplying a regulated 1 V output. The converter consumes 1.6 (1.1) ?W of quiescent power, delivers up to 25 (175) ?W of output power, and is 46 (75)% efficient for a 20 mV and 100 mV input, respectively.

A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting

Abstract: This paper presents a low power boost converter for thermoelectric energy harvesting that demonstrates an efficiency that is 15% higher than the state-of-the-art for voltage conversion ratios above 20. This is achieved by utilizing a technique allowing synchronous rectification in the discontinuous conduction mode. A low-power method for input voltage monitoring is presented. The low input voltage requirements allow operation from a thermoelectric generator powered by body heat. The converter, fabricated in a 0.13 μm CMOS process, operates from input voltages ranging from 20 mV to 250 mV while supplying a regulated 1 V output. The converter consumes 1.6 (1.1) μW of quiescent power, delivers up to 25 (175) μW of output power, and is 46 (75)% efficient for a 20 mV and 100 mV input, respectively.

Ultralow-Power Design in Near-Threshold Region

Abstract: Operation in the subthreshold region most often is synonymous to minimum-energy operation. Yet, the penalty in performance is huge. In this paper, we explore how design in the moderate inversion region helps to recover some of that lost performance, while staying quite close to the minimum-energy point. An energy-delay modeling framework that extends over the weak, moderate, and strong inversion regions is developed. The impact of activity and design parameters such as supply voltage and transistor sizing on the energy and performance in this operational region is derived. The quantitative benefits of operating in near-threshold region are established using some simple examples. The paper shows that a 20% increase in energy from the minimum-energy point gives back ten times in performance. Based on these observations, a pass-transistor based logic family that excels in this operational region is introduced. The logic family operates most of its logic in the above-threshold mode (using low-threshold transistors), yet containing leakage to only those in subthreshold. Operation below minimum-energy point of CMOS is demonstrated. In leakage-dominated ultralow-power designs, time-multiplexing will be shown to yield not only area, but also energy reduction due to lower leakage. Finally, the paper demonstrates the use of ultralow-power design techniques in chip synthesis.

A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$ W at 1 MS/s

Abstract: This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115×225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step.

Enhanced low-power high-speed adder for error-tolerant application

Abstract: The tradeoff between power consumption and speed performance has become a major design consideration when devices approach the sub-100 nm regime. It is especially critical when dealing with large data set, whereby the system is degraded in terms of power and speed. If the application can accept some errors, i.e. the application is Error — tolerant (ET), a large reduction in power and an increased in speed can be simultaneously achieved. In this paper, we shall present a novel low-power and high-speed Error-Tolerant Adder Type IV design called ETAIV. The proposed ETAIV is an enhancement of our earlier design, ETAII [1] in terms of speed and accuracy.

A Low-Power Stand-Alone Adaptive Circuit for Harvesting Energy From a Piezoelectric Micropower Generator

Abstract: An adaptive energy-harvesting circuit with low power dissipation is presented and demonstrated, which is useful for efficient ac/dc voltage conversion of a piezoelectric micropower generator. The circuit operates stand-alone, and it extracts the piezoelectric strain energy independent of the load and piezoelectric parameters without using any external sensor. The circuit consists of a voltage-doubler rectifier, a step-down switching converter, and an analog controller operating with a single supply voltage in the range of 2.5-15 V. The controller uses the piezoelectric voltage as a feedback and regulates the rectified voltage to adaptively improve the extracted power. The nonscalable power dissipation of the controller unit is less than 0.05 mW, and the efficiency of the circuit is about 60% for output power levels above 0.5 mW. Experimental verifications of the circuit show the following: 1) the circuit notably increases the extracted power from a piezoelectric element compared to a simple full-bridge diode rectifier without control circuitry, and 2) the efficiency of the circuit is dominantly determined by its switching converter. The simplicity of the circuit facilitates the development of efficient piezoelectric energy harvesters for low-power applications such as wireless sensors and portable devices.

Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing

Abstract: As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations, traditional MOSFET scaling theory prescribes reducing supply and threshold voltages in proportion to device dimensions, a practice that induces an exponential increase in subthreshold leakage. As a result, leakage power has become comparable to dynamic power in current-generation processes, and will soon exceed it in magnitude if voltages are scaled down any further. Beyond this inflection point, multicore processors will not be able to afford keeping more than a small fraction of all cores active at any given moment. Multicore scaling will soon hit a power wall. This paper presents resistive computation, a new technique that aims at avoiding the power wall by migrating most of the functionality of a modern microprocessor from CMOS to spin-torque transfer magnetoresistive RAM (STT-MRAM)---a CMOS-compatible, leakage-resistant, non-volatile resistive memory technology. By implementing much of the on-chip storage and combinational logic using leakage-resistant, scalable RAM blocks and lookup tables, and by carefully re-architecting the pipeline, an STT-MRAM based implementation of an eight-core Sun Niagara-like CMT processor reduces chip-wide power dissipation by 1.7× and leakage power by 2.1× at the 32nm technology node, while maintaining 93% of the system throughput of a CMOS-based design.

An ultra-small, low-power all-optical flip-flop memory on a silicon chip

Abstract: A 7.5pm-diameter InP microdisk laser, integrated on an SOI waveguide is demonstrated as all-optical flip-flop working in continuous-wave regime with an electrical power consumption of several mW, and allowing switching in 60ps with pulses of 1.8fJ.

A Sub- $\mu$ W Embedded CMOS Temperature Sensor for RFID Food Monitoring Application

Abstract: An ultra-low power embedded CMOS temperature sensor based on serially connected subthreshold MOS operation is implemented in a 0.18 μm CMOS process for passive RFID food monitoring applications. Employing serially connected subthreshold MOS as sensing element enables reduced minimum supply voltage for further power reduction, which is of utmost importance in passive RFID applications. Both proportional-to-absolute-temperature (PTAT) and complimentary-to-absolute-temperature (CTAT) signals can be obtained through proper transistor sizing. With the sensor core working under 0.5 V and digital interfacing under 1 V, the sensor dissipates a measured total power of 119 nW at 333 samples/s and achieves an inaccuracy of + 1/-0.8°C from - 10°C to 30°C after calibration. The sensor is embedded inside the fabricated passive UHF RFID tag. Measurement of the sensor performance at the system level is also carried out, illustrating proper sensing operation for passive RFID applications.

An Insight into the Switching Process of Power MOSFETs: An Improved Analytical Losses Model

Abstract: The piecewise linear model has traditionally been used to calculate switching losses in switching mode power supplies due to its simplicity and good performance. However, the use of the latest low voltage power MOSFET generations and the continuously increasing range of switching frequencies have made it necessary to review this model to account for the parasitic inductances that it does not include. This paper presents a complete analytical switching loss model for power MOSFETs in low voltage switching converters that includes the most relevant parasitic elements. It clarifies the switching process, providing information about how these parasitics, especially the inductances, determine switching losses and hence the final converter efficiency. The analysis presented in this paper yields two different types of possible switching situations: capacitance-limited switching and inductance-limited switching. This paper shows that, while the piecewise linear model may be applied in the former, the proposed model is more accurate for the latter. Carefully-obtained experimental results, described in detail, support the analytical results presented.

A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor

Abstract: This paper presents a system-on-chip passive RFID tag with an embedded temperature sensor for the EPC Gen-2 protocol in the 900-MHz UHF frequency band. A dual-path clock generator is proposed to support both applications with either very accurate link frequency or very low power consumption. On-chip temperature sensing is accomplished with a time-readout scheme to reduce the power consumption. Moreover, a gain-compensation technique is proposed to reduce the temperature sensing error due to process variations by using the same bandgap reference of the tag to generate bias currents for both the current-to-digital converter and the clock generator of the sensor. Also integrated is a 128-bit one-time-programmable (OTP) memory array based on gate-oxide antifuse without extra mask steps. Fabricated in a standard 0.18- μm CMOS process with analog options, the 1.1-mm2 tag chip is bonded onto an antenna using flip-chip technology to realize a complete tag inlay, which is successfully demonstrated and evaluated in real-time wireless communications with commercial RFID readers. The tag inlay achieves a sensitivity of -6 dBm and a sensing inaccuracy of ±0.8° C (3 σ inaccuracy) over operating temperature range from -20°C to 30°C with one-point calibration.

A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 $\mu{\hbox {m}}$ CMOS Technology

Abstract: A 12-bit Vernier ring time-to-digital converter (TDC) with time resolution of 8 ps for digital-phase-locked-loops (DPLL) is presented. This novel Vernier ring TDC places the Vernier delay cells and arbiters in a ring format and reuses them for the measurement of the input time interval. The proposed TDC thus achieves large detectable range, fine time resolution, small die size and low power consumption simultaneously. A pre-logic unit is developed to measure both positive and negative phase errors for DPLL applications. The TDC achieves a large detectable range of 12 bits with core area of 0.75 × 0.35 mm2 in a 0.13 μm CMOS technology. The total power consumption for the entire TDC chip is only 7.5 mW with a 1.5 V power supply, while operating at a clock frequency of 15 MSPS.

On the Possibility of Obtaining MOSFET-Like Performance and Sub-60-mV/dec Swing in 1-D Broken-Gap Tunnel Transistors

Abstract: Tunneling field-effect transistors (TFETs) have gained a great deal of interest recently due to their potential to reduce power dissipation in integrated circuits. One major challenge for TFETs so far has been to achieve high drive currents, which is a prerequisite for high-performance operation. In this paper, we explore the performance potential of a 1-D TFET with a broken-gap heterojunction source injector using dissipative quantum transport simulations based on the nonequilibrium Green's function formalism, as well as the carbon nanotube band structure as the model 1-D material system. We provide detailed insights into broken-gap TFET (BG-TFET) operation and show that it can, indeed, produce less than 60 mV/dec subthreshold swing at room temperature, even in the presence of electron-phonon scattering. The 1-D geometry is recognized to be uniquely favorable due to its superior electrostatic control, reduced carrier thermalization rate, and beneficial quantum confinement effects that reduce the off-state leakage below the thermionic limit. Because of higher source injection compared to staggered-gap and homojunction geometries, BG-TFET delivers superior performance that is comparable to MOSFET's. BG-TFET even exceeds the MOSFET performance at lower supply voltages (VDD), showing promise for low-power/high-performance applications.

A Subthreshold to Above-Threshold Level Shifter Comprising a Wilson Current Mirror

Abstract: In this brief, we propose a novel level shifter circuit that is capable of converting subthreshold to above-threshold signal levels. In contrast to other existing implementations, it does not require a static current flow and can therefore offer considerable static power savings. The circuit has been optimized and simulated in a 90-nm process technology. It operates correctly across process corners for supply voltages from 100 mV to 1 V on the low-voltage side. At the target design voltage of 200 mV, the level shifter has a propagation delay of 18.4 ns and a static power dissipation of 6.6 nW. For a 1-MHz input signal, the total energy per transition is 93.9 fJ. Simulation results are compared to an existing subthreshold to above-threshold level shifter implementation from the paper of Chen et al.

A Fully Integrated RF-Powered Contact Lens With a Single Element Display

Abstract: We present progress toward a wirelessly-powered active contact lens comprised of a transparent polymer substrate, loop antenna, power harvesting IC, and micro-LED. The fully integrated radio power harvesting and power management system was fabricated in a 0.13 μm CMOS process with a total die area of 0.2 mm2. It utilizes a small on-chip capacitor for energy storage to light up a micro-LED pixel. We have demonstrated wireless power transfer at 10 cm distance using the custom IC and on-lens antenna.

Low-power high-speed multiplier for error-tolerant application

Abstract: In this paper, a new design concept that engaged accuracy as a design parameter is proposed. By introducing accuracy as a design parameter, the bottleneck of conventional digital IC design techniques can be breakthrough to improve on the performances of power consumption and speed. The aim is to fulfill the need for high performance basic sequential elements with low-power dissipation which is steadily growing.

Technologies for Ultradynamic Voltage Scaling

Abstract: Energy efficiency of electronic circuits is a critical concern in a wide range of applications from mobile multi-media to biomedical monitoring. An added challenge is that many of these applications have dynamic workloads. To reduce the energy consumption under these variable computation requirements, the underlying circuits must function efficiently over a wide range of supply voltages. This paper presents voltage-scalable circuits such as logic cells, SRAMs, ADCs, and dc-dc converters. Using these circuits as building blocks, two different applications are highlighted. First, we describe an H.264/AVC video decoder that efficiently scales between QCIF and 1080p resolutions, using a supply voltage varying from 0.5 V to 0.85 V. Second, we describe a 0.3 V 16-bit micro-controller with on-chip SRAM, where the supply voltage is generated efficiently by an integrated dc-dc converter.

Thermal energy harvesting for WSNs

Abstract: Because of the recent developments in both wireless technologies and low power electronics, wireless devices consume less and less power and are promising the possibility to operate continuously by using energy harvesting technologies. The interest in Wireless Sensor Networks (WSNs), powered by environment energy harvesters, has been increasing over the last decade, especially those using thermal energy harvesting. In this paper, a low temperature thermal energy harvesting system, which can harvest heat energy from a temperature gradient and convert it into electrical energy, which can be used to power wireless electronics, is proposed. A prototype based on three subsystems is presented to extract heat energy from a radiator and use it to power ZigBee electronics. High efficiency and a long system lifetime are two of the main advantages of this design. The experimental results show that a maximum of 150mW power can be harvested by the prototype and the system can continue to operate normally when the harvesting voltage is as low as 0.45V. Theoretical calculations suggest that by placing the two AA batteries by proposed thermal energy harvesting system, a ZigBee Wireless Radiator Valve can operate for more than eight years.

Flexible Circuits and Architectures for Ultralow Power

Abstract: Subthreshold digital circuits minimize energy per operation and are thus ideal for ultralow-power (ULP) applications with low performance requirements. However, a large range of ULP applications continue to face performance constraints at certain times that exceed the capabilities of subthreshold operation. In this paper, we give two different examples to show that designing flexibility into ULP systems across the architecture and circuit levels can meet both the ULP requirements and the performance demands. Specifically, we first present a method that expands on ultradynamic voltage scaling (UDVS) to combine multiple supply voltages with component level power switches to provide more efficient operation at any energy-delay point and low overhead switching between points. This system supports operation across the space from maximum performance, when necessary, to minimum energy, when possible. It thus combines the benefits of single-V DD, multi-V DD, and dynamic voltage scaling (DVS) while improving on them all. Second, we propose that reconfigurable subthreshold circuits can increase applicability for ULP embedded systems. Since ULP devices conventionally require custom circuit design but the manufacturing volume for many ULP applications is low, a subthreshold field programmable gate array (FPGA) offers a cost-effective custom solution with hardware flexibility that makes it applicable across a wide range of applications. We describe the design of a subthreshold FPGA to support ULP operation and identify key challenges to this effort.

A 1V 17.9dBm 60GHz power amplifier in standard 65nm CMOS

Abstract: For point-to-point multi-Gb/s applications in mobile devices with single antennas, low-cost, highly integrated solutions are preferred, and CMOS technology is a candidate for mm-Wave SoC products. To provide users with nearly omni-directional links, the TX power requirement could be considerably high. Assuming a receiver with 7dB NF, and 1dBi antennas at both ends of the link, the required power to transmit a 60GHz signal over 1m distance is 10dBm. A power amplifier (PA) that is capable of delivering 13dBm OP 1dB for a 3Gb/s QPSK signal is thus needed if 3dB power back-off is added. This paper presents a CMOS PA meeting these requirements.

A 60-GHz OOK Receiver With an On-Chip Antenna in 90 nm CMOS

Abstract: A low power 60-GHz on-off-keying (OOK) receiver has been implemented in a commercial 90 nm RF CMOS process. By employing a novel on-chip antenna together with architecture optimization, the receiver achieves a sensitivity of -47 dBm at a bit-error rate (BER) of less than 10-3. Using a commercial transmitter with transmit power of 1.5 dBm, a transmission distance of 5 cm can be achieved at 1.2 Gbps data rate. In this design, the on-chip antenna minimizes the packaging loss, while energy detection at RF allows architecture simplification. Both techniques contribute to the receiver's low power consumption of 51 mW, excluding test buffers. This leads to a bit energy efficiency of 28 pj/bit at 1.8 Gbps. The total die area is 3.8 mm2 with the on-chip antenna occupying almost half of it.

A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology

Abstract: A 21-Gb/s backplane transceiver has been presented. The transmitter incorporates half-rate topology with purely digital blocks to substantially reduce power consumption. The receiver employs analog and decision-feedback equalizers in a full-rate structure to avoid complicated structure. The one-tap decision-feedback equalizer merges the summer and the slicer into the flipflop, shortening the feedback path and speeding up the operation considerably. Fabricated in 65-nm CMOS, the transceiver (excluding clock generating PLL and CDR circuits) delivers 21-Gb/s data (231- 1 PRBS) over 40-cm FR4 channel while consuming 87 mW from a 1.2-V supply.

A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process

Abstract: A 12.3-mW 12.5-Gb/s complete transceiver based on the 65-nm standard digital CMOS process was developed. The chip includes a clock-and-data-recovery (CDR) device, a multiplexer/demultiplexer (MUX/DEMUX), and a global clock-distribution network. To reduce power consumption, a low-swing voltage-mode driver with pulse-current boosting and an LC resonant-clock distribution with distributed on-chip inductors are used in the transmitter, while a symbol-rate phase detector (SPD) using a three-stage sense amplifier and phase-rotating phase-locked loop (PLL) with variable delay are used in the receiver. The transceiver operates at a bit error rate (BER) of 10-12 or less through a 20-cm test board with total attenuation of -12.1 dB while consuming power of 0.98 mW/(Gb/s) per transceiver.

Device and Circuit Co-Design Robustness Studies in the Subthreshold Logic for Ultralow-Power Applications for 32 nm CMOS

Abstract: Digital circuits operating in a subthreshold region have gained wide interest due to their suitability for applications requiring ultralow power consumption with low-to-medium performance criteria. It has been demonstrated that by appropriately optimizing the devices for subthreshold logic, total energy consumption can be reduced significantly. One of the major concerns for subthreshold circuit design is increased sensitivity to process, voltage, and temperature (PVT) variations. In this paper, we critically study the effect of variations of different device and environmental parameters like gate oxide thickness, channel length, threshold voltage, supply voltage, temperature, and reverse body bias on subthreshold circuit performance for 32 nm bulk CMOS. From the study, we conclude that alternative devices like double-gate silicon-on-insulator (DGSOI) are better candidates in terms of performance, robustness and PVT insensitivity as compared to bulk circuits for both static CMOS and pseudo NMOS logic families. We also study the performance and robustness comparisons of bulk CMOS and DGSOI subthreshold basic logic gates with and without parameter variations and we observe 60-70% improvement in power delay product and roughly 50% better tolerance to PVT variations of DGSOI subthreshold logic circuits compared to bulk CMOS subthreshold circuits at the 32 nm node.

Dynamic and Leakage Energy Minimization With Soft Real-Time Loop Scheduling and Voltage Assignment

Abstract: With the shrinking of technology feature sizes, the share of leakage in total power consumption of digital systems continues to grow. Traditional dynamic voltage scaling (DVS) fails to accurately address the impact of scaling on system power consumption as the leakage power increases exponentially. The combination of DVS and adaptive body biasing (ABB) is an effective technique to jointly optimize dynamic and leakage energy dissipation. In this paper, we propose an optimal soft real-time loop scheduling and voltage assignment algorithm, loop scheduling and voltage assignment to minimize energy, to minimize both dynamic and leakage energy via DVS and ABB. Voltage transition overhead has been considered in our approach. We conduct simulations on a set of digital signal processor benchmarks based on the power model of 70 nm technology. The simulation results show that our approach achieves significant energy saving compared to that of the integer linear programming approach.

Area- and Power-Efficient Monolithic Buck Converters With Pseudo-Type III Compensation

Abstract: Monolithic PWM voltage-mode buck converters with a novel Pseudo-Type III (PT3) compensation are presented. The proposed compensation maintains the fast load transient response of the conventional Type III compensator; while the Type III compensator response is synthesized by adding a high-gain low-frequency path (via error amplifier) with a moderate-gain high-frequency path (via bandpass filter) at the inputs of PWM comparator. As such, smaller passive components and low-power active circuits can be used to generate two zeros required in a Type III compensator. Constant Gm/C biasing technique can also be adopted by PT3 to reduce the process variation of passive components, which is not possible in a conventional Type III design. Two prototype chips are fabricated in a 0.35-μm CMOS process with constant Gm/C biasing technique being applied to one of the designs. Measurement result shows that converter output is settled within 7 μs for a load current step of 500 mA. Peak efficiency of 97% is obtained at 360 mW output power, and high efficiency of 86% is measured for output power as low as 60 mW. The area and power consumption of proposed compensator is reduced by > 75 % in both designs, compared to an equivalent conventional Type III compensator.