Showing papers on "Low-power electronics published in 2011"
TL;DR: A novel energy-efficient single flux quantum logic family, ERSFQ/eSFQ, is presented and different superconductor digital technology approaches and logic families addressing this problem are compared.
Abstract: Figures of merit connecting processing capabilities with power dissipated (OpS/Watt, Joule/bit, etc.) are becoming dominant factors in choosing technologies for implementing the next generation of computing and communication network systems. Superconductivity is viewed as a technology capable of achieving higher energy efficiencies than other technologies. Static power dissipation of standard RSFQ logic, associated with dc bias resistors, is responsible for most of the circuit power dissipation. In this paper, we review and compare different superconductor digital technology approaches and logic families addressing this problem. We present a novel energy-efficient single flux quantum logic family, ERSFQ/eSFQ. We also discuss energy-efficient approaches for output data interface and overall cryosystem design.
469 citations
TL;DR: A multi-core processor that integrates 48 cores, 4 DDR3 memory channels, and a voltage regulator controller in a 64 2D-mesh network-on-chip architecture that uses message passing while exploiting 384 KB of on-die shared memory for fine grain power management.
Abstract: This paper describes a multi-core processor that integrates 48 cores, 4 DDR3 memory channels, and a voltage regulator controller in a 64 2D-mesh network-on-chip architecture. Located at each mesh node is a five-port virtual cut-through packet-switched router shared between two IA-32 cores. Core-to-core communication uses message passing while exploiting 384 KB of on-die shared memory. Fine grain power management takes advantage of 8 voltage and 28 frequency islands to allow independent DVFS of cores and mesh. At the nominal 1.1 V supply, the cores operate at 1 GHz while the 2D-mesh operates at 2 GHz. As performance and voltage scales, the processor dissipates between 25 W and 125 W. The processor is implemented in 45 nm Hi-K CMOS and has 1.3 billion transistors.
415 citations
TL;DR: Energy-efficient RSFQ (ERSFQ) as discussed by the authors is a resistor-free approach to dc biasing, which does not dissipate energy in the static (non-active) mode and dissipates orders of magnitude less power while operating.
Abstract: We present a novel, resistor-free approach to dc biasing of RSFQ circuits, known as Energy-efficient RSFQ (ERSFQ). This biasing scheme does not dissipate energy in the static (non-active) mode, and dissipates orders of magnitude less power than traditional RSFQ while operating. Using this approach, we have designed, fabricated and successfully tested at low and high speed a D flip-flop with complementary outputs and several static frequency dividers. We present the method, demonstrate experimental results, and discuss future implementations of ERSFQ.
285 citations
TL;DR: In this article, the authors simulate and experimentally investigate the source-pocket tunnel field effect transistor (TFET), which is based on the principle of band-to-band tunneling.
Abstract: Low operating power is an important concern for sub-45-nm CMOS integrated circuits. Scaling of devices to below 45 nm leads to an increase in active power dissipation (CV2.f) and subthreshold power (IOFF.VDD)Hence, new device innovations are being explored to address these problems. In this paper, we simulate and experimentally investigate the source-pocket tunnel field-effect transistor (TFET), which is based on the principle of band-to-band tunneling, p-i-n and source-pocket TFETs are fabricated with different pocket conditions to observe the effect of the source-side pocket on device performance. Different annealing schemes (spike and conventional rapid thermal annealing) are used to study the effect of annealing conditions on TFET performance. The source-pocket TFET shows a higher ION (~10 times) and steeper subthreshold swing as compared to a p-i-n TFET. The ambipolar conduction is also reduced by using a low-doped drain extension. Low-temperature measurements of the source-pocket TFET were performed, and the subthreshold swing of the source-pocket TFET shows very little temperature dependence, which confirms the dominant source injection mechanism to be band-to-band tunneling.
218 citations
TL;DR: It will be shown that, in spite of what commonly is assumed, although the total capacitance and the power consumption of those architectures employing attenuating capacitors seem to be smaller than conventional binary-weighted structures, the linearity requirements impose much larger unit capacitance to the structure such that the entire power consumption is larger.
Abstract: Successive-approximation analog-to-digital converters (SA-ADCs) are widely used in ultra-low-power applications. In this paper, the power consumption and the linearity of capacitive-array digital-to-analog converters (DACs) employed in SA-ADCs are analyzed. Specifically, closed-form formulas for the power consumption as well as the standard deviation of INL and DNL for three commonly-used radix-2 architectures including the effect of parasitic capacitances are presented and the structures are compared. The proposed analysis can be employed in choosing the best architecture and optimizing it in both hand calculations and computer-aided-design tools. Measurement results of previously published works as well as simulation results of a 10-bit 10 kS/s SA-ADC confirm the accuracy of the proposed equations. It will be shown that, in spite of what commonly is assumed, although the total capacitance and the power consumption of those architectures employing attenuating capacitors seem to be smaller than conventional binary-weighted structures, the linearity requirements impose much larger unit capacitance to the structure such that the entire power consumption is larger.
203 citations
TL;DR: In this article, the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage (VT) platform for digital circuits compatible with bulk complementary metal-oxide-semiconductor (CMOS) was analyzed.
Abstract: This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage VT platform for digital circuits compatible with bulk complementary metal-oxide-semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thickness, back plane doping type, and back biasing, were investigated in order to achieve a technology platform that offers at least three distinct VT options (high-VT, standard- VT, and low-VT ). The multi-VT technology platform highlighted in this paper was developed with standard CMOS circuit design constraints in mind; its compatibility in terms of design and power management techniques, as well as its superior performance with regard to bulk CMOS, are described. Finally, it is shown that a multi-VT technology platform based on two gate materials offers additional advantages as a competitive solution. The proposed approach enables excellent channel electrostatic control and low VT variability of the FDSOI process. The viability of the proposed concept has been studied through technology computer-aided design simulations and demonstrated through experimental measurements on 30-nm gate length devices.
189 citations
TL;DR: An embedded processor platform chip using an ARM Cortex-M3 suitable for mapping medical applications requiring microwatt power consumption is presented and the first sub-microwatt per channel electroencephalograph (EEG) seizure detection is demonstrated.
Abstract: Battery life specifications drive the power consumption requirements of integrated circuits in implantable, wearable, and portable medical devices. In this paper, we present an embedded processor platform chip using an ARM Cortex-M3 suitable for mapping medical applications requiring microwatt power consumption. Ultra-low-power operation is achieved via 0.5-1.0 V operation, a 28 fW/bit fully differential subthreshold 6T SRAM, a 90%-efficient DC-DC converter, and a 100-nJ fast Fourier transform (FFT) accelerator to reduce processor workload. Using a combination of novel circuit design, system architecture, and SoC implementation, the first sub-microwatt per channel electroencephalograph (EEG) seizure detection is demonstrated.
160 citations
07 Apr 2011
TL;DR: The effective on-to-off ratio can be considerably improved by the use of Schmitt Trigger structures, which effectively reduce the leakage from the gate output node and thereby stabilize the output level.
Abstract: Supply voltage reduction beyond the minimum energy per operation point is advantageous for supply voltage constrained applications, but is limited by the degradation of on-to-off current ratios with decreasing supply. In this work, we show that the effective on-to-off ratio can be considerably improved by the use of Schmitt Trigger structures, which effectively reduce the leakage from the gate output node and thereby stabilize the output level. A method for applying this concept to general logic is presented. Design rules concerning transistor sizing, gate selection and layout necessary to further minimize the required supply voltage are outlined and applied to the design of a chip implementing 8 × 8 bit multipliers as test structures. The only custom design step is the creation of the Schmitt Trigger standard-cell library, otherwise a regular digital tool chain is used. The multipliers exhibit full functionality down to supply voltages of 84 mV-62 mV, depending on the area overhead invested. No process or post-silicon tuning like body biasing is used. At the minimum possible supply voltage of 62 mV, a power consumption of 17.9 nW at an operation frequency of 5.2 kHz is measured for an 8 × 8 bit multiplier.
154 citations
TL;DR: An ultra-low-power 32-channel neural-recording integrated circuit (chip) in a 0.18 μ m CMOS technology that achieves an ENOB of 7.65 and a net efficiency of 77 fJ/State, making it one of the most energy-efficient designs for neural recording applications.
Abstract: We report the design of an ultra-low-power 32-channel neural-recording integrated circuit (chip) in a 0.18 μ m CMOS technology. The chip consists of eight neural recording modules where each module contains four neural amplifiers, an analog multiplexer, an A/D converter, and a serial programming interface. Each amplifier can be programmed to record either spikes or LFPs with a programmable gain from 49-66 dB. To minimize the total power consumption, an adaptive-biasing scheme is utilized to adjust each amplifier's input-referred noise to suit the background noise at the recording site. The amplifier's input-referred noise can be adjusted from 11.2 μVrms (total power of 5.4 μW) down to 5.4 μVrms (total power of 20 μW) in the spike-recording setting. The ADC in each recording module digitizes the a.c. signal input to each amplifier at 8-bit precision with a sampling rate of 31.25 kS/s per channel, with an average power consumption of 483 nW per channel, and, because of a.c. coupling, allows d.c. operation over a wide dynamic range. It achieves an ENOB of 7.65, resulting in a net efficiency of 77 fJ/State, making it one of the most energy-efficient designs for neural recording applications. The presented chip was successfully tested in an in vivo wireless recording experiment from a behaving primate with an average power dissipation per channel of 10.1 μ W. The neural amplifier and the ADC occupy areas of 0.03 mm2 and 0.02 mm2 respectively, making our design simultaneously area efficient and power efficient, thus enabling scaling to high channel-count systems.
150 citations
TL;DR: This paper describes a micropower low-noise neural front-end circuit capable of recording epileptic fast ripples (FR) and is the first to achieve the FR-recording functionality.
Abstract: This paper describes a micropower low-noise neural front-end circuit capable of recording epileptic fast ripples (FR) The front-end circuit consisting of a preamplifier followed by a 6th-order bandpass filter is designed for signal sensing in a future epileptic deep brain stimulator A current-splitting technique is combined with an output-branch current scaling technique in a folded-cascode amplifier structure to improve the noise and power tradeoff in the preamplifier In measurements, the preamplifier exhibits 394 dB DC gain, 036 Hz to 13 kHz of -3 dB bandwidth, and 307 μVrms total input-referred noise while consuming 24 μW from a 28 V power supply provided by an on-chip regulator circuit A noise efficiency factor (NEF) of 309 is achieved with minimal power consumption and is one of the lowest published to date The 6th-order follow-the-leader feedback elliptic bandpass filter passes FR signals and provides -110 dB/decade attenuation to out-of-band frequency components In measurements, the entire front-end circuit achieves a mid-band gain of 385 dB, a bandwidth from 250 to 486 Hz, and a total input-referred noise of 248 μVrms while consuming 45 μW from the 28 V power supply The front-end NEF achieved is 76 To the authors' knowledge, the proposed epileptic seizure- detection system is the first to achieve the FR-recording functionality The chip is fabricated in a standard 06 μm CMOS process Die size is 045 mm2
138 citations
TL;DR: Variation-aware DVFS with optimal core mapping is shown to improve energy efficiency 6%-35% across a range of compute/communication activity workloads and a new dynamic thread hopping scheme boosts performance by 5%-10% or energy efficiency by 20%-60%.
Abstract: In this paper, we present measured within-die core-to-core Fmax and leakage variation data for an 80-core processor in 65 nm CMOS and 1) populate a parameterized energy/performance model to determine the most energy-efficient operating point for a workload; 2) examine impacts of per-core clock and power gating on optimal dynamic voltage-frequency-core scaling (DVFCS) operating points; and 3) compare improvements in energy efficiency achievable by variation-aware DVFCS and core mapping on Single-Voltage/Multiple-Frequency (SVMF), Multiple-Voltage/Single-Frequency (MVSF) and Multiple-Voltage/Multiple-Frequency (MVMF) designs. Variation-aware DVFS with optimal core mapping is shown to improve energy efficiency 6%-35% across a range of compute/communication activity workloads. A new dynamic thread hopping scheme boosts performance by 5%-10% or energy efficiency by 20%-60%.
TL;DR: A novel P-P-N-based 10T SRAM cell, in which the latch is formed essentially by a cross-coupled P-p-N inverter pair, which is especially suitable for an SRAM macro with long bitlines - a property often desirable in order to achieve high density.
Abstract: SRAM has been under its renovation stage recently, aiming to withstand the ever-increasing process variation as well as to support ultra-low-power applications using even subthreshold supply voltages. We present in this paper a novel P-P-N-based 10T SRAM cell, in which the latch is formed essentially by a cross-coupled P-P-N inverter pair. This type of cell can operate at a voltage as low as 285 mV while still demonstrating high resilience to process variation. Its noise margin has been elevated in not only the hold state, but also the read operations. As compared to previous 10T SRAM cells, our cell excels in particular in two aspects: 1) ultra-low cell leakage, and 2) high immunity to the data-dependent bitline leakage. The second merit makes it especially suitable for an SRAM macro with long bitlines - a property often desirable in order to achieve high density. We have fabricated and validated its performance through a 16 Kb SRAM test chip using the UMC 90 nm process technology.
TL;DR: A 65-nm digitally modulated polar transmitter incorporates a fully integrated, efficient 2.4-GHz switching Inverse Class-D power amplifier and simple static predistortion helps the transmitter meet EVM and mask requirements of 802.11g 54-Mb/s WLAN data.
Abstract: A 65-nm digitally modulated polar transmitter incorporates a fully integrated, efficient 2.4-GHz switching Inverse Class-D power amplifier. Low-power digital filtering on the amplitude path helps remove spectral images for coexistence. The transmitter integrates the complete LO distribution network and digital drivers. Operating from a 1-V supply, the PA has 21.8-dBm peak output power with 44% efficiency. Simple static predistortion helps the transmitter meet EVM and mask requirements of 802.11g 54-Mb/s WLAN data with 18% average efficiency.
TL;DR: This work presents a method for creating a trade-off curve that can be used to estimate the maximum floating-point performance given a set of area and power constraints, and finds that in a 90 nm CMOS technology at 1 W/mm2, one can achieve a performance of 27 GFlops/ mm2 single precision, and 7.5 GFlop/mm double precision.
Abstract: Energy-efficient computation is critical if we are going to continue to scale performance in power-limited systems. For floating-point applications that have large amounts of data parallelism, one should optimize the throughput/mm2 given a power density constraint. We present a method for creating a trade-off curve that can be used to estimate the maximum floating-point performance given a set of area and power constraints. Looking at FP multiply-add units and ignoring register and memory overheads, we find that in a 90 nm CMOS technology at 1 W/mm2, one can achieve a performance of 27 GFlops/mm2 single precision, and 7.5 GFlops/mm double precision. Adding register file overheads reduces the throughput by less than 50 percent if the compute intensity is high. Since the energy of the basic gates is no longer scaling rapidly, to maintain constant power density with scaling requires moving the overall FP architecture to a lower energy/performance point. A 1 W/mm2 design at 90 nm is a "high-energy" design, so scaling it to a lower energy design in 45 nm still yields a 7× performance gain, while a more balanced 0.1 W/mm2 design only speeds up by 3.5× when scaled to 45 nm. Performance scaling below 45 nm rapidly decreases, with a projected improvement of only ~3x for both power densities when scaling to a 22 nm technology.
TL;DR: It is shown that it is possible to achieve 2-D-like, or even better, power quality by increasing C4 granularity and by selecting suitable TSV size and spacing and this is the first detailed architectural-level analysis for 3-D power delivery.
Abstract: 3-D integrated circuits promise high bandwidth, low latency, low device power, and a small form factor. Increased device density and asymmetrical packaging, however, renders the design of 3-D power delivery a challenge. We investigate in this paper various methods to improve 3-D power delivery. We analyze the impact of through-silicon via (TSV) size and spacing, of controlled collapse chip connection (C4) spacing, and of dedicated power delivery TSVs. In addition to considering typical cylindrical or square metal-filled TSVs (core TSVs), we also investigate using coaxial TSVs for power delivery resulting in reduced routing blockages and added coupling capacitance. Our 3-D evaluation system is composed of a quad-core chip multiprocessor, a memory die, and an accelerator engine, and it is evaluated using representative SPEC benchmark traces. This is the first detailed architectural-level analysis for 3-D power delivery. Our findings provide clear guidelines for 3-D power delivery design. More importantly, we show that it is possible to achieve 2-D-like, or even better, power quality by increasing C4 granularity and by selecting suitable TSV size and spacing.
07 Apr 2011
TL;DR: This work designs and test a D-flip-flop, known as adaptive-coupling flip- flop (ACFF), which has a reduced transistor count compared to other low-power flip-flops, and 2 fewer transistors than the mainstream transmission-gate flip-Flop (TGFF).
Abstract: Flip-flops (FF) typically consume more than 50% of random-logic power in an SoC chip, due to their redundant transition of internal nodes, when the input and the output are in the same state. Several low-power techniques have been proposed [1–5], but all of them incur transistor-count penalties, leading to an increase in size, which is too costly since flip-flops typically account for 50% of random-logic area. In this work, we design and test a D-flip-flop, known as adaptive-coupling flip-flop (ACFF), which has a reduced transistor count compared to other low-power flip-flops, and 2 fewer transistors than the mainstream transmission-gate flip-flop (TGFF). ACFF features a single-phase clocking structure, with no local clock buffer and no precharging stage, enabling it to be more energy efficient than TGFF, where up to 77% energy saving is achieved at 0% data activity. ACFF also has an adaptive-coupling configuration, which weakens state-retention coupling during a transition, allowing it to be tolerant to process variations. Test chips are fabricated in a 40nm CMOS technology for 1.1V application, and 500k ACFFs are tested over all chips in 5 skew wafers. All tested ACFFs are fully functional down to 0.75V supply voltage, with spreads of timing parameters comparable to TGFF. We also demonstrate a P&R test by employing ACFF to a wireless LAN chip, and the results indicate chip power is reduced by as much as 24%.
TL;DR: A power-efficient frequency compensation topology, Impedance Adapting Compensation (IAC), is presented, which has a normal Miller capacitor still needed to provide an internal negative feedback loop and a serial RC impedance as a load to the intermediate stage, improving performance parameters such as stability, gain-bandwidth product and power dissipation.
Abstract: A power-efficient frequency compensation topology, Impedance Adapting Compensation (IAC), is presented in this paper. This IAC topology has, on one hand, a normal Miller capacitor, which is still needed to provide an internal negative feedback loop, and on the other hand, a serial RC impedance as a load to the intermediate stage, improving performance parameters such as stability, gain-bandwidth product and power dissipation. A three-stage IAC amplifier was implemented and fabricated in a 0.35 μm CMOS technology. Experiment results show that the implemented IAC amplifier, driving a 150 pF load capacitance, achieved a gain-bandwidth product (GBW) of 4.4 MHz while dissipating only 30 μW power with a 1.5 V supply.
TL;DR: The proposed preamble detection scheme can significantly reduce false wake ups due to other wireless devices in a WBAN and significantly reduces the overall power consumption for packet reception and decoding.
Abstract: We designed, implemented, tested and measured an ultra low power Wake Up Receiver (WUR), intended for use in Wireless Body Area Networks (WBAN). Gaussian On-Off Keying (GOOK) and Pulse Width Modulation (PWM) are used to modulate and encode, respectively, the preamble signal. The receiver incorporates a decoder to enable Serial Peripheral Interface (SPI). WUR was also comprehensively tested for power consumption and robustness to RF interference from wireless devices commonly found in the vicinity of persons utilising WBAN technology. Our results and comparative evaluation demonstrate that the achieved listening power of 270nW for the Wake Up Receiver is significantly lower power consumption than for the other state-of-the-art. The proposed preamble detection scheme can significantly reduce false wake ups due to other wireless devices in a WBAN. Additionally, SPI significantly reduces the overall power consumption for packet reception and decoding.
TL;DR: In this paper, a 90-nm CMOS low-noise amplifier (LNA) for 3-10 GHz ultra-wideband (UWB) applications is presented, which adopts a single-ended dual-stage solution.
Abstract: A 90-nm CMOS low-noise amplifier (LNA) for 3-10-GHz ultra-wideband (UWB) applications is presented. The circuit adopts a single-ended dual-stage solution. The first stage is based on a current-reuse topology and performs UWB (3-10 GHz) input matching. The second stage is a cascode amplifier with resonant load to enhance gain and reverse isolation. Thanks to both the circuit solution and design approach, the LNA provides input matching, low noise, flat gain, and small group-delay variation in the UWB frequency range at minimum power consumption. The design is also conceived to cope with application issues such as low-cost off-chip interfaces and electrostatic discharge robustness. Measurements exhibit a 12.5-dB power gain in a 7.6-GHz 3-dB bandwidth, a minimum noise figure of 3 dB, a reverse isolation better than 45 dB up to 10.6 GHz, and a record small group-delay variation of ±12 ps. The LNA draws 6 mA from a 1.2-V power supply.
TL;DR: In this paper, a sensitivity-based energy-delay optimization approach is developed in order to establish simple relay design guidelines, and it is found that, at the optimal design point, every 2 X energy increase can be traded off for a ~1.5x reduction in relay delay.
Abstract: Microelectromechanical relays have recently been proposed for ultra-low-power digital logic because their nearly ideal switching behavior can potentially enable reductions in supply voltage (Vdd) and, hence, energy per operation beyond the limits of MOSFETs. Using a calibrated analytical model, a sensitivity-based energy-delay optimization approach is developed in order to establish simple relay design guidelines. It is found that, at the optimal design point, every 2 X energy increase can be traded off for a ~1.5x reduction in relay delay. A contact-gap-to-actuation-gap thickness ratio of 0.7-0.8 is shown to result in the most energy-efficient relay operation, implying that pull-in operation is preferred for an energy-efficient relay design. Based on the analytical model and design guidelines, a scaling theory for relays is presented. A scaled relay technology is projected to provide >; 10 X energy savings over an equivalent MOSFET technology, for circuits operating at clock frequencies up to ~100 MHz.
01 Dec 2011
TL;DR: In this article, the authors leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) high-к/metal gate (HKMG) logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.
Abstract: Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH ) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with T inv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.
TL;DR: A novel 9T bitcell is presented, implementing a Supply Feedback concept to internally weaken the pull-up current during write cycles and thus enable low-voltage write operations, achieved without the need for additional peripheral circuits and techniques.
Abstract: Low voltage operation of digital circuits continues to be an attractive option for aggressive power reduction. As standard SRAM bitcells are limited to operation in the strong-inversion regimes due to process variations and local mismatch, the development of specially designed SRAMs for low voltage operation has become popular in recent years. In this paper, we present a novel 9T bitcell, implementing a Supply Feedback concept to internally weaken the pull-up current during write cycles and thus enable low-voltage write operations. As opposed to the majority of existing solutions, this is achieved without the need for additional peripheral circuits and techniques. The proposed bitcell is fully functional under global and local variations at voltages from 250 mV to 1.1 V. In addition, the proposed cell presents a low-leakage state reducing power up to 60%, as compared to an identically supplied 8T bitcell. An 8 kbit SF-SRAM array was implemented and fabricated in a low-power 40 nm process, showing full functionality and ultra-low power.
TL;DR: A multiharvesting system conception focused on low-voltage and low-power applications is presented and validated as a point-of-view system, able to collect and manage energy from different power sources, such as solar light, vibration, and electromagnetic induction.
Abstract: A multiharvesting system conception focused on low-voltage (up to 2.5 V) and low-power applications is presented and validated as a point-of-view system. Using just this application-specified integrated circuit, with a total quiescent power consumption of 160 μW, the harvesting system is able to collect and manage energy from different power sources, such as solar light (indoor environment), vibration (low-voltage piezoelectric generators), and electromagnetic induction (operating with a carrier frequency of 13.56-MHz regulated band). The maximum total power harvested with the addition of the three harvesting sources is around 6.4 mW, for the operating conditions defined by a PZT at 7 m/s2 at 80 Hz, 1500 lx for a laboratory illumination, and 200 mW emitted by a base transmitter at 25-mm distance between coils. A broad and detailed description of all low-power-consumption circuits involved in the multiharvesting system is described, emphasizing their design for low-voltage and low-power applications.
TL;DR: In this article, a design space comprising of I_ON, a drain saturation voltage, and a drain threshold voltage for minimizing the propagation delay of circuits using TFETs is presented. But, as shown in this paper, the delay of the circuit is determined by the rise/fall time rather than by propagation delay.
Abstract: Improving the on-current has been the focus of enhancing the performance of tunnel field-effect transistors (TFETs). In this paper, we show that the increase in I_ON is not sufficient to improve the circuit performance with TFETs. As TFETs show a drain-barrier voltage in their output characteristics below which the drain current drastically reduces, the rise/fall time significantly increases. This reduces the dynamic noise margin and limits the performance achievable from TFETs. We show that, in TFETs, the delay of the circuit is determined by the rise/fall time rather than by the propagation delay. The saturation voltage is much higher compared with that of complementary metal-oxide-semiconductor (CMOS) devices, leading to a lower gain and a lower static noise margin in digital circuits, as well as impeding the performance of latch/regenerative circuits. We present a design space comprising of I_ON, a drain saturation voltage, and a drain threshold voltage for minimizing the propagation delay of circuits using TFETs. Finally, for the same off-current and speed of operation, TFET devices tend to suffer from a higher gate capacitance compared with CMOS devices. If this behavior is not taken into account during the circuit design, these devices (although designed for low-power applications) can dissipate more power at the same speed of operation than CMOS counterparts.
25 Jul 2011
TL;DR: It is shown that the throughput, response time, and power consumption of a high-core-count processor operating at a low clock rate and very low power consumption can perform well when compared to a platform using faster but fewer commodity cores.
Abstract: Scaling data centers to handle task-parallel work-loads requires balancing the cost of hardware, operations, and power. Low-power, low-core-count servers reduce costs in one of these dimensions, but may require additional nodes to provide the required quality of service or increase costs by under-utilizing memory and other resources. We show that the throughput, response time, and power consumption of a high-core-count processor operating at a low clock rate and very low power consumption can perform well when compared to a platform using faster but fewer commodity cores. Specific measurements are made for a key-value store, Memcached, using a variety of systems based on three different processors: the 4-core Intel Xeon L5520, 8-core AMD Opteron 6128 HE, and 64-core Tilera TILEPro64.
14 Mar 2011
TL;DR: A novel hybrid SPM which consists of non-volatile memory (NVM) and SRAM to take advantage of the ultra-low leakage power consumption and high density of NVM as well as the efficient writes of SRAM is proposed.
Abstract: Scratch Pad Memory (SPM), a software-controlled on-chip memory, has been widely adopted in many embedded systems due to its small area and low power consumption. As technology scaling reaches the sub-micron level, leakage energy consumption is surpassing dynamic energy consumption and becoming a critical issue. In this paper, we propose a novel hybrid SPM which consists of non-volatile memory (NVM) and SRAM to take advantage of the ultra-low leakage power consumption and high density of NVM as well as the efficient writes of SRAM. A novel dynamic data allocation algorithm is proposed to make use of the full potential of both NVM and SRAM. According to the experimental results, with the help of the proposed algorithm, the novel hybrid SPM architecture can reduce memory access time by 18.17%, dynamic energy by 24.29%, and leakage power by 37.34% on average compared with a pure SRAM based SPM with the same size area.
TL;DR: A library of static ambipolar carbon nanotube field effect transistor (CNTFET) gates based on generalized NOR-NAND-AOI-OAI primitives, which efficiently implements XOR-based functions are proposed, which results in ambipolar gates with a higher expressive power than conventional complementary metal-oxidesemiconductor (CMOS) libraries.
Abstract: Recently, several emerging technologies have been reported as potential candidates for controllable ambipolar devices. Controllable ambipolarity is a desirable property that enables the on-line configurability of n-type and p-type device polarity. In this paper, we introduce a new design methodology for logic gates based on controllable ambipolar devices, with an emphasis on carbon nanotubes as the candidate technology. Our technique results in ambipolar gates with a higher expressive power than conventional complementary metal-oxidesemiconductor (CMOS) libraries. We propose a library of static ambipolar carbon nanotube field effect transistor (CNTFET) gates based on generalized NOR-NAND-AOI-OAI primitives, which efficiently implements XOR-based functions. Technology mapping of several multi-level logic benchmarks that extensively use the XOR function, including multipliers, adders, and linear circuits, with ambipolar CNTFET logic gates indicates that on average, it is possible to reduce the number of logic levels by 42%, the delay by 26%, and the power consumption by 32%, resulting in a energy-delay-product (EDP) reduction of 59 % over the same circuits mapped with unipolar CNTFET logic gates. Based on the projections in [1], where it is stated that defectfree CNTFETs will provide a 5x performance improvement over metal-oxide-semiconductor field effect transistors, the ambipolar library provides a performance improvement of 7x, a 57% reduction in power consumption, and a 20x improvement in EDP over the CMOS library.
TL;DR: A low-power high linearity CMOS Gm-C channel select filter for WLAN/WiMAX receivers in 90-nm CMOS technology is presented and a biquad cell with simple architecture is used to reduce power consumption and improve the linearity of the filter.
Abstract: A low-power high linearity CMOS Gm-C channel select filter for WLAN/WiMAX receivers in 90-nm CMOS technology is presented. To reduce power consumption a biquad cell with simple architecture is used. A simple but efficient technique is also proposed to improve the linearity of the filter without increasing its power consumption. Coarse and fine tuning techniques are used to tune the cutoff frequency of the sixth-order Butterworth low-pass filter from 8.1 MHz to 13.5 MHz suitable for WLAN and WiMAX applications. The measurement results show an in-band IIP3 of + 22 dBm, an HD3 better than - 40 dB at 470 mVP input signal amplitude, and an input referred noise of 75 nV/√Hz at a power consumption of 4.35 mW from a 1-V supply. The differential filter occupies a chip area of 0.239 mm2 excluding pads.
TL;DR: In this article, the 1T1R ZrO2-based resistive switching access memory with low power and highly reliable multilevel operation has high potential for practical applications.
Abstract: The Ti/ZrO2/Pt resistive memory devices with one transistor and one resistor (1T1R) architecture are successfully fabricated in this letter. The tested devices show low operation current (20 μA), low switching voltage (set/reset, 0.8/-1 V), and reliable data retention for low-resistance state (LRS) with a 20-μA set current at 80°C (over ten years) via an excellent current limiter, namely, a metal-oxide-semiconductor field-effect transistor (MOSFET). In addition, multilevel storage characteristics are also demonstrated by modulating the amplitude of the MOSFET gate voltage. The various LRS levels obtained are possibly attributed to the formation of different numbers and sizes of conducting filaments consisting of oxygen vacancies caused by an external electric field. Moreover, reproducible resistive switching characteristics up to 2000 switching cycles are achieved in the same device. Our 1T1R ZrO2-based resistive switching access memory with low-power and highly reliable multilevel operation has high potential for practical applications.
15 May 2011
TL;DR: This paper presents a complete ultra-low power receiver with direct down conversion architecture designed as Wake-up Receiver for wireless sensor nodes and includes envelope detector, low noise baseband amplifier, PGA, mixed-signal correlation unit and auxiliaries for stand-alone operation.
Abstract: This paper presents a complete ultra-low power receiver with direct down conversion architecture. It is designed as Wake-up Receiver for wireless sensor nodes. The 130nm CMOS chip includes envelope detector, low noise baseband amplifier, PGA, mixed-signal correlation unit and auxiliaries for stand-alone operation. At 868MHz, a receiver sensitivity of −71dBm is achieved with total power consumption of 2.4µW at 1.0V supply by means of baseband correlation over 7ms with 64 bit pattern, 99% detection probability and a false wake-up rate of 10−3/s.