Showing papers on "Low-power electronics published in 2012"

Design of a High-Efficiency 2.45-GHz Rectenna for Low-Input-Power Energy Harvesting

Abstract: This letter presents a high-efficiency 2.45-GHz rectenna that can harvest low input RF power effectively. A new antenna with a simple structure and high gain of 8.6 dBi is proposed for the rectenna. The antenna is designed to directly match the rectifying circuit at 2.45 GHz and mismatch it at the second and third harmonics so that the use of bandpass filter between the antenna and rectifying circuit can be eliminated. The rectenna shows a maximum conversion efficiency of 83% with a load resistance of 1400 Ω. Furthermore, the overall conversion efficiency can remain 50% for the low, -17.2 dBm (corresponding power density 0.22 μW/cm2 ) input power level.

A Portable 2-Transistor Picowatt Temperature-Compensated Voltage Reference Operating at 0.5 V

Abstract: Sensing systems such as biomedical implants, infrastructure monitoring systems, and military surveillance units are constrained to consume only picowatts to nanowatts in standby and active mode, respectively. This tight power budget places ultra-low power demands on all building blocks in the systems. This work proposes a voltage reference for use in such ultra-low power systems, referred to as the 2T voltage reference, which has been demonstrated in silicon across three CMOS technologies. Prototype chips in 0.13 μm show a temperature coefficient of 16.9 ppm/°C (best) and line sensitivity of 0.033%/V, while consuming 2.22 pW in 1350 μm2. The lowest functional Vdd 0.5 V. The proposed design improves energy efficiency by 2 to 3 orders of magnitude while exhibiting better line sensitivity and temperature coefficient in less area, compared to other nanowatt voltage references. For process spread analysis, 49 dies are measured across two runs, showing the design exhibits comparable spreads in TC and output voltage to existing voltage references in the literature. Digital trimming is demonstrated, and assisted one temperature point digital trimming, guided by initial samples with two temperature point trimming, enables TC <; 50 ppm/°C and ±0.35% output precision across all 25 dies. Ease of technology portability is demonstrated with silicon measurement results in 65 nm, 0.13 μm, and 0.18 μm CMOS technologies.

A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

Abstract: A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, < 65mV/dec subthreshold slope and <40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages. This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products.

Survey of low power testing of VLSI circuits

Abstract: The System-On-Chip (SoC) revolution challenges both design and test engineers, especially in the area of power dissipation. Generally, a circuit or system consumes more power in test mode than in normal mode. This extra power consumption can give rise to severe hazards in circuit reliability or, in some cases, can provoke instant circuit damage. Moreover, it can create problems such as increased product cost, difficulty in performance verification, reduced autonomy of portable systems, and decrease of overall yield. Low power dissipation during test application is becoming increasingly important in today's VLSI systems design and is a major goal in the future development of VLSI design.

Spin-Based Neuron Model With Domain-Wall Magnets as Synapse

Abstract: We present artificial neural network design using spin devices that achieves ultralow voltage operation, low power consumption, high speed, and high integration density We employ spin torque switched nanomagnets for modeling neuron and domain-wall magnets for compact, programmable synapses The spin-based neuron-synapse units operate locally at ultralow supply voltage of 30 mV resulting in low computation power CMOS-based interneuron communication is employed to realize network-level functionality We corroborate circuit operation with physics-based models developed for the spin devices Simulation results for character recognition as a benchmark application show 95% lower power consumption as compared to 45-nm CMOS design

A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13- $\mu$ m CMOS for Medical Implant Devices

Abstract: This paper describes an ultra-low power SAR ADC for medical implant devices. To achieve the nano-watt range power consumption, an ultra-low power design strategy has been utilized, imposing maximum simplicity on the ADC architecture, low transistor count and matched capacitive DAC with a switching scheme which results in full-range sampling without switch bootstrapping and extra reset voltage. Furthermore, a dual-supply voltage scheme allows the SAR logic to operate at 0.4 V, reducing the overall power consumption of the ADC by 15% without any loss in performance. The ADC was fabricated in 0.13-μm CMOS. In dual-supply mode (1.0 V for analog and 0.4 V for digital), the ADC consumes 53 nW at a sampling rate of 1 kS/s and achieves the ENOB of 9.1 bits. The leakage power constitutes 25% of the 53-nW total power.

Low-Power Wireless Power Delivery

Abstract: This paper addresses design and implementation of integrated rectifier-antennas (rectennas) for wireless powering at low incident power densities, from 25 to 200 μW/cm2. Source-pull nonlinear measurement of the rectifying devices is compared to harmonic-balance simulations. Optimal diode RF and dc impedances for most efficient rectification, as a function of input power, are obtained. This allows optimized antenna design, which can eliminate or simplify matching networks and improve overall efficiency. As an example of the design methodology, Schottky diodes were characterized at 1.96 GHz and an antenna is matched to the optimal complex impedance for the most efficient rectifier. For incident power density range of interest, the optimal impedance is 137 + j149 Ω, with an RF to dc conversion efficiency of the rectifying circuit alone of 63% and total rectenna efficiency of 54%.

Low-Power Design of a Self-powered Piezoelectric Energy Harvesting System With Maximum Power Point Tracking

Abstract: A low-power energy harvesting system targeting to harvest several milliwatts from vibration is presented in this paper. Several low-power design schemes to reduce power dissipation of the proposed system are described, and sources of power loss are analyzed to improve the power efficiency. A discontinuous conduction mode (DCM) flyback converter with the constant on-time modulation is adopted for our system. The DCM operation of a flyback converter is chosen as for maximum power point tracking (MPPT) to be implemented with a single current sensor. The constant on-time modulation lowers the clock frequency of the controller by more than an order of magnitude for our system, which reduces the dynamic power dissipation of the controller. MPPT, executed by a microcontroller unit (MCU), is achieved through dynamic resistive matching, and the MPPT is executed at intermittent time intervals due to a relatively slow change of the operating condition. When MPPT is not active, the MCU operates at a lower clock frequency to save power. Experimental results indicate that the proposed system harvests up to 8.4 mW power under 0.5-g base acceleration with four parallel piezoelectric cantilevers and achieves 72% power efficiency around the resonant frequency of 47 Hz.

A batteryless 19μW MICS/ISM-band energy harvesting body area sensor node SoC

Abstract: Recent advances in ultra-low power chip design techniques, many originally targeting wireless sensor networks, will enable a new generation of body-worn devices for health monitoring. We utilize the state-of-the-art in low power RF transmitters, low voltage boost circuits, subthreshold processing, biosignal front-ends, dynamic power management, and energy harvesting to realize an integrated reconfigurable wireless body-area-sensor node (BASN) SoC capable of autonomous power management for battery-free operation.

A DC/DC Boosting Technique and Power Management for Ultralow-Voltage Energy Harvesting Applications

Abstract: With the increasing use of low-voltage portable devices and growing requirements of functionalities embedded into such devices, efficient dc/dc conversion and power management techniques are needed. In this paper, an architecture for boosting extremely low voltages (about 100 mV) to the typical supply voltages of current integrated circuits is presented which is suitable for power harvesting applications too. Starting from a 120-mV supply voltage, the converter reaches an output voltage of 1.2 V, providing an output current of 220 μA and exhibiting a maximum power efficiency of about 30%. Along with the dc/dc converter, a power management circuit is presented, which can regulate the output voltage and improve the overall efficiency. A test chip was fabricated using a United Microelectronics Corporation 180-nm low-threshold CMOS process.

An Ultra Low Power Bandgap Operational at Supply From 0.75 V

Abstract: We present an ultra low power (200 nA current consumption) reverse bandgap voltage reference operational from supply voltages down to 0.75 V. The reference is a part of microprocessor system on chip implemented in a digital 130 nm CMOS process and has a total area of 0.07 mm2. The reference accuracy is ± 2.5% (5 sigma) over a temperature range of - 20 to 85°C without trimming. With trimming ± 0.5% accuracy is achieved.

A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches

Abstract: Circuit techniques for enhancing the retention time and random cycle of logic-compatible embedded DRAMs (eDRAMs) are presented. An asymmetric 2T gain cell utilizes the gate and junction leakages of a PMOS write device to maintain a high data `1' voltage level which enables fast read access using an NMOS read device. A current-mode sense amplifier (C-S/A) featuring a cross-coupled PMOS latch and pseudo-PMOS diode pairs is proposed to overcome the innate problem of small read bit-line (RBL) voltage swing in 2T eDRAMs with improved voltage headroom and better impedance matching under process-voltage-temperature (PVT) variations. A half-swing write bit-line (WBL) scheme is adopted to improve the WBL speed by 33% and reduce its power dissipation by 25% during write-back operation with no effect on retention time. A stepped write word-line (WWL) driver reduces the current drawn from the boosted high and low supplies by 67%. A 192 kb eDRAM test chip with 512 cells-per-BL implemented in a 65 nm low-power (LP) CMOS process shows a random cycle frequency and latency of 667 MHz and 1.65 ns, respectively, at 1.1 V and 85 × °C. The measured refresh period at a 99.9% bit yield condition was 110 μs which is comparable to that of recently published 1T1C eDRAM designs.

Performance and Power Dissipation Comparisons Between 28 Gb/s NRZ, PAM, CAP and Optical OFDM Systems for Data Communication Applications

Abstract: Theoretical investigations have been carried out to analyze and compare the link power budget and power dissipation of non-return-to-zero (NRZ), pulse amplitude modulation-4 (PAM-4), carrierless amplitude and phase modulation-16 (CAP-16) and 16-quadrature amplitude modulation-orthogonal frequency division multiplexing (16-QAM-OFDM) systems for data center interconnect scenarios. It is shown that for multimode fiber (MMF) links, NRZ modulation schemes with electronic equalization offer the best link power budget margins with the least power dissipation for short transmission distances up to 200 m; while OOFDM is the only scheme which can support a distance of 300 m albeit with power dissipation as high as 4 times that of NRZ. For short single mode fiber (SMF) links, all the modulation schemes offer similar link power budget margins for fiber lengths up to 15 km, but NRZ and PAM-4 are preferable due to their system simplicity and low power consumption. For lengths of up to 30 km, CAP-16 and OOFDM are required although the schemes consume 2 and 4 times as much power respectively compared to that of NRZ. OOFDM alone allows link operation up to 35 km distances.

An Energy-Efficient Memristive Threshold Logic Circuit

Abstract: Researchers have claimed that the memristor, the fourth fundamental circuit element, can be used for computing. In this work, we utilize memristors as weights in the realization of low-power Field Programmable Gate Arrays (FPGAs) using threshold logic which is necessary not only for low power embedded systems, but also realizing biological applications using threshold logic. Boolean functions, which are subsets of threshold functions, can be implemented using the proposed Memristive Threshold Logic (MTL) gate, whose functionality can be configured by changing the weights (memristance). A CAD framework is also developed to map the weights of a threshold gate to corresponding memristance values and synthesize logic circuits using MTL gates. Performance of the MTL gates at the circuit and logic levels is also evaluated using this CAD framework using ISCAS-85 combinational benchmarking circuits. This work also provides solutions based on device options and refreshing memristance, against drift in memristance, which can be a potential problem during operation. Comparisons with the existing CMOS look-up-table (LUT) and capacitor threshold logic (CTL) gates show that MTL gates exhibit less energy-delay product by at least 90 percent.

2.5D and 3D technology challenges and test vehicle demonstrations

Abstract: Three-dimensional (3D) chip integration with through-silicon-vias (TSV's) can enable system benefits of enhanced performance, power efficiency, and cost reduction leveraging micro-architecture designs such as 2.5D silicon packages and 3D die stacks. 2.5D silicon packages and 3D die stacks structures integrated in modules each have unique technical challenges but each can provide system benefits including lower latency and higher bandwidth compared to traditional packaging solutions. Additional system benefits using 2.5D or 3D integration can include product miniaturization or increased function in the same size product. Leveraging proper design and micro-architecture for a system application, 3D technology can aide chip manufacturability for lower costs, sub-component heterogeneous integration, modular design and sub-component design reuse, which can reduce development expense and decrease time to market. 2.5D and 3D technology can reduce interconnection length between circuits leading to lower power consumption and lower latency as well as increase the number of interconnections which supports increased bandwidth to traditional 2D off chip interconnection. Appropriate design ground rules, clocking, and electrical models should match well defined technology attributes such as TSV's and silicon to silicon interconnection electrical parametrics. In addition a wafer test methodology for known good die (KGD) and high yield assembly integration approach are important to obtain integrated 2.5D and 3D modules. For complex 3D integration, proper consideration for module or integrated die stacked with TSV's and Si to Si interconnection may require redundancy and an integral repair methodology. 2.5D and 3D technology challenges may include an increase in the power delivery and cooling requirements to meet the increased circuit density and power density of these structures. For small, low power applications such as mobile devices, 2.5D and 3D technology can provide substantial benefit through both performance benefit and power savings and lead to longer battery life for the same function. For some high performance and high power applications, the 2.5D approach simplifies heterogeneous die integration without requiring leading to increases power density and heat removal cooling density. Whereas some high performance and high power applications using 3D technology may require extensive planning for power delivery with localized power regulation and specialized cooling approaches to avoid excessive in die stack temperatures while taking advantage of performance gains that these short links between heterogeneous die can provide. 3D die stacks using multi-core processors and wide I/O DRAM, eDRAM, SRAM or cache stacks can provide high bandwidth, performance improvements with lower latency. In addition to the power delivery and thermal challenges of 2.5D and 3D described above, there are 3D fabrication and industry compatibility challenges. Technology challenges include wafer integration and finishing with TSV's, test for known-good-die (KGD), assembly and module integration. Infrastructure compatibility and use of newly evolving industry standards such as Semi-3D standards for wafer handling and JEDEC standards for wide I/O memory to name two examples. Standards for wafer shipping are underway and other 3D compatibility standards are being defined over time. This research paper describes key challenges to enable systems using 2.5D and 3D technology. The paper also highlights progress and results for 2.5D and 3D hardware demonstrations and gives an outlook on future demonstrations.

A Low Power Inductorless LNA With Double ${\rm G} _{\rm m}$ Enhancement in 130 nm CMOS

Abstract: This paper presents the design of a low power differential Low Noise Amplifier (LNA) in 130 nm CMOS technology for 2.45 GHz ISM band applications. The circuit benefits from several gm-enhancements. These techniques provide a high gain and reduced Noise Figure (NF) in spite of the low intrinsic gm of the MOS transistors. Moreover, the circuit is fully inductorless. Main design points are described and the performance tradeoffs of the circuit are discussed. A prototype has been implemented and it exhibits a 20 dB gain with a 4 dB NF while dissipating 1.32 mW. The IIP3 is -12 dBm for an input compression point of -21 dBm.

An Output-Capacitor-Free Adaptively Biased Low-Dropout Regulator With Subthreshold Undershoot-Reduction for SoC

Abstract: This paper presents an output-capacitor-free adaptively biased low-dropout regulator with subthreshold undershoot-reduction (ABSTUR LDR) for SoC power management applications. Techniques of adaptive biasing (AB) and Miller compensation with Q-reduction are employed to achieve low-voltage high-precision regulation with extended loop bandwidth while maintaining low quiescent current and high current efficiency. The pass transistor is designed to work in the linear region at heavy load to save silicon area, and a symmetrically matched current-voltage mirror is used to implement the AB scheme with accurate current sensing for the full load range. The dedicated STUR circuit, which is low-voltage compatible and consumes very low current in the steady state, is inserted to momentarily but exponentially increase the gate discharging current of the pass transistor when the LDR output has a large undershoot due to a large step up of the load current. Undershoot voltage is hence dramatically reduced. Stability of the ABSTUR LDR is thoroughly analyzed and tradeoffs between the undershoot-reduction strength and the light load stability are discussed. Features of the proposed ABSTUR LDR are experimentally verified by a prototype fabricated in a standard 0.35-μm CMOS process.

Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme

Abstract: In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. First, the pulse generation control logic, an and function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor and gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various postlayout simulation results based on UMC CMOS 90-nm technology reveal that the proposed design features the best power-delay-product performance in seven FF designs under comparison. Its maximum power saving against rival designs is up to 38.4%. Compared with the conventional transmission gate-based FF design, the average leakage power consumption is also reduced by a factor of 3.52.

Body-Biased Complementary Logic Implemented Using AlN Piezoelectric MEMS Switches

Abstract: This paper reports on the implementation of low-voltage complementary mechanical logic achieved by using body-biased aluminum nitride (AlN) piezoelectric microelectro-mechanical systems (MEMS) switches. By biasing the equivalent body of a four terminal mechanical switch with a fixed voltage, the threshold voltage of the mechanical transistor has been precisely tuned and the voltage swing used for implementing digital functionalities reduced to very low values (≤ ±2 V). Thanks to the use of a mechanical switching mechanism, the AlN MEMS switches have exhibited an extremely low subthreshold slope (0.065 mV/dec), which sets the promise for even further reduction of the voltage swing to less than 100 mV. By using opposite body biases, the same mechanical switch has been made to operate as an equivalent n-like or p-like (complementary) device. Two basic AlN mechanical switch elements have then been used to form a body-biased inverter operating at 100 Hz with a ±1.5-V voltage swing. Furthermore, low voltage and functionally complete logic elements (NAND and NOR) implemented by using body-biased complementary and thin-film (250 nm thick) AlN-based piezoelectric mechanical switches have been synthesized. Finally, scaling rules for these devices are derived, and the key challenges that will need to be addressed to achieve further miniaturization are presented.

Inductive and Ultrasonic Multi-Tier Interface for Low-Power, Deeply Implantable Medical Devices

Abstract: We report the development of a novel multi-tier interface which enables the wireless, noninvasive transfer of sufficient amounts of power as well as the collection and transmission of data from low-power, deeply implantable analog sensors. The interface consists of an inductive coupling subsystem and an ultrasonic subsystem. The designed and experimentally verified inductive subsystem ensures that 5 W of power is transferred across 10 mm of air gap between a single pair of PCB spiral coils with an efficiency of 83% using our prototype CMOS logic gate-based driver circuit. The implemented ultrasonic subsystem, based on ultrasonic PZT ceramic discs driven in their low-frequency, radial/planar-excitation mode, further ensures that 29 μW of power is delivered 70 mm deeper inside a homogenous liquid environment-with no acoustic matching layer employed-with an efficiency of 1%. Overall system power consumption is 2.3 W. The implant is intermittently powered every 800 msec; charging a capacitor which provides sufficient power for a duration of ~ 18nmsec; sufficient for an implant μC operating at a frequency of 500 KHz to transmit a nibble (4 bits) of digitized sensed data.

$K$ -Band CMOS Differential and Quadrature Voltage-Controlled Oscillators for Low Phase-Noise and Low-Power Applications

Abstract: In this paper, modified circuit topologies of a differential voltage-controlled oscillator (VCO) and a quadrature VCO (QVCO) in a standard bulk 90-nm CMOS process are presented for low dc power and low phase-noise applications. By utilizing current-reuse and transformer-feedback techniques, the proposed VCO and QVCO can be operated at reduced dc power consumption while maintaining extraordinary circuit performance in terms of low phase-noise and low amplitude/phase errors. The VCO circuit topology is investigated to obtain the design procedure. The VCO is further applied to the QVCO design with a bottom-series coupling technique. The coupling network between two differential VCOs and device size are properly designed based on our proposed design methodology to achieve low amplitude and phase errors. Moreover, the VCO and the QVCO are fully characterized with amplitude and phase errors via a four-port vector network analyzer. With a dc power of 3 mW, the VCO exhibits a frequency tuning range from 20.3 to 21.3 GHz, a phase noise of - 116.4 dBc/Hz at 1-MHz offset, a figure-of-merit (FOM) of -198 dBc/Hz, a phase error of 3.8° , and an amplitude error of 0.9 dB. With a dc power of 6 mW, the QVCO demonstrates a phase noise of -117.4 dBc/Hz, a FOM of -195.6 dBc/Hz, a phase error of 4° , and an amplitude error of 0.6 dB. The proposed VCO and QVCO can be compared with the previously reported state-of-the-art VCOs and QVCOs in silicon-based technologies.

An Ultra Low-Power CMOS Transceiver Using Various Low-Power Techniques for LR-WPAN Applications

Abstract: In this work, we implemented and evaluated a fully integrated 2.4 GHz CMOS RF transceiver using various low-power techniques for low-rate wireless personal area network (IEEE 802.15.4 LR_WPAN) applications in 0.18-μm CMOS technology. In order to achieve an ultra low power consumption, a RC oscillator (OSC) operating below 200 nA, a regulator operating below 200 nA for sleep mode, a quick start block for the crystal oscillator, a passive wake-up circuit, a LNA with negative gm, a current bleeding mixer, and a stacked VCO are all implemented in this transceiver. The transmitter achieves less than 5.0% error vector magnitude (EVM) at 5 dBm output, and the receiver sensitivity is -101 dBm. The sensitivity of the wake-up block is -29.8 dBm. The current consumption is below 14.3 mA for the data receiving mode, 16.7 mA for the transmitter, and less than 600 nA for the sleep mode from a 1.8 V power supply. That is considered to be lowest for the 2.4 GHz CMOS ZigBee transceiver compared to open literature results.

Carbon nanotube based ultra-low voltage integrated circuits: Scaling down to 0.4 V

Abstract: Carbon nanotube (CNT) based integrated circuits (ICs) including basic logic and arithmetic circuits were demonstrated working under a supply voltage low as 0.4 V, which is much lower than that used in conventional silicon ICs. The low limit of supply voltage of the CNT circuits is determined by the degraded noise margin originated from the process inducing threshold voltage fluctuation. The power dissipation of CNT ICs can be remarkably reduced by scaling down the supply voltage, and it is of crucial importance for the further developments of nanoelectronics ICs with higher integration density.

Resonant clock design for a power-efficient high-volume x86–64 microprocessor

Abstract: AMD's 4+ GHz x86–64 core codenamed “Piledriver” employs resonant clocking [1–4] to reduce clock distribution power up to 24% while maintaining a low clock-skew target. To support testability and robust operation at the wide range of operating frequencies required of a commercial processor, the clock system operates in two modes: direct-drive (cclk) and resonant (rclk). Leveraging favorable factors such as the availability of two thick top-level metals, high operating frequency, clock-load density, and the existing clock-design methodology [5], the rclk mode was designed to enable both reduced average power dissipation and improved peak-power-constrained performance, with minimal area impact. This work represents a volume production-enabled implementation of resonant clock technology, and is plan of record for mid-2012 product offerings.

Spin-Transfer Torque MRAMs for Low Power Memories: Perspective and Prospective

Abstract: Electron-spin based data storage for on-chip memories has the potential for ultrahigh density, low power consumption, very high endurance, and reasonably low read/write latency. In this article, we analyze the energy-performance characteristics of a state-of-the-art spin-transfer-torque based magnetic random access memories (STT-MRAM) bit-cell in the presence of parametric process variations. In order to realize ultra low power under process variations, we propose device, bit-cell and architecture level design techniques. Such design methods at various levels of design abstraction has been found to achieve substantially enhanced robustness, density, reliability and low power as compared to their charge-based counterparts for future embedded applications.

A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF

Abstract: A continuous-time bandpass ΔΣ modulator (CTBPDSM) is a good solution for software-defined-radio (SDR) since it allows much flexibility in the digital backend and also decreases the complexity of the receiver chain by combining several analog blocks into a single ADC [1]. However, conventional CTBPDSMs suffer from large power consumption and occupy large area. CTBPDSMs based on LC tanks are large, while biquad-based resonators are also large and suffer from high power consumption because two amplifiers are usually required in each resonator. The fact that there are typically twice as many feedback paths compared to a lowpass ΔΣ modulator with the same bandwidth and performance also increases power consumption, area and complexity. This paper presents a power-efficient resonator with a single amplifier and also introduces a simplified architecture utilizing return-to-zero (RZ) and half-clock-delayed return-to-zero (HZ) pulses to solve the power and complexity problems.

A 0.09 $\mu$ W Low Power Front-End Biopotential Amplifier for Biosignal Recording

Abstract: This work presents a biopotential front-end amplifier in which the MOS transistors are biased in subthreshold region with a supply voltage and current of 0.4-0.8 V and 0.23-1.86 μA, respectively, to reduce the system power. Flicker noise is then removed using a chopping technique, and differential interference produced by electrode impedance imbalance is suppressed using a Gm-C filter. Additionally, the circuit is fabricated using TSMC 0.18 μm CMOS technology with a core area of 0.77 × 0.36 mm2. With a minimum supply voltage of 0.4 V, the measured SNR and power consumption of the proposed IC chip are 54.1 dB and 0.09 μW , respectively.

An Ultralow-Power Low-Voltage Class-AB Fully Differential OpAmp for Long-Life Autonomous Portable Equipment

Abstract: This brief presents an ultralow-power class-AB operational amplifier (OpAmp) designed in a low-cost 0.18- μm CMOS technology. The proposed circuit uses transistors biased in the subthreshold region for low-voltage low-power operation. For a 0.8-V single supply, this OpAmp has 51-dB open-loop gain, 57-kHz unity-gain frequency, 60° phase margin, and 65-dB common-mode rejection ratio for 8-pF loads with a power consumption of only 1.2 μW. Experimental results illustrate performances such as a 0.14-V/μs slew rate and a 750-mV linear output swing, demonstrating its correct functionality.

A 200 °C Universal Gate Driver Integrated Circuit for Extreme Environment Applications

Abstract: High-temperature power converters (dc-dc, dc-ac, etc.) have enormous potential in extreme environment applications, including automotive, aerospace, geothermal, nuclear, and well logging. For successful realization of such high-temperature power conversion modules, the associated control electronics also need to perform at high temperature. This paper presents a silicon-on-insulator (SOI) based high-temperature gate driver integrated circuit (IC) incorporating an on-chip low-power temperature sensor and demonstrating an improved peak output current drive over our previously reported work. This driver IC has been primarily designed for automotive applications, where the underhood temperature can reach 200 °C. This new gate driver prototype has been designed and implemented in a 0.8 μm, 2-poly, and 3-metal bipolar CMOS-DMOS (Double-Diffused Metal-Oxide Semiconductor) on SOI process and has been successfully tested for up to 200 °C ambient temperature driving a SiC MOSFET and a SiC normally-ON JFET. The salient feature of the proposed universal gate driver is its ability to drive power switches over a wide range of gate turn-ON voltages such as MOSFET (0 to 20 V), normally-OFF JFET (-7 to 3 V), and normally-ON JFET (-20 to 0 V). The measured peak output current capability of the driver is around 5 A and is thus capable of driving several power switches connected in parallel. An ultralow-power on-chip temperature supervisory circuit has also been integrated into the die to safeguard the driver circuit against excessive die temperature (≥220 °C). This approach utilizes increased diode leakage current at higher temperature to monitor the die temperature. The power consumption of the proposed temperature sensor circuit is below 10 μW for operating temperature up to 200 °C.

A Low Power Inductorless LNA With Double Gm Enhancement in 130 nm CMOS

Abstract: This paper presents the design of a low power differential Low Noise Amplifier (LNA) in 130 nm CMOS technology for 2.45 GHz ISM band applications. The circuit benefits from several g m -enhancements. These techniques provide a high gain and reduced Noise Figure (NF) in spite of the low intrinsic g m of the MOS transistors. Moreover, the circuit is fully inductorless. Main design points are described and the performance tradeoffs of the circuit are discussed. A prototype has been implemented and it exhibits a 20 dB gain with a 4 dB NF while dissipating 1.32 mW. The IIP 3 is ―12 dBm for an input compression point of —21 dBm.