Showing papers on "Low-power electronics published in 2014"

Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator

Abstract: The need for ultra low-power, area efficient, and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In this paper, an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double-tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. Post-layout simulation results in a 0.18- μm CMOS technology confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 2.5 and 1.1 GHz at supply voltages of 1.2 and 0.6 V, while consuming 1.4 mW and 153 μW, respectively. The standard deviation of the input-referred offset is 7.8 mV at 1.2 V supply.

11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS

Abstract: Analog-to-digital converters (ADC) are extensively used in wireless sensor networks and healthcare electronic devices to monitor long-term signal conditions. It is essential to prolong battery life in these applications by using an energy-efficient ADC. A successive-approximation register (SAR) architecture, mostly composed of digital circuits, can achieve low power under low supply voltages [1,2]. Power consumption can be decreased by using either an energy-efficient capacitive-DAC switching method [1] or a low-power comparator with a majority voting technique [2]. In this work, a small coarse ADC resolves the MSB bits. Then, a detect-and-skip algorithm and an aligned switching technique are used to reduce the big fine DAC switching energy. The comparator power is also decreased by utilizing a low-power comparator during coarse conversion and a low-noise comparator during fine conversion. As a result, its FoM performance is as low as 0.85fJ/conversion-step, which is about 3 times better than that of the state-of-the-art work [2].

Compressed Sensing Analog Front-End for Bio-Sensor Applications

Abstract: In a conventional bio-sensor, key signal features are acquired using Nyquist-rate analog-to-digital conversion without exploiting the typical bio-signal characteristic of sparsity in some domain (e.g., time, frequency, etc.). Compressed sensing (CS) is a signal processing paradigm that exploits this sparsity for commensurate power savings by enabling alias-free sub-Nyquist acquisition. In a severely energy constrained sensor, CS also eliminates the need for digital signal processing (DSP). A fully-integrated low-power CS analog front-end (CS-AFE) is described for an electrocardiogram (ECG) sensor. Switched-capacitor circuits are used to achieve high accuracy and low power. Implemented in 0.13 μm CMOS in 2×3 mm2, the prototype comprises a 384-bit Fibonacci-Galois hybrid linear feedback shift register and 64 digitally-selectable CS channels with a 6-bit C-2C MDAC/integrator and a 10-bit C-2C SAR ADC in each. Clocked at 2 kHz, the total power dissipation is 28 nW and 1.8 μW for one and 64 active channels, respectively. CS-AFE enables compressive sampling of bio-signals that are sparse in an arbitrary domain.

23.1 A 0.15V-input energy-harvesting charge pump with switching body biasing and adaptive dead-time for efficiency improvement

Abstract: Design of low-voltage and efficient energy-harvesting circuits is becoming increasingly important, particularly, for autonomous systems. Since the amount of energy that can be harvested from the surrounding environment is limited, the available output voltage of a harvester is low. Therefore, the design of a low-input-voltage (low-VIN) up-converter is critical to self-powered systems [1-3]. Moreover, the form factor is very constrained in applications such as wearable electronic devices and sensor networks. Recently, low-VIN charge pumps (CPs) for energy harvesting has been compared with DC-DC converters using a large inductor [1-3]. CPs introduced in [1] and [2] use the advanced process technology to push VIN down to the subthreshold region. The CP in [1] introduces a forward-body-biasing (FBB) technique, which improves the voltage conversion efficiency (VCE) for low VIN but shows poor power conversion efficiency (PCE). The CP in [2] achieves the lowest operation voltage. However, the design with a 10-stage CP provides low output power. This paper presents a CP with switching-body-biasing (SBB), adaptive-dead-time (AD), and switch-conductance (SW-G) enhancement techniques to improve the PCE for low VIN as well as to extend the maximum load current.

23.2 A 1.1nW energy harvesting system with 544pW quiescent power for next-generation implants

Abstract: A wireless sensor that is powered from the endocochlear potential (EP), a 70-to-100mV bio-potential inside the mammalian ear, has been demonstrated in [1]. Due to the anatomical size and physiological constraints inside the ear, a maximum of 1.1 to 6.25nW can be extracted from the EP. The nanowatt power budget of the sensor gives rise to unique challenges with power conversion efficiency and quiescent current reduction in the power management unit (PMU). While [1] presents the system aspects of the biomedical harvesting including the biologic interface and system measurements, this work presents the details of the nanowatt PMU required to power the electronics. More specifically, it focuses on the low-power circuit design techniques needed to realize a nW power converter that is applicable to a broad spectrum of emerging biomedical applications with ultra-low energy-harvesting sources.

13.2 A 14nm FinFET 128Mb 6T SRAM with V MIN -enhancement techniques for low-power applications

Abstract: With the explosive growth of battery-operated portable devices, the demand for low power and small size has been increasing for system-on-a-chip (SoC). The FinFET is considered as one of the most promising technologies for future low-power mobile applications because of its good scaling ability, high on-current, better SCE and subthreshold slope, and small leakage current [1]. As a key approach for low-power, supply-voltage (VDD) scaling has been widely used in SoC design. However, SRAM is the limiting factor of voltage-scaling, since all SRAM functions of read, write, and hold-stability are highly influenced by increased variations at low VDD, resulting in lower yield. In addition, the width-quantization property of FinFET device reduces the design window for transistor sizing, and increases the failure probability due to the un-optimized bitcell sizing [1]. In order to overcome the bitcell challenges to high yield, peripheral-assist techniques are required. In this paper, we present 14nm FinFET-based 128Mb 6T SRAM chips featuring low-VMIN with newly developed assist techniques.

Low-Voltage Steep Turn-On pMOSFET Using Ferroelectric High- $\kappa$ Gate Dielectric

Abstract: Power consumption is the most difficult challenge for CMOS integrated circuits. Here, we demonstrate experimentally a novel steep turn-on pMOSFET for low-voltage operation for the first time, which exhibits 5-60 mV/decade SS, wide voltage range for , sturdy SS at 85°C, faster transistor turn-on at above threshold voltage, and lower off-state leakage by greater than three orders of magnitude. Such improved leakage current is crucial to decrease the OFF-state leakage current in sub-1X nm CMOS. This was achieved using ferroelectric high-κ ZrHfO gate dielectric pMOSFET.

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications

Abstract: Recently there has been increased demand for not only ultra-low power, but also high performance, even in standby-power-critical applications. Sensor nodes, for example, need a microcontroller unit (MCU) that has the ability to process signals and compress data immediately. A previously reported 130nm CMOS and FeRAM-based MCU features zero-standby power and fast wakeup operation by incorporating FeRAM devices into logic circuits [1]. The 8MHz speed, however, was not sufficiently high to meet application requirements, and the FeRAM process also has drawbacks: low compatibility with standard CMOS, and write endurance limitations. A spintronics-based nonvolatile integrated circuit is a promising option to achieve zero standby power and high-speed operation, along with compatibility with CMOS processes. In this work, we demonstrate a fully nonvolatile 16b MCU using 90nm standard CMOS and three-terminal SpinRAM technology. It achieves 20MHz, 145μW/MHz operation with a 1V supply in the active state, and 4.5μW intermittent operation with 120ns wakeup time and 0.1% active ratio, without forwarding of re-boot code from memory. The features provide sufficiently long battery life to achieve maintenance-free sensor nodes.

A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration

Abstract: This paper presents a low-jitter, low-power and a small-area injection-locked all-digital PLL (IL-ADPLL). It consists of a dual-loop and a dual-VCO architecture in which one VCO (Replica) is placed in a TDC-less synthesizable ADFLL to provide continuous tracking of voltage and temperature variations. The other VCO (main) shares the control voltage with the replica VCO but is placed outside the loop and is injection-locked to lower its jitter and accurately set its frequency to the desired one. This approach avoids timing problems in the conventional ILPLL since the injection-locked VCO is placed outside the feedback loop. It also achieves a low power and a small area, due to the absence of a power hungry TDC and an area-consuming loop filter, while tracking any PVT variations. The IL-ADPLL is implemented in a 65 nm CMOS process and measurement results show that it achieves a 0.7ps RMS jitter at 1.2 GHz while having 1.6 mW and 0.97 mW power consumption with and without intermittent operation resulting in an FOM of -243 dB. It also consumes an area of only 0.022 mm2 resulting in the best performance-area trade-off system presented up-to-date.

22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers

Abstract: High-speed low-resolution ADCs are widely used for various applications, such as 60GHz receivers, serial links, and high-density disk drive systems. Flash architectures have the highest conversion rate without employing time interleaving. Moreover, flash architectures have the lowest latency, which is often required in feedback-loop systems. However, the area and power consumption are exponentially increased by increasing the resolution since the number of comparators must be 2N. A folding architecture is a well-known technique to reduce the number of comparators in an ADC while maintaining high sampling rate and low latency [1,2]. Folding architectures were previously realized by generating a number of zero crossings with folding amplifiers. However, the conventional folding amplifiers consume a large amount of power to realize a fast response. In contrast, a folding ADC with only dynamic power consumption and without using amplifiers is reported in [3]. However, only a folding factor of 2 is realized, and therefore the number of comparators is reduced by half.

15.3 A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO

Abstract: Due to the high supply sensitivity of ring voltage-controlled oscillators (RVCOs) ([oscillation frequency change %] / [VDD change %] typically lies in the range from 1 to 2 [1]), an LDO has to provide over 40dB power-supply-rejection ratio (PSRR) to maintain VCO phase noise. However, the voltage dropout of an LDO consumes extra power and voltage headroom, which is unacceptable in low-voltage design. Moreover, the device noise from the LDO degrades the phase-noise performance. Recently published works [1-5] employ analog compensation techniques to lower supply sensitivity, and [2] incorporates a hybrid background calibration scheme for robustness. However, the additional current sources and active devices embedded in the oscillator [1-5] increase power and noise. In this work, a DCO with passive devices and all-digital calibration mitigates supply sensitivity under PVT variation, while maintaining phase noise and power consumption. The digital background-calibration logic regulates the oscillator supply to an optimally insensitive point by monitoring a digital loop filter (DLF) code, leveraging an advantage of an ADPLL [6].

SHE-NVFF: Spin Hall Effect-Based Nonvolatile Flip-Flop for Power Gating Architecture

Abstract: A novel nonvolatile flip-flop (NVFF) using a magnetic tunnel junction (MTJ) is presented for power gating architecture. The proposed NVFF exploits spin Hall effect (SHE) for fast and low-power data backup into MTJs before the power is gated off. Owing to the high spin injection efficiency of SHE, the estimated write current for backup operation is lower than 40 μA. Due to the low write current requirement, we do not introduce a dedicated write driver circuit. Instead, we utilize the cross-coupled inverters in the slave latch to perform the backup operation, resulting in low area overhead. The simulation results show 10× improvement in backup energy when compared with previous works on spin transfer torque-based NVFFs.

MOST Moderate–Weak-Inversion Region as the Optimum Design Zone for CMOS 2.4-GHz CS-LNAs

Abstract: In this paper, the MOS transistor (MOST) moderate-inversion (MI)-weak-inversion (WI) region is shown to be the optimum design zone for CMOS 2.4-GHz common-source low-noise amplifiers (CS-LNAs) focused on low power consumption applications. This statement is supported by a systematic study where the MOST is analyzed in all-inversion regions using an exhaustive CS-LNA noise-figure (NF)-power-consumption optimization technique with power gain constraint. Effects of bias choke resistance and MOST capacitances are carefully included in the study to obtain more accurate results, especially for the MI-WI region. NF, power consumption, and gain versus the inversion region are described with design space maps, providing the designer with a deep insight of their tradeoffs. The Pareto-optimal design frontier obtained by calculation-showing the MI-WI region as the optimum design zone-is reverified by extensive electrical simulations of a high number of designs. Finally, one 90-nm 2.4-GHz CS-LNA Pareto optimal design is implemented. It achieves the best figure of merit considering under-milliwatt CS-LNAs published designs, consuming 684 μW, an NF of 4.36 dB, a power gain of 9.7 dB, and a third-order intermodulation intercept point of -4 dBm with load and source resistances of 50 Ω.

Improved Accuracy Current-Mode Multiplier Circuits With Applications in Analog Signal Processing

Abstract: This brief presents two original implementations of improved accuracy current-mode multiplier/divider circuits. Besides the advantage of their simplicity, these original multiplier/divider structures present the advantage of very small linearity errors that can be obtained as a result of the proposed design techniques (0.75% and 0.9%, respectively, for an extended range of the input currents). The original multiplier/divider circuits permit a facile reconfiguration, the presented structures representing the functional basis for implementing complex function synthesizer circuits. The proposed computational structures are designed for implementing in 0.18-μm CMOS technology, with a low-voltage operation (a supply voltage of 1.2 V). The circuits' power consumptions are 60 and 75 μW, respectively, while their frequency bandwidths are 79.6 and 59.7 MHz, respectively.

Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through

Abstract: In this brief, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Based on post-layout simulation results using TSMC CMOS 90-nm technology, the proposed design outperforms the conventional P-FF design data-close-to-output (ep-DCO) by 8.2% in data-to-Q delay. In the mean time, the performance edges on power and power- delay-product metrics are 22.7% and 29.7%, respectively.

An Area-Efficient CMOS Time-to-Digital Converter Based on a Pulse-Shrinking Scheme

Abstract: An area-efficient CMOS time-to-digital converter (TDC) based on a pulse-shrinking scheme with an improved cyclic delay line is proposed to achieve low thermal sensitivity in this brief. First, by only thermally compensating the pulse-shrinking unit rather than all delay cells, a large number of compensated circuits could be removed to reduce costs, and the thermal sensitivity of the TDC was still greatly reduced. Additionally, based on the improved cyclic delay line with identical logic gates, an undesired shift resolution caused by the mismatch between the inhomogeneous gates can be successfully eliminated, and the effective resolution can be completely determined by the pulse-shrinking unit. The proposed circuit was fabricated in a Taiwan Semiconductor Manufacturing Company Limited (TSMC) 0.35- μm CMOS technology and has an extremely small chip area of 0.025 mm2, which is much smaller than the 0.12 mm2 of its predecessor. The effective resolution is approximately 40 ps/LSB (least significant bit), and the corresponding integral nonlinearity errors are all within ±0.6 LSB. The experimental results show that a ±5.5% resolution variation of the proposed TDC was achieved in a 0 °C-100 °C temperature range. The measured power consumption is 1.65 μW at a measurement rate of 10 samples/s.

TFET Inverters With n-/p-Devices on the Same Technology Platform for Low-Voltage/Low-Power Applications

Abstract: This paper investigates feasible inverter configurations based on co-optimized n- and p-type tunnel field-effect transistors (TFETs) integrated on the same InAs/Al0.05Ga0.95 Sb platform. Based on 3-D full-quantum simulations, the considered devices feature steep subthreshold slopes and relatively high on- currents and are combined into two inverter designs. Benchmarking against aggressively scaled CMOS logic based on multigate architectures highlights potential of the proposed TFET implementations to perform up to 10× and 100× faster in low operating power and low standby power environments, respectively. The comparison is conducted at low supply voltages (VDD=0.25 V) and for equal levels of static power consumption. The proposed TFET-based platform is thus expected to be a good candidate for low-voltage/low-power applications in near-future technology generations.

Design Criteria of Low-Power Oscillators for Consumer-Grade MEMS Resonant Sensors

Abstract: This paper discusses the constraints in the design of circuits for microelectromechanical systems (MEMS) resonant sensors in consumer applications, presents a novel integrated circuit implementation, and shows that this approach can be competitive with respect to the mostly used capacitive readout. From a circuit design perspective, it is shown how the large equivalent resistance typical of MEMS resonators, their operation close to mechanical nonlinearity, and the effect of feedthrough capacitances on the oscillating loop constrain the power requirements of the driving/readout electronics. As a case study, a resonant accelerometer built in an industrial process is coupled to a suitably designed transimpedance amplifier with a low-power “hard limiter.” The performance shown in terms of linearity across the measurement range (±8 g), minimum measurable acceleration (1 mg with a readout bandwidth of 100 Hz), and power consumption (≈ 100 μW per axis) is comparable to those of state-of-the-art capacitive inertial sensors.

15.2 A 0.012mm 2 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider

Abstract: Digital phase-locked loops (DPLLs) [1-7] have received considerable attention recently due to their compatibility with advanced CMOS technology. However, there are two critical factors hindering their uptake in SoC products. One factor is that a digitally controlled oscillator (DCO) is highly sensitive to supply noise. A common solution is to apply voltage regulation or to adopt digital calibration [2] at the cost of larger area, higher power consumption or both. The other factor is a power-hungry time-to-digital converter (TDC), which typically requires complex auxiliary circuitry to overcome sensitivity to process, voltage and temperature [3]. A bang-bang phase/frequency detector (BBPFD) is a good alternative to the TDC for low-power small-size applications. A fractional-N implementation, however, still demands a fractional frequency divider with high design complexity [5]. This paper presents a bang-bang all-digital fractional-N PLL, which occupies a small area, consumes low power and addresses the aforementioned issues. A block diagram of the fractional-N DPLL is shown in Fig. 15.2.1. An automatic frequency controller (AFC) tunes a DCO frequency in the foreground for fast locking. The DCO employs a supply-noise canceling architecture to address the power supply noise issue with negligible power and area overhead. We adopt a phase-interpolator-based fractional divider controlled by a walking-one phase selector for low power and compactness.

9.3 A 1mW 1Mb/s 7.75-to-8.25GHz chirp-UWB transceiver with low peak-power transmission and fast synchronization capability

Abstract: Future binaural hearing-aid devices face severe energy constraints on the wireless links where the ear-to-ear link enables signal processing of sound for both ears to enhance speech intelligence and the ear-to-device link provides an audio channel to commercial electronics such as smart TVs, MP3 players, and smart phones. Due to the limited size of the battery (35 to 90mAh) especially for in-the-ear (ITE) and in-the-canal (ITC) types, a sub-mW transceiver is required for long operational time. A low-data-rate impulse-radio ultra-wideband (IR-UWB) transceiver [1] achieves low power consumption with aggressive duty-cycled operation, namely 1%, but suffers from the bit-level synchronization problem by the baseband. Moreover, the low-data-rate IR-UWB exhibits a high peak transmission power to maintain a sufficient average transmission power for the given link margin. The constant-envelope frequency-modulated ultra-wideband (FM-UWB) system in [2,3] features a low peak voltage and a steep roll-off spectrum, but the lack of duty-cycled operation makes it difficult to achieve low power. Narrowband WBAN transceivers such as the Bluetooth Low Energy (BLE) transceiver [4,5] offer good compliance with existing wireless SoCs, but the sub-mW power consumption is not feasible and they have a potential coexistence problem with existing Bluetooth devices. In this paper, a chirp-FSK-based UWB transceiver is proposed to significantly reduce the peak transmission power with relaxed duty-cycled operation for noninvasive, energy-efficient, and agile short-range communications.

A 7.65-mW 5-bit 90-nm 1-Gs/s Folded Interpolated ADC Without Calibration

Abstract: Power consumption of high-speed low-resolution analog-to-digital converters (ADCs) can be reduced by means of calibration. However, this solution has some drawbacks such as time slot allocation for calibration and die area increase. This paper presents a 5-bit 1-Gs/s ADC without calibration, fabricated in 90-nm CMOS. Low power consumption has been ensured by operating at both architecture and comparator levels. A folded interpolated architecture has been adopted. However, compared to standard solutions that use static preamplifiers, the interpolation technique has been implemented by taking recourse to dynamic comparators, enabling significant power saving. Moreover, despite the high operating frequency, intrinsic matching has been ensured while keeping low power consumption. The ADC uses double-tail dynamic comparators, operating with a fixed bias current and with reduced kickback noise. Large input transistors are used to guarantee the targeted matching, thereby avoiding calibration. The ADC achieves 4.3b-ENOB (effective number of bits) and 260-MHz effective resolution bandwidth while consuming 7.65 mW from a 1.2 V supply. The ADC figure of meritis 0.39 pJ/conv. step, which is the state-of-the-art performance for an uncalibrated ADC at this sampling frequency and resolution.

Low-Power DT $\Delta \Sigma$ Modulators Using SC Passive Filters in 65 nm CMOS

Abstract: A comparative design study of ultra-low-power discrete-time ΔΣ modulators (DT ΔΣMs) suited for medical implant devices is presented. Aiming to reduce the analog power consumption, the objective is to investigate the effectiveness of the switched-capacitor passive filter. Two design variants of 2nd-order ΔΣMs are analyzed and compared to a power-optimized standard active modulator (ΔΣMAA). The first variant (ΔΣMAP) employs an active filter in the 1st stage and a passive filter in the less critical 2nd stage. The second variant (OTA-less ΔΣMPP) makes use of passive filters in both stages. For practical verification, all three modulators are implemented on a single chip in 65 nm CMOS technology. Designed for 500-Hz signal bandwidth, the ΔΣMAA, ΔΣMAP, and ΔΣMPP achieve 76 dB, 70 dB and 67 dB peak SNDR, while consuming 2.1 μW, 1.27 μW, and 0.92 μW, respectively, from a 0.9 V supply. Furthermore, the ΔΣMPP can operate at a supply voltage reduced to 0.7 V, achieving a 65 dB SNDR at 430 nW power and 0.296 pJ/step.

Average-8T Differential-Sensing Subthreshold SRAM With Bit Interleaving and 1k Bits Per Bitline

Abstract: This paper presents a new average-8T write/read decoupled (A8T-WRD) SRAM architecture for low-power sub/near-threshold SRAM in power-constraint applications such as biomedical implants and autonomous sensor nodes. The proposed architecture consists of several novel concepts in dealing with issues in sub/near-threshold SRAM including: 1) the differential and data-independent-leakage read port that facilitates robust and faster read operation and alleviates issues in the half-selected cell (pseudo-write) while reducing the area compared to the conventional 8T cell and 2) the various configurations from 14T for a baseline cell to 6.5T for an area-efficient 16-bit cell. These configurations reduce the overall bitcell area and enable low operating voltage. Two memory blocks based on the proposed architecture at the size of 16 and 64 kb, respectively, are fabricated in 0.13-μm CMOS process. The 64 kb prototype has an active area of 0.512 mm2 which is 16% less than that of the conventional 8T-cell-based design. The chip is fully functional for the read operation with 260 mV at 245 kHz and 270 mV for the write operation at 1 MHz. It can hold data down to 170 mV where the standby power consumption is only 884 nW.

27.8 A static contention-free single-phase-clocked 24T flip-flop in 45nm for low-power applications

Abstract: Near-threshold computing (NTC) is an attractive solution to stagnating energy efficiencies in digital integrated circuits, arising from slowed voltage scaling in nanometer CMOS [1-2]. The design of sequential elements for NTC, as well as in voltage-scaled systems operating at both near-threshold and super-threshold, has not been extensively studied. However, it is well known that sequential elements have a strong sensitivity to process variations in NTC [2], which can have a significant impact on system yield and power consumption. In order to achieve reliable energy-efficient operation across a wide operating voltage range, a flip-flop should have the following attributes: 1) static operation, since dynamic nodes are highly susceptible to PVT variations at low voltage; 2) contention-free transitions, since ratioed logic has poor robustness across the wide range of device ION/IOFF ratios incurred with voltage scaling; 3) single-phase clocking, which avoids toggling of internal clock inverters and the corresponding power penalty; 4) minimum or no area penalty compared to conventional flip-flops.

Advanced system on a chip design based on controllable-polarity FETs

Abstract: Field-Effect Transistors (FETs) with on-line controllable-polarity are promising candidates to support next generation System-on-Chip (SoC). Thanks to their enhanced functionality, controllable-polarity FETs enable a superior design of critical components in a SoC, such as processing units and memories, while also providing native solutions to control power consumption. In this paper, we present the efficient design of a SoC core with controllable-polarity FET. Processing units are speeded-up at the datapath level, as arithmetic operations require fewer physical resources than in standard CMOS. Power consumption is decreased via embedded power-gating techniques and tunable high-performance/low-power devices operation. Memory cells are made smaller by merging the access interface with the storage circuitry. We foresee the advantages deriving from these techniques, by evaluating their impact on the design of SoC for a contemporary telecommunication application. Using a 22-nm vertically-stacked silicon nanowire technology, a coarse-grain evaluation at the block level estimates a delay and power reduction of 20% and 19% respectively, at a cost of a moderate area overhead of 15%, with respect to a state-of-art FinFET technology.

Low-power programmable-logic cell arrays using nonvolatile complementary atom switch

Abstract: Programmable-logic cell that utilizes complementary atom switch (CAS) is fabricated using 65-nm node CMOS process. A 16-bit ALU is implemented and demonstrated on a 24×24 programmable-logic cell array including 645kbit CAS for both routing switches and configuration memories. Comparing the conventional cell design using CMOS routing multiplexer (MUX), the proposed programmable-logic cell array performs 60% active power saving and 3 times faster operation.

A Low-Voltage Low-Power Wide-Tuning-Range Hybrid Class-AB/Class-B VCO With Robust Start-Up and High-Performance ${\rm FOM}_{ T}$

Abstract: This paper proposes a hybrid class-AB/class-B voltage-controlled oscillator (VCO) with low voltage, low power, and a wide tuning range. The class-AB VCO core is designed to ensure robust start-up of the class-B VCO core. Featuring a high-efficiency class-B VCO core, the combination of class-AB/class-B VCO cores consumes low dc power. Based on the proposed architecture, the fabricated 0.18-μm CMOS VCO exhibits a measured tuning range of 25.6%. Operating at a low supply voltage of 0.75 V, the hybrid class-AB/class-B VCO cores consume a low total dc power of 2.4 mW. In this bias condition, the measured average value of phase noise for all frequency ranges is -101.4 dBc/Hz at 1-MHz offset from the carriers. Compared to recently published wide-tuning range VCOs, the proposed hybrid class-AB/class-B VCO simultaneously achieves a low supply voltage, a low dc power dissipation, and wide tuning range, leading to a good figure-of-merit including the tuning range (FOMT). In addition, the theories for analyzing the VCO are given in detail, and the mechanisms are validated by experiments.

3.4 A dual-mode transformer-based doherty LTE power amplifier in 40nm CMOS

Abstract: Modern high-data-rate communication systems such as LTE use spectrally efficient modulation schemes with a high peak-to-average power ratio (PAPR), placing stringent linearity demands on the RF power amplifiers (PA). The main challenge for LTE power amplifiers is therefore to achieve high efficiency and high linearity for a wide power range. In addition, delivering Watt-level output power is another challenge for CMOS RF power amplifiers due to the low breakdown voltage of the transistors. Series-combining transformers (SCT) enable high output power levels by summing up the output voltages of low-voltage CMOS power amplifiers [1-4].

Ultra-low power electronics with Si/Ge tunnel FET

Abstract: Si/Ge Tunnel FET (TFET) with its subthermal subthreshold swing is attractive for low power analog and digital designs. Greater Ion/Ioff ratio of TFET can reduce the dynamic power in digital designs, while higher gm/IDS can lower the bias power of analog amplifier. However, the above benefits of TFET are eclipsed by MOSFET at a higher power/performance point. Ultra low power scalability of the key analog and digital circuits, SRAM and operational transconductance amplifier (OTA), with TFET is demonstrated. Analyzing a TFET based cellular neural network, this work shows the feasibility of ultra-low-power neuromorphic computing with TFET.

An Energy Efficient Time-Domain Temperature Sensor for Low-Power On-Chip Thermal Management

Abstract: Because temperature variations significantly affect the performance and reliability of highly integrated chips, the thermal management of such chips is an important issue. In this paper, a time-domain process variation calibrated temperature sensor is proposed for on-chip thermal management. For a suitable on-chip implementation, the digitally converted temperature-dependent time signal is used to reduce the area and power consumption of the chip. The proposed temperature sensor is fabricated using a 0.13- μm CMOS technology and has an active area of 0.031 mm2. Measurement results show an energy consumption of 0.67 nJ/conversion at a 430 kHz conversion rate, with 1.2 V supply voltage. Using one-point calibration, the sensing error is found to range from -0.63°C to 1.04°C over a temperature range of 20°C to 120°C.