Showing papers on "Low-power electronics published in 2016"

Superconductor digital electronics: Scalability and energy efficiency issues (Review Article)

Abstract: Superconductor digital electronics using Josephson junctions as ultrafast switches and magnetic-flux encoding of information was proposed over 30 years ago as a sub-terahertz clock frequency alternative to semiconductor electronics based on complementary metal-oxide-semiconductor (CMOS) transistors. Recently, interest in developing superconductor electronics has been renewed due to a search for energy saving solutions in applications related to high-performance computing. The current state of superconductor electronics and fabrication processes are reviewed in order to evaluate whether this electronics is scalable to a very large scale integration (VLSI) required to achieve computation complexities comparable to CMOS processors. A fully planarized process at MIT Lincoln Laboratory, perhaps the most advanced process developed so far for superconductor electronics, is used as an example. The process has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm, and a thin s...

A Subthreshold ARM Cortex-M0+ Subsystem in 65 nm CMOS for WSN Applications with 14 Power Domains, 10T SRAM, and Integrated Voltage Regulator

Abstract: The Internet of Things (IoT) is widely predicted to comprise billions of connected devices, many of which will be wireless sensor nodes (WSN). Energy efficiency is a huge challenge here, followed by node cost and ease of software (SW) development. Addressing all of the above, this paper presents an 11.7 pJ/cycle subthreshold ARM Cortex-M0+ WSN processing subsystem implemented in low-leakage 65 nm CMOS. Voltage and frequency scalability is from 850 nW active power at 250 mV to 66 MHz above 900 mV, with a fully integrated 82% peak-efficiency voltage regulator for direct-battery operation, and supporting 80 nW CPU and RAM state-retention power gating for SW transparent leakage reduction. SW and system optimization approaches are described and a $2.94\;\boldsymbol{\upmu}{\text{W}}$ SW ECG workload is presented.

Low-power technique for dynamic comparators

Abstract: A low-power technique to reduce the power consumption of the dynamic comparators is presented. Using this technique, the pre-amplification phase of the comparator is stopped without any effect on the dynamic behaviour of the comparator. Therefore, the power consumption of the pre-amplifier stage which is the main part of the total power consumption is reduced significantly. Simulation results in various comparators reveal that the proposed technique reduces the total power consumption by more than 50%.

Operation and control of an insulated gate bipolar transistor-based current controlling device for power flow applications in multi-terminal high-voltage direct current grids

Abstract: One of the main problems that need to be solved to allow the realisation of multi-terminal high-voltage direct current (HVDC) transmission systems is the absence of a practical power flow control method. Industry leaders and researchers have proposed a few methods of power flow control based on either the control of converter station or the connection of new power electronic equipment to the grid. This study presents the operation and control of a three-port insulated gate bipolar transistor-based current flow control (CFC) device suitable for multi-terminal HVDC systems. Key features and functionalities of the proposed controller including the balancing of cable currents, limiting the magnitude of cable current and current nulling are demonstrated. The three-port CFC was simulated using power system computer aided design (PSCAD)/electromagnetic transient and direct current (EMTDC), network simulation software to evaluate its steady state and dynamic performance. Furthermore, low-power prototypes are implemented for a two and three-ports CFC to experimentally validate their different functionalities. Simulation and experimental studies explore the fast dynamic response and the results show that the CFC studied may have a significant role to play in the control of power flows in multi-terminal high-voltage DC systems.

Adiabatic logic: An alternative approach to low power application circuits

Abstract: Today's major concerns in designing VLSI circuits have been the amount of power dissipated by these circuits. The Adiabatic logic technique is becoming an answer to the problem of power dissipation. The term ‘Adiabatic’ refers to the change of state that occurs without the loss or gain of heat. The adiabatic switching technique reduces the power dissipation during switching events. But, adiabatic circuits highly depend upon power clock and parameter variations. In this paper mux, one bit sum and carry adder are designed and simulated on cadence Virtuoso using 180nm technology. In an analysis PFAL is compared with conventional CMOS logic on the basis of frequency and supply voltage. The proposed technique shows the reduction of power dissipation as compared to the conventional CMOS design style. And results analysis accomplishes that adiabatic logic can be used for the implementation of relatively large, complex circuits that dissipate less energy than conventional CMOS designs.

0.5 V fully differential current conveyor using bulk-driven quasi-floating-gate technique

Abstract: This study presents a new low-voltage (LV) supply and low-power consumption bulk-driven quasi-floating-gate fully differential current conveyor (BD–QFG-FDCCII) active element which is suitable for LV signal processing applications. The bulk-driven technique is used to achieve LV supply as low as a 0.5 V and extended input voltage swing. On the other hand, the quasi-floating-gate technique is used to achieve high-frequency performance. To prove the workability of the proposed circuit, new voltage-mode biquadratic filter and fifth-order leap-frog low-pass filter using BD–QFG-FDCCIIs as active devices have been designed and illustrated in this study. The functionality of the proposed circuits is demonstrated through PSPICE simulations using Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 µm n-well complementary metal–oxide–semiconductor technology with a 0.5 V supply voltage and a power consumption of 16.1 µW.

A 1.1 $\mu \text{W}$ CMOS Smart Temperature Sensor With an Inaccuracy of ±0.2 °C ( ${3}\sigma )$ for Clinical Temperature Monitoring

Abstract: In this paper, an ultra-low power, high accuracy CMOS smart temperature sensor customized for clinical temperature monitoring based on substrate p-n-p bipolar junction transistors (BJTs) is presented. A power efficient analog front end with a sensing-range customized multi-ratio pre-gain stage is proposed to effectively utilize the input range of the incremental analog-to-digital converter to relax the conversion speed and resolution requirement. A block-based data weighted averaging technique is also proposed to achieve highly accurate pre-gain ratios while significantly reducing the implementation complexity. The complete temperature sensor is implemented in a standard 0.18 $\mu \text{m}$ CMOS process occupying an active area of 0.198 mm2. Measurement results from 20 test chips show that an inaccuracy of ±0.2 °C ( $3\sigma )$ is achieved from 25 °C to 45 °C after one-point calibration. The average power consumption is 1.1 $\mu \text{W}$ at a conversion speed of 2 Sa/s.

General Top/Bottom-Plate Charge Recycling Technique for Integrated Switched Capacitor DC-DC Converters

Abstract: Energy loss due to top/bottom plate parasitic capacitances is one of the factors determining the efficiency of integrated switched capacitor DC/DC converters. This loss is particularly significant when MOS gate or deep trench capacitors are used. We propose a technique for top/bottom-plate charge recycling that can be applied with low overhead independently of the converter architecture. Two examples of application of the technique are presented. First, it is shown how the technique can be applied to any converter by transforming it to an interleaved implementation. This approach is demonstrated in a series-parallel 1/3 down converter achieving a maximum load power of 240 $\mu\text{W}$ . Simulation results show an improvement of 7% in the efficiency by decreasing the top/bottom-plate parasitic capacitance losses by 52%. The second example considers an architecture where the proposed technique can be directly applied without additional transformations of the converter implementation. It is a ring modular architecture converter, which was fabricated in a 130 nm CMOS process. An efficiency improvement of up to 4% was achieved in measurements by reducing the top/bottom plate losses by 70%, thus reaching an outstanding efficiency of 80.6% at a conversion ratio of 2/3 and a maximum load power of 2.2 mW.

A Multi-Frequency Multi-Standard Wideband Fractional- $ { N}$ PLL With Adaptive Phase-Noise Cancellation for Low-Power Short-Range Standards

Abstract: This paper presents a wideband fractional- $ { N}$ frequency synthesizer design with a low-effort adaptive calibration technique for $\Sigma \Delta $ quantization noise cancellation. After adopting from the classical single-ended loop filter structure, this least mean square algorithm based calibration technique can precisely and efficiently adjust the noise cancellation digital–analog convertor current with high linearity and immunity. Besides, as long as the desired current is achieved, the calibration circuits are turned off and disconnected to save the power consumption and isolate from the signal paths. With the proposed phase-noise cancellation technique, small area and low power circuit design are achieved, meanwhile the fractional and reference spurs are highly attenuated, allowing the wideband direct frequency/phase modulation with high data rates. With low effort modification, it can be directly implemented as straightforward phase-noise enhancement for any wideband phase-locked loop applications.

An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating

Abstract: Leakage power is an important component of the total power consumption in field-programmable gate arrays (FPGAs) built using 90-nm and smaller technology nodes. Power gating was shown to be effective at reducing the leakage power. Previous techniques focus on turning OFF unused FPGA resources at configuration time; the benefit of this approach depends on resource utilization. In this paper, we present an FPGA architecture that enables dynamically controlled power gating, in which FPGA resources can be selectively powered down at run-time. This could lead to significant overall energy savings for applications having modules with long idle times. We also present a CAD flow that can be used to map applications to the proposed architecture. We study the area and power tradeoffs by varying the different FPGA architecture parameters and power gating granularity. The proposed CAD flow is used to map a set of benchmark circuits that have multiple power-gated modules to the proposed architecture. Power savings of up to 83% are achievable for these circuits. Finally, we study a control system of a robot that is used in endoscopy. Using the proposed architecture combined with clock gating results in up to 19% energy savings in this application.

Logic gates realized by nonvolatile GeTe/Sb2Te3 super lattice phase-change memory with a magnetic field input

Abstract: Nonvolatile memory devices or circuits that can implement both storage and calculation are a crucial requirement for the efficiency improvement of modern computer. In this work, we realize logic functions by using [GeTe/Sb2Te3]n super lattice phase change memory (PCM) cell in which higher threshold voltage is needed for phase change with a magnetic field applied. First, the [GeTe/Sb2Te3]n super lattice cells were fabricated and the R-V curve was measured. Then we designed the logic circuits with the super lattice PCM cell verified by HSPICE simulation and experiments. Seven basic logic functions are first demonstrated in this letter; then several multi-input logic gates are presented. The proposed logic devices offer the advantages of simple structures and low power consumption, indicating that the super lattice PCM has the potential in the future nonvolatile central processing unit design, facilitating the development of massive parallel computing architecture.

RF remotely-powered integrated system to nullify standby power consumption in electrical appliances

Abstract: In order to increase energy efficiency in electrical appliances, autonomy in WSN (Wireless Sensor Network) nodes, IoT (Internet of Things) devices and self-powered sensors, it is necessary to reduce energy consumption as much as possible. One of the main issues to solve is reduction of standby power consumption, which is not negligible due to the enormous number of appliances involved. While in standby, power management circuits are permanently on, consuming unnecessary energy. This leads designers to consider power efficiency. In this article, a different approach is introduced based on Radio Frequency to electrical energy transduction with the intention to resolve this issue. The proposed solution goes beyond the well-known concept of standby as it instead applies to electric appliances that are off. An RF powered receiver silicon IC (integrated circuit) for remotely controlled systems is presented. This includes an RF-to-DC energy converter specifically designed with a sensitivity of −18.8dBm, which allows an operating distance of up 8 meters at 900 MHz with a transmitting power of 1Watt in free space. Experimental results using a complete working prototype will be shown.

A 90 nm leakage control transistor based clock gating for low power flip flop applications

Abstract: The continuous growing demand of portable battery-powered electronics devices hunts for Nano-electronic circuit design for ultra-low power applications by reducing dynamic power, static power and short circuit power. In sequential circuit elements of an IC, a notable amount of power dissipation occurs due to the rapid switching of high frequency clock signals, which do not fetch any data bit or information. The needless switching of clock, during the HOLD phase of either ‘logic 1’ or ‘logic 0’, may be abolished using gated clock. In this paper, we have presented a new clock gating technique incorporating Leakage Control Transistor. The improvised technique is employed to trigger a D-Flip Flop using 90nm PTM technology at 1.1V power supply. We have observed an impressive reduction in power, delay and latency using the proposed gating logic, which has outsmarted the existing works. The simulation is also performed in smaller technology nodes such as 65nm, 45nm and 32 nm to notice the change in delay, dynamic power and static power of the circuit.

Analysis of NAND/NOR gates using subthreshold adiabatic logic (SAL) for ultra low power applications

Abstract: In this paper, in depth analysis of the NAND/NOR gates in the weak inversion regime using sub-threshold adiabatic logic (SAL) has been analyzed. As either pull up or pull down network in SAL, silicon area can be reduced significantly. The analytical expression of the power dissipation, leakage energy dissipation, and maximum and minimum output voltages is detailed here. Also the analytical expression of the optimum supply voltage and the frequency are given for the analysis. Extensive CADENCE simulations have been done to verify the analytical expressions. Simulated results are well matched with the analytical value which validates the acceptability of the proposed structure in the sub-threshold regime for the ultra low power application.

Triple-resonance RLC-tank divide-by-2 injection-locked frequency divider

Abstract: Conventional CMOS injection-locked frequency dividers (ILFDs) were often designed with a single-resonance LC resonator and they have a single-band locking range. Wide-locking range in these ILFDs was obtained at the cost of lower output power. A triple-resonance (TR) resistor (R), inductor (L) and capacitor (C)-tank ILFD is presented to design a wide-locking range CMOS divide-by-2 circuit, which is based on a cross-coupled n-core MOS pair. The TR ILFD has three overlapped locking ranges seen as one-band locking range at high microwave injection power and it has large output power. At the core power consumption of 6.76 mW and at the microwave input power of 0 dBm, the divide-by-2 TR ILFD achieve a maximum locking range of 5.77 GHz (105.2%) from 2.6 to 8.37 GHz.

Ultra-low power current mode all- MOS ASK demodulator for radio frequency identification applications

Abstract: An ultra-low power amplitude shift keying (ASK) demodulator for radio frequency identification (RFID) tags is presented. On the basis of a fast averaging stage, the proposed ASK-demodulator uses a current domain switching envelope amplifier which yields low-power operation. More importantly, it removes the need for a conventional voltage comparator. Designed and fabricated in a 0.18 µm complementary metal–oxide–semiconductor process on about 3000 µm2 silicon area, the proposed demodulator consumes only 7.5 µA from a magnetically coupled induced power. Operating with a 13.56 MHz carrier frequency, the circuit supports modulation indices from 7 up to 100%. The demodulator may as well be used in passive biomedical devices where power efficiency is crucial.

A 151-nW Adaptive Delta-Sampling ADC for Ultra-Low Power Sensing Applications

Abstract: This brief presents a novel analog-to-digital converter (ADC) with adaptive delta-sampling for ultra-low power sensing applications. By sampling only the incremental value of the input signal and adaptively adjusting the sampling frequency, the proposed ADC can achieve the same resolution and conversion range with less number of bits than the conventional ADC. Meanwhile, the power consumption is also very much reduced. The proposed 8-bit ADC is fabricated in a 0.18- $\mu\text{m}$ CMOS technology. It achieves 7.3 effective number of bits at an adaptive sampling frequency of 20 kHz/2 kHz, consuming only 151 nW for a neural signal acquisition application.

An experimental study on thermal energy harvesting using Ca0.15(Sr0.5Ba0.5)0.85Nb2O5 pyroelectric ceramics

Abstract: Pyroelectric materials can be used for energy harvesting in integrated Micro-Electro-Mechanical-Systems (MEMS) and low power electronics devices. This paper considers the thermal energy harvesting using Ca0.15(Sr0.5Ba0.5)0.85Nb2O5 (CSBN) pyroelectric ceramics. Hot/cold air was used to generate a continuous temporal temperature profile on the material surfaces. The maximum open circuit voltage was observed as 0.26V. The maximum stored energy was 1.9 μJ in 47 μF capacitor (without load resistance). The maximum power was found to be 2.07nW across 3 MΩ and 47 μF.

Subthreshold leakage power reduction in VLSI circuits: A survey

Abstract: As technology enters into deep submicron regime, subthreshold leakage power increases exponentially and become a limiting factor in the performance of portable and battery operated electronic devices. To increase the life of battery and computational capacities of portable devices the reduction of power in standby/ sleep mode is evident. Now a day's power dissipation emerged as a major design constraint in the device miniaturization and integration of huge number of transistors. A detailed survey of alternative techniques to reduce subthreshold leakage power is presented in this paper.

An ESL framework for low power architecture design space exploration

Abstract: Designers of complex SoCs have to face the issue of tuning their design to achieve low power consumption without compromising performance. A set of complementary techniques at hardware level are able to reduce power consumption but most of these techniques impact system performance and behavior. At register transfer level, low power design flows are available. Unfortunately, equivalent design flows at transactional level are missing. In this paper we describe how a power/clock intent could be described at transactional level using a separation of concerns process and how the transactional simulation code merging functional and power behaviors can be generated automatically using a model-driven engineering approach.

Low-power quadrature voltage-controlled oscillator using current-reuse and transformer-based Armstrong topologies

Abstract: A new low-power current-reuse quadrature voltage-controlled oscillator (QVCO) is proposed. The proposed QVCO couples two complementary current-reuse Armstrong voltage-controlled oscillators (VCOs) using series coupling switches. The current-reuse technique reduces the power consumption, and the transformer-based Armstrong configuration improves the phase noise performance by increasing the negative Gm of the VCO core. The proposed QVCO consumes 2.46 mW of power at 8.71 GHz from a 1.1 V supply. The measured phase noise is −113.3 dBc/Hz at the offset frequency of 1 MHz, and the figure of merit is −188.2 dBc/Hz. The frequency tuning range is from 8.34 to 9.13 GHz. The chip area is 700 × 340 μm2 in a 0.13 μm CMOS process.

Micropower CMOS lock-in amplifier for portable applications

Abstract: A new fully integrated micropower CMOS analogue lock-in amplifier (LIA) is presented. To achieve a compact architecture able to operate under low voltage with low-power consumption, it is based on a current-mode amplifier with embedded rectification within the transconductance stage. Post-layout results for a 0.18 µm CMOS implementation show a dynamic reserve of 51.2 dB, a power consumption of 482 µW and an integration area of 0.03 mm2. The frequency operation ranges from 450 Hz to 1.1 MHz, whereas the gain is programmable from 39 to 59 dB, providing the LIA with flexibility to match a wide range of applications.

Highly linear TIA for SAW-less FDD receivers

Abstract: A highly linear trans-impedance amplifier TIA is proposed to meet stringent linearity requirements of SAW-less frequency-division duplexing (FDD) LTE receivers with 20MHz channel bandwidth. In the proposed solution the operational amplifier is compensated exploiting the passive feedback network in order to achieve wide bandwidth and low power dissipation. The prototype in 28nm CMOS achieves 14dB of gain with 20MHz bandwidth and features 46 dBm IIP3 and 12μV in-band noise, with 5.4mW power dissipation and a filter FOM of 183 dB.

MBus: A System Integration Bus for the Modular Microscale Computing Class

Abstract: I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized--yet reusable--components with an interconnect that permits tiny, ultra-low-power systems. In contrast to today's interconnects, which are limited by power-hungry pull-ups or high-overhead chip select lines, the authors' approach operates at lower power, with a fixed pin count, using fully synthesizable logic, and with surprisingly low-protocol overhead. The authors present MBus, a new four-pin, 22.6 pJ/bit/chip chip-to-chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low-power system operation by automatically power gating each chip in the system, easing the integration of active and inactive circuits. In addition, they introduce power-oblivious communication, which guarantees message reception even if the recipient is inactive. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that draw nanowatts.

Low-power charge-steering phase interpolator

Abstract: The demand for low-power equalisation at high data rates in serial-link receivers has prioritised the issue of power consumption. This high demand has also involved the phase-locked loop (PLL) and clock and data recovery (CDR) circuits. This propelled efforts to further optimise the PLLs and CDRs building blocks and to pursue low-power solutions. A charge-based phase interpolator (PI) is presented. It employs charge-steering circuits in order to reduce the power typically consumed by its current-based counterpart. Implemented in 65-nm CMOS technology, a 6-bit charge-based PI consumes 180 μW at 1–V supply and 5-GHz clock.

Continuous-time four-quadrant modulator with inherent PVT cancellation

Abstract: A continuous-time four-quadrant multiplier in subthreshold region is presented. Besides its simplicity, the structure features inherent process–voltage–temperature (PVT) variation cancellation while working under low voltage supply and dissipating an ultra-low power. The PVT variation was alleviated through an inherent log/anti-log cancellation technique, making it as a good candidate for bio-potential acquisition systems. The input and output signals are currents resulting in a wider bandwidth and larger dynamic range compared with the voltage-mode counterparts. The circuit is versatile and can be configured as a modulator, frequency doubler, and linear variable gain amplifier as shown in theory and simulation results.

Stacked transistor based multimode power efficient MTCMOS full adder design in 90nm CMOS technology

Abstract: High rate of power consumption in the digital integrated circuit is the major field of concern in the development of VLSI circuits. Demand of higher speed, multiple operations and smaller process geometry contributes in the leakage power. So today leakage power consumption is the most important source of power dissipation rather than run time power consumption. Previously many techniques have been proposed for the leakage reduction. Amongst all MTCMOS technique carries the property of being most efficient in leakage reduction. In this paper we are going to analyze the different types of low power adder circuits with different types of low power design methodologies. The comparison results have also been displayed in this paper. The circuits are simulated in 90nm CMOS technology using tanner EDA simulator.

Subthreshold leakage power reduction by Feedback Sleeper-Stack technique

Abstract: As per the International Technology Roadmap for Semiconductors (ITRS) the leakage power is growing exponentially and is the major part of total power consumption in the integrated device. With the growing impact of subthreshold and gate leakage, static leakage contributes more and more towards the power dissipation in deep submicron nano CMOS technology. To overcome this problem several techniques has been proposed. In this paper we analyses the subthreshold leakage minimization techniques in circuit level. We propose a circuit technique named “Feedback Sleeper-Stack (FS-S)” for efficient leakage reduction in digital circuits. The proposed technique is compared with available leakage reduction techniques for subthreshold power, total power, delay and PDP (Power Delay Product). Of the available techniques, three power gating techniques are considered for comparison namely, Sleeper, Forced Stacking (FS) and Sleepy Stack (SS). Nominal supply voltage of 0.9V is selected and 32nm BSIM4 Predictive Technology Models (PTM) is employed in the analysis. ELDO Mentor Graphics tool is used for net list simulation.

A W-band wireless communication transmitter utilizing a stacked-FET oscillator for high output power performance

Abstract: This paper reports on an efficient transmitter monolithic microwave integrated circuit (TX MMIC) suitable for high-speed wireless communication. In order to achieve high output power, the TX is based on a direct modulation approach, containing a stacked-FET voltage-controlled oscillator (VCO) and an amplitude modulator. Thus, the modulation scheme is based on amplitude-shift keying (ASK). The MMIC utilizes the Fraunhofer IAF 50nm gate-length metamorphic high-electron-mobility transistor (mHEMT) technology. The stacked-FET oscillator generates the carrier signal and achieves an output power of about 14 dBm. The carrier frequency can be tuned from 87.8 to 98.2 GHz. Due to the FET-stacking approach the amplitude modulator can be simplified to a single-pole, single-throw (SPST) switch. Hence, the transmitter MMIC achieves a peak output power of 12.5dBm and a maximum data rate of 18 Gbit/s. The maximum continuous wave (CW) efficiency of the entire TX MMIC yields 17.6 %.

The Future of Low-Power Electronics

Abstract: The number of integrated transistors has increased so rapidly that it has become evident that a further increase of the performance is limited by the power dissipation. The future IT and electronics, therefore, require more efficient power-reduction solutions. In the human brain and nerve system, analog signals from sensing orgasms are processed by a network composed of neurons and synapses. This process is slow but very power-efficient because it is done by below-100 mV signal levels.