Showing papers on "Low-power electronics published in 2019"

Switching Delay in Self-Powered Nonlinear Piezoelectric Vibration Energy Harvesting Circuit: Mechanisms, Effects, and Solutions

Abstract: Piezoelectric vibration energy harvesting (PVEH) has been proved to be much promising in making low power electronics completely self-powered due to wide availability and high energy density. Self-powered synchronized switching harvesting on an inductor (SSHI) circuits have been proved to greatly increase the performance of a PVEH device and peak detector-based self-powered switches are widely used. In practice, however, the switch is impossible to turn on simultaneously at peak displacements due to nonlinear components so that switching delay (SD) always exists. Furthermore, the SD will degrade the performance of PVEH devices, so it must be reduced. Therefore, for this kind of SSHI circuits, the purpose of this paper is to explore basic causes of generating SD and investigate the corresponding solution. First, theoretical model of SD in self-powered parallel SSHI (SP-PSSHI) is derived and the SD is first proved to be positive. Then, effects of key component parameters on the SD are studied. Based on above results, an improved SP-PSSHI (ISP-PSSHI) circuit is proposed by adding a voltage divider and its SD is proved to be less than that of the SP-PSSHI circuit. Next, the key factor is discussed, namely the divider resistor. Circuit simulations validate theoretical results and also expose that there are optimal resistor and capacitor of the envelope detector for achieving the maximum harvested power. In the end, experimental results show that the ISP-PSSHI circuit can improve the averaged harvested power about 11% more than that of the SP-PSSHI circuit under choosing optimal components.

Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

Abstract: Flip-flops (FFs) are essential building blocks of sequential digital circuits but typically occupy a substantial proportion of chip area and consume significant amounts of power. This paper proposes 18-transistor single-phase clocked (18TSPC), a new topology of fully static contention-free single-phase clocked (SPC) FF with only 18 transistors, the lowest number reported for this type. Implemented in 65-nm CMOS, it achieves 20% cell area reduction compared to the conventional transmission gate FF (TGFF). Simulation results show the proposed 18TSPC is two times more efficient than TGFF in the energy-delay space. To demonstrate EDA compatibility and circuit/system-level benefits, a shift register and an AES-128 encryption engine have been implemented. Chip experimental measurements at 0.6 V, 25 °C show that, compared to TGFF, the proposed 18TSPC achieves reductions of 68% and 73% in overall and clock dynamic power, respectively, and 27% lower leakage.

Transmission gate-based 9T SRAM cell for variation resilient low power and reliable internet of things applications

Abstract: Higher variation resilience, lower power consumption, and higher reliability are the three principal design metrics for designing a static random-access memory (SRAM) cell. The most intuitive way to achieve lower power consumption is voltage scaling. However, voltage scaling at nanometre technology nodes leads to degradation in the robustness of the SRAM cell and decreased data stability. It is proved that conventional 6T SRAM fails to maintain its stability in scaled technology, particularly in the deep-subthreshold regime. Furthermore, SRAM cells utilising techniques such as read decoupling, for achieving reliable read operation, tend to increase leakage current resulting in higher hold power, which contributes a major portion to the total power consumption in modern internet of things devices. To cater to the requirements of higher robustness and lower hold power dissipation, a transmission gate-based 9T SRAM is proposed, which achieves these requirements at the cost of slightly higher read and write access time. The simulations are performed utilising a 16-nm complementary metal oxide semiconductor model.

A RISC-V Based Open Hardware Platform for Always-On Wearable Smart Sensing

Abstract: We present a fully programmable ultra-low-power embedded platform that hosts an "electronic skin" (E-skin) arrays of tactile sensors with up to 64 channels, ECG/EMG sensors up to 8 channels, inertial sensors, and a Bluetooth Low Energy 5.0 module. The platform’s compute engine is a heterogeneous multi-core parallel ultra-low power (PULP) processor based on RISC-V, capable of delivering up to 2.5 GOPS, within a 55 mW power consumption envelope, which makes the platform ideal for battery-powered always-on operation. Experimental results show a peak of 38.3x energy efficiency increase (0.7 V, 85 MHz) compared to ARM-Cortex-M microcontrollers with similar power budgets.

Design of efficient quantum Dot cellular automata (QCA) multiply accumulate (MAC) unit with power dissipation analysis

Abstract: Quantum dot cellular automata (QCA) is a hopeful technology in the field of nanotechnology that seems to suite well with signal-processing needs. It is concerned with great interest because of its benefits such as ultra-low power consumption, small size and can operate at one Terahertz. The multiply accumulator (MAC) unit is considered as one of the essential operations in digital signal processing (DSP). In the real-time DSP systems, several applications like speech processing, video coding, and digital filtering etc. require MAC operations. However, the power dissipation and area are the most significant aspects in these systems. Here, the authors design low power MAC unit based on QCA technology. QCADesigner version 2.0.3 is used to validate the accuracy of the proposed circuit. The reliability of this unit is taken at different temperatures. The power dissipation is estimated using QCAPro tool. The total power consumed by this unit is 2.183 μW. The proposed circuit has 90% improvement in terms of power over complementary metal–oxide–semiconductor (CMOS) circuits. Since the works in the field of QCA logic signal processing has started to progress, the suggested contribution will give rise to a new thread of research in the field of real-time signal and image treatment.

Research and development of ultra-low power LoraWan sensor node

Abstract: The work presents the project of ultra-low power sensor node for IoT applications with LoRa interface, which was successfully designed and tested. The main features of this design is its low power consumption, long distance communication and secure data transmission. By using external nano timer TPL5110 it is possible to reduce the end node consumption current Ic from 4.2uA to 290nA. This increases battery life and sensor autonomous operation.

Ultra-low-voltage CMOS ring oscillators

Abstract: This communication discusses the realisation of ultra-low-voltage CMOS ring oscillators (ROs) that are potentially capable of starting up from a supply voltage V DDmin of around 40 mV. Experimental results for ROs based on the standard inverter and on the six-transistor Schmitt trigger integrated in a 130 nm CMOS technology demonstrate a start-up voltage very close to 50 mV.

0.5 V bulk-driven CMOS fully differential current feedback operational amplifier

Abstract: This study presents a new low-voltage fully differential current feedback operational amplifier for ultra-low-voltage and low-power analogue circuit applications. A bulk-driven technique is used to reduce the supply voltage requirement and also provides a rail-to-rail input voltage common-mode swing. The proposed circuit has been simulated using a TSMC 0.18 µm n-well CMOS technology with a 0.5 V supply voltage. Simulation results show that the static power consumption of the proposed circuit is 4.7 µW. The proposed circuit has been used to realise fully differential integrators and fully low-pass / band-pass second-order filters to express the performance of the new circuit.

Implementation of capacitor multiplier with cell-based variable transconductance amplifier

Abstract: Portable and implantable devices dictate the system integration and low power consumption Digital integrated circuits (ICs) design with small-size transistors enables system integration and low power consumption However, analogue IC design for biomedical application is critical for system integration and low power consumption The presence of passive circuit elements such as capacitors that occupies more area on the chip has led the analogue IC's designers to the search for different solutions Capacitor multiplier is one of intelligent solution for system integration of analogue processing unit of biomedical applications In this work, a new capacitor multiplier circuit is proposed with recently recommended cell-based variable transconductance amplifier The performance of the proposed circuit is verified with post-layout simulations and worst-case analysis under 135 corners including variations of process, temperature and power supply The multiplication factor of the designed capacitor multiplier is 98 The verification of the designed circuit is proved in Cadence environment with TSMC 018 μm technology

Highly-digital voltage scalable 4-bit flash ADC

Abstract: This study describes the highly-digital 4-bit 200 MS flash analogue to digital converter (ADC) whose major part can be digitally synthesised thus achieving low power, reducing the time-to-market and is scalable with technology. The comparators used in the ADC consist of complementary metal-oxide-semiconductor (CMOS)-based inverter and NAND-NOR as standard cells. The complete flash ADC is designed in 180 nm CMOS technology with 1.8 V supply with the power consumption of 4.51 mW. The signal-to-noise and distortion ratio, signal-to-noise ratio and spurious-free dynamic range are equal to 23.3, 25.2 and 30.1 dB. It provides an effective number of bits equal to 3.5. The differential non-linearity (DNL) of this ADC is ± 0.25 LSB and integral non-linearity (INL) is + 0.6 LSB.

High-speed sub-threshold operation of carbon nanotube interconnects

Abstract: Sub-threshold voltage operated circuits are the future for ultra-low-power applications. These circuits are inherently slow due to the very small sub-threshold currents. Here, the authors propose two approaches for improving the speed of SWCNT bundle interconnects driven by CNTFET-based circuits under sub-threshold conditions. First, the authors modulate the channel length of the CNTFETs that are used in the driver circuits to increase sub-threshold output current. The output current is maximum when the channel length is optimised to 15 nm. Second, the authors design driver circuits made of CNTFET-based inverters and transmission gates for SWCNT bundle interconnects at sub-threshold voltages. The authors consider five different configurations of the driver and load circuits. SPICE simulations show that transmission gates play a vital role in driver circuits by reducing the propagation delay and increasing the switching speed at high frequencies. Finally, the authors perform temperature-dependent analysis of the best cases from the proposed circuits and show that the propagation delay and power dissipated by them increases drastically at increased temperatures up to 500 K.

The Insect Brain as a Model System for Low Power Electronics and Edge Processing Applications

Abstract: The insect brain is a great model system for low power electronics: insects carry out multisensory integration and are able to change the way the process information, learn, and adapt to changes in their environment with a very limited power budget. This context-dependent processing allows them to implement multiple functionalities within the same network, as well as to minimize power consumption by having context-dependent gains in their first layers of input processing. The combination of low power consumption, adaptability and online learning, and robustness makes them particularly appealing for a number of space applications, from rovers and probes to satellites, all having to deal with the progressive degradation of their capabilities in remote environments. In this work, we explore architectures inspired in the insect brain capable of context-dependent processing and learning. Starting from algorithms, we have explored three different implementations: a spiking implementation in a neuromorphic chip, a custom implementation in an FPGA, and finally hybrid analog/digital implementations based on cross-bar arrays. For the latter, we found that the development of novel resistive materials is crucial in order to enhance the energy efficiency of analog devices while maintaining an adequate footprint. Metal-oxide nanocomposite materials, fabricated using ALD with processes compatible with semiconductor processing, are promising candidates to fill in that role.

Signal Waveform Impact on Efficiency of Low Power Harvesting Devices in WSN

Abstract: The paper is devoted to the study of the impact of different multi-tone signals on the efficiency of low power harvesting devices in wireless sensor networks (WSN). Moreover, the impact of the load resistance on harvesting device performance is examined. For the current experimental study a low power RF harvesting device, consisting of a classic voltage doubler circuit for RF-DC conversion and a DC-DC converter based on Texas Instruments manufactured chip BQ25504, is used. Single-tone and 8–64 multi-tone signals with high and low peak-to-average power ratio (PAPR) levels are employed as signal waveforms. A software defined radio (SDR) USRP B210 and a PC with MATLAB/Simulink software are used for generation and RF transmission of different waveforms in an unlicensed sub-gigahertz ISM band. To generate low PAPR signals, Zadoff-Chu sequences and an IFFT operation are employed, but for high PAPR signal generation subcarriers with the same amplitude are summed together in phase. To evaluate the efficiency of RF-DC conversion of the low power harvesting device, the voltage at the input and output of the classic voltage doubler circuit is measured. For the performance estimation of the harvesting device the average output power of the DC-DC power converter is also measured.

Low Leakage Clock Tree With Dual-Threshold- Voltage Split Input–Output Repeaters

Abstract: Leakage power consumption of clock distribution networks (CDNs) is an important challenge in modern synchronous integrated circuits with billions of deeply scaled transistors. Multithreshold CMOS technology is commonly used to provide power reduction in standby mode while maintaining high performance in active mode. In this paper, a novel dual-threshold-voltage repeater circuit with split inputs–outputs (SPLIT-IOs) is employed for suppressing leakage currents in gated CDNs. Three floor planning strategies are considered for clock distribution across the chip with signal transition times of less than or equal to 50 ps at the leaves. Depending on the power supply voltage and floor plan, the standby leakage power consumption is reduced by 50.36%–78.43% with the proposed clock tree with SPLIT-IO repeaters as compared to the conventional three-level H-tree in a 45-nm CMOS technology. The spread of standby leakage power due to process variations is compressed by 36.72%–73.77% with the proposed clock tree as compared to the standard network. The proposed circuit technique significantly lowers the total energy consumption of partially active networks with local clock gating as well. The energy savings provided by the SPLIT-IO buffers are enhanced with the scaling of power supply voltage and frequency in synchronous systems-on-chip.

High‐speed, low power, and dead zone improved phase frequency detector

Abstract: Design of a novel phase frequency detector (PFD) has been presented here. The innovative advantage of the proposed structure is its improved dead zone performance due to the architectural simplicity which is a combination of static and pass transistor logic (PTL)-based latch configuration. Due to low latency from inputs to the outputs, the operating frequency of the proposed circuit is high while its power consumption is very low. Analytics along with simulations have confirmed the correct behaviour of the designed circuit. For better evaluation of designed architecture advantages, two of the last reported works have been redesigned and simulated along with the proposed PFD. The post-layout simulation results using HSPICE with TSMC 0.18 µm CMOS technology and 1.8 V power supply demonstrate the operating frequency of 1 GHz for the designed circuitry while the power dissipation is 277 µW and the measured dead zone is π / 11 as an enormous enhancement over previous works.

Self-Powered Portable Electronic Reader for Point-of-Care Amperometric Measurements.

Abstract: In this work, we present a self-powered electronic reader (e-reader) for point-of-care diagnostics based on the use of a fuel cell (FC) which works as a power source and as a sensor. The self-powered e-reader extracts the energy from the FC to supply the electronic components concomitantly, while performing the detection of the fuel concentration. The designed electronics rely on straightforward standards for low power consumption, resulting in a robust and low power device without needing an external power source. Besides, the custom electronic instrumentation platform can process and display fuel concentration without requiring any type of laboratory equipment. In this study, we present the electronics system in detail and describe all modules that make up the system. Furthermore, we validate the device's operation with different emulated FCs and sensors presented in the literature. The e-reader can be adjusted to numerous current ranges up to 3 mA, with a 13 nA resolution and an uncertainty of 1.8%. Besides, it only consumes 900 µW in the low power mode of operation, and it can operate with a minimum voltage of 330 mV. This concept can be extended to a wide range of fields, from biomedical to environmental applications.

Low leakage domino logic circuit for wide fan-in gates using CNTFET

Abstract: A carbon nanotube field effect transistor (CNTFET) emerged as an alternative to the complementary metal oxide semiconductor (CMOS) for implementing low-power high-speed very-large-scale integration circuits. In this study, the CNTFET technology is discussed that has faster switching speed and high-carrier mobility as compared with the CMOS technology. A new technique ultra-low power dynamic node driven transistor domino logic is proposed for designing low-power domino logic circuits. 2, 4, 8 and 16 input logic gates are simulated using the proposed and existing techniques. Simulation is done on an H-Spice Stanford CNFET 32 nm model at a clock frequency of 200 MHz using the CNTFET technology. The proposed technique shows a maximum power reduction of 57.14% and a maximum delay reduction of 50.24% as compared with the current mirror footed domino logic technique in CNTFET technology. The proposed technique has a maximum power reduction of 96.61% in the CNTFET technology as compared with its counterpart in the CMOS technology for the two-input OR gate. The proposed technique shows a maximum improvement of 1.39× in unity noise gain as compared with the conditional stacked keeper domino logic technique for 16 input OR gates in the CNTFET technology at 200 MHz.

Thermal energy harvester powered piezoresistive pressure sensor system with wireless operation for nuclear reactor application.

Abstract: To access the crucial parameters of a nuclear reactor during station blackout condition, we have proposed a concept of using thermal energy harvester powered sensors and instrumentation with wireless operation. To demonstrate this concept, low power electronics comprising a micro electro mechanical system piezoresistive pressure sensor, amplifier, and wireless transmitter was developed for measurement of pressure in a reactor process. The required electrical power for the sensor and instrumentation was derived from the thermal energy produced by the reactor process itself. A thermoelectric generator was used as an energy harvester for converting the heat energy from the process to electrical energy. A power management circuitry was used for the management of the power which was fed to the sensor and electronics. The complete instrumentation was tested in a test loop to demonstrate the operation of thermal energy harvester powered sensor with wireless operation for static and dynamic pressure measurements. Static pressure, increase or decrease of pressure with time and pressure oscillations were measured in a wireless mode using the developed instrumentation. Differential mode measurements were also carried out. The concept of thermal energy harvester powered sensor and instrumentation presented in this paper would be suitable for wireless sensor network of self-powered/thermal energy harvester powered sensors and for wearable devices by operators. An overview of the design and development of the instrumentation and the results are presented in this paper.To access the crucial parameters of a nuclear reactor during station blackout condition, we have proposed a concept of using thermal energy harvester powered sensors and instrumentation with wireless operation. To demonstrate this concept, low power electronics comprising a micro electro mechanical system piezoresistive pressure sensor, amplifier, and wireless transmitter was developed for measurement of pressure in a reactor process. The required electrical power for the sensor and instrumentation was derived from the thermal energy produced by the reactor process itself. A thermoelectric generator was used as an energy harvester for converting the heat energy from the process to electrical energy. A power management circuitry was used for the management of the power which was fed to the sensor and electronics. The complete instrumentation was tested in a test loop to demonstrate the operation of thermal energy harvester powered sensor with wireless operation for static and dynamic pressure measurements....

Numerical Optimization of a Fully Cross-Coupled Rectifier Circuit for Wireless Passive Ultra Low Power Sensor Nodes.

Abstract: In the context of the Internet of Things, billions of devices-especially sensors-will be linked together in the next few years. A core component of wireless passive sensor nodes is the rectifier, which has to provide the circuit with sufficient operating voltage. In these devices, the rectifier has to be as energy efficient as possible in order to guarantee an optimal operation. Therefore, a numerical optimization scheme is proposed in this paper, which is able to find a unique optimal solution for an integrated Complementary Metal-Oxide-Semiconductor (CMOS) rectifier circuit with Self-Vth-Cancellation (SVC). An exploration of the parameter space is carried out in order to generate a meaningful target function for enhancing the rectified power for a fixed communication distance. In this paper, a mean conversion efficiency is introduced, which is a more valid target function for optimization than the Voltage Conversion Efficiency (VCE) and the commonly used Power Conversion Efficiency (PCE) and is defined as the arithmetic mean between PCE and VCE. Various trade-offs between output voltage, PCE, VCE and MCE are shown, which provide valuable information for low power rectifier designs. With the proposed method, a rectifier in a low power 55 nm process from Globalfoundries (GF55LPe) is optimized and simulated at -30 dBm input power. A mean PCE of 63.33% and a mean VCE of 63.40% is achieved.

Charge balancing symmetric pre-resolve adiabatic logic against power analysis attacks

Abstract: A novel, energy efficient and power analysis robust logic style called the charge balancing symmetric pre-resolve adiabatic logic (CBSPAL) is proposed to overcome the susceptibility of cryptosystems against side channel power analysis attacks. It employs differential cascode logic tree structure with a pre-resolving feature, which realises improved energy efficiency by minimising non-adiabatic loss and leakage current. The energy efficiency of the proposed logic against static complementary metal oxide semiconductor (CMOS) and other existing secure adiabatic logic styles is proved. Energy deviation for the different input transitions of the individual logic gates, namely, buffer/NOT, AND/NAND and XOR/XNOR is found to be very minimal and it validates the immunity of the proposed logic against power analysis attacks. SPICE simulation of 4-bit add-round structure implementation using CBSPAL shows an energy saving of 89.5% compared to static CMOS implementation at a frequency of 125 MHz. Security of the proposed logic against the side channel power analysis attack is demonstrated by performing the correlation power analysis attacks as applicable for the SPICE simulations. Exhaustive SPICE simulations have been performed using the 32 nm CMOS predictive technology model libraries.

Temperature Controlled Voltage Regulated Boost Converter for Thermoelectric Energy Harvesting

Abstract: This paper presents a temperature controlled voltage regulated boost converter for running low power electronics using thermoelectric energy harvesting. The modulation of gate driver clock using di...

Low Power Contacless Voltage Sensor for IoT Applications

Abstract: Due to advances in the fields of low power electronics, computer science and communications, the diffusion of sensors based on the Internet of Things is more and more increasing. In particular, contactless sensing principles represent enabling technologies for the IoT. This paper presents a new contactless power line voltage sensor (from 0 V to 300 V) with low power consumption in order to be suitable for IoT applications. It has been characterized with a high performance electrical calibrator showing good accuracy (lower than 1 %) at 230 V.

Low-power low-data-rate IR-UWB transmitter for paediatric apnoea monitoring system

Abstract: Wireless telemetry has recently become a very important feature for healthcare monitoring and wearable systems. Several factors such as reliability, power budget, and cost impose design constraints for data transmission. Literature reported transmitters characterised by lower energy efficiency for low data rate operations and are not quite suitable for low-power biomedical applications. To overcome these constraints, this paper presents an impulse radio ultra-wideband (IR-UWB) transmitter that implements a heavy duty-cycling approach to achieve low power consumption. The transmitter is designed to be used for a non-invasive wireless respiration monitoring and apnoea detection system for premature infants. The transmitter is designed and fabricated in 130 nm standard CMOS process achieving 9.12 µW of power consumption and 91.2 pJ per pulse at 100 kbps data rate.

Hybrid interconnect network for on-chip low-power clock distribution

Abstract: Clock is regarded as the heartbeat of modern synchronous digital integrated circuits. However, with the CMOS technology shrinking, it becomes critical to deliver high-quality global clock signal with low propagation delay and hence conventional metallic interconnect seems to meet its bottleneck, as a clock distribution network (CDN) might consume up to 50% of the overall power. To address these problems, this Letter proposes a novel combination of wireless and conventional metallic interconnect to improve the performance of on-chip clock distribution. By incorporating integrated wireless clock transceivers and efficient modulation technique, overall performance has been increased significantly with a total delay reduction of 66.8% compared with a new cornerstone tapered H-tree model from 400 to 130 ps. In addition, clock uncertainties are now predictable according to the displacement of transceivers, <;33 ps of clock skew at 2.5 GHz input with highly unbalanced loads could be found within the proposed CDN, and hence, indicates a promising potential of future high-performance on-chip clock distribution.

qCG: A Low-Power Multi-Domain SFQ Logic Design and Verification Framework

Abstract: In this paper, we propose qCG, a multi-domain design and verification framework, which utilizes clock gating and frequency scaling to optimize dynamic power dissipation. SFQ circuits are ultra-deep pipelined at the logic level, resulting in large clock distribution networks which account for a considerable part of overall power dissipation. We have shown that qCG significantly increases power efficiency, not only for SFQ circuits, but also their clock networks and inherently cooling systems. The verification engine of qCG learns to increase the quality of results in terms of verification time and coverage. Datapath and coverage meters are embedded to verify the pulse integrity of clock signals, SFQ fanout, and path-balancing properties. Our experiments on several SFQ benchmark circuits show that qCG provides 3X power reductions for the chip. Results also confirm that when compared to a traditional random-based coverage-driven approach, qCG provides significant verification quality improvement including 2.33X verification speedup.

Low Power High Bandwidth Acceleration Sensor For Industrial Applications

Abstract: This paper reports on the improved micromechanical structures and improved integrated electronics to create high bandwidth acceleration sensors with a high signal to noise ratio and very low power electronics. This ambitious aim can be achieved by a very close co-design of MEMS and ASIC. Our two axis micromechanical element is optimized with respect to its seismic mass, which is needed to have an ultra-low noise sensor. Therefore, a large height of the micro mechanical structure is preferred. Another aim is a very high capacitive sensitivity while keeping the base capacitance as small as possible to aim for a small power consumption. Hence, a high aspect ratio technology is essential.

Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

Abstract: In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

Device-Circuit Co-Design Employing Phase Transition Materials for Low Power Electronics

Abstract: Phase transition materials (PTM) have garnered immense interest in concurrent post-CMOS electronics, due to their unique properties such as - electrically driven abrupt resistance switching, hysteresis, and high selectivity. The phase transitions can be attributed to diverse material-specific phenomena, including- correlated electrons, filamentary ion diffusion, and dimerization. In this research, we explore the application space for these materials through extensive device-circuit co-design and propose new ideas harnessing their unique electrical properties. The abrupt transitions and high selectivity of PTMs enable steep (< 60 mV/decade) switching characteristics in Hyper-FET, a promising post-CMOS transistor. We explore device-circuit co-design methodology for Hyper-FET and identify the criterion for material down-selection. We evaluate the achievable voltage swing, energy-delay trade-off, and noise response for this novel device. In addition to the application in low power logic device, PTMs can actively facilitate non-volatile memory design. We propose a PTM augmented Spin Transfer Torque (STT) MRAM that utilizes selective phase transitions to boost the sense margin and stability of stored data, simultaneously. We show that such selective transitions can also be used to improve other MRAM designs with separate read/write paths, avoiding the possibility of read-write conflicts. Further, we analyze the application of PTMs as selectors in cross-point memories. We establish a general simulation framework for cross-point memory array with PTM based selector. We explore the biasing constraints, develop detailed design methodology, and deduce figures of merit for PTM selectors. We also develop a computationally efficient compact model to estimate the leakage through the sneak paths in a cross-point array. Subsequently, we present a new sense amplifier design utilizing PTM, which offers built-in tunable reference with low power and area demand. Finally, we show that the hysteretic characteristics of unipolar PTMs can be utilized to achieve highly efficient rectification. We validate the idea by demonstrating significant design improvements in a Cockcroft-Walton Multiplier, implemented with TS based rectifiers. We emphasize the need to explore other PTMs with high endurance, thermal stability, and faster switching to enable many more innovative applications in the future.

A 200-pA Under-Voltage Lockout Circuit for Ultra-Low Power Applications

Abstract: A temperature compensated under voltage lockout (UVLO) circuit for ultra-low power applications is presented. The UVLO operation is achieved using two transistors with different threshold voltages and a source follower. The difference in the thresholds of the two transistors is used to create a reference voltage. As the supply voltage rises, the generated reference voltage tracks the supply till its designed voltage value and thereafter becomes a constant. This reference voltage is applied to a self-referenced common-source stage and is further amplified by CMOS inverters to arrive at a decision to lock out the supply or not. The designed UVLO consumes 200 pA of current at 1.8 V supply. The measured low-to-high trip points (LHTP) and high-to-low trip points (HLTP) are 1.28 V and 1.12 V with a variability of 208 ppm/°C and 200 ppm/°C respectively. These trip points are programmable from 1.1 V to 1.4 V in steps of 100 mV. The design occupies 0.00723 mm2 in standard 180 nm CMOS.