Topic

# Low voltage

About: Low voltage is a research topic. Over the lifetime, 40077 publications have been published within this topic receiving 361919 citations.

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TL;DR: By replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation.

Abstract: It is well-known that conventional field effect transistors (FETs) require a change in the channel potential of at least 60 mV at 300 K to effect a change in the current by a factor of 10, and this minimum subthreshold slope S puts a fundamental lower limit on the operating voltage and hence the power dissipation in standard FET-based switches. Here, we suggest that by replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation. The voltage transformer action can be understood intuitively as the result of an effective negative capacitance provided by the ferroelectric capacitor that arises from an internal positive feedback that in principle could be obtained from other microscopic mechanisms as well. Unlike other proposals to reduce S, this involves no change in the basic physics of the FET and thus does not affect its current drive or impose other restrictions.

1,722 citations

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TL;DR: In this article, a multithreshold-voltage CMOS (MTCMOS) based low-power digital circuit with 0.1-V power supply high-speed low power digital circuit technology was proposed, which has brought about logic gate characteristics of a 1.7ns propagation delay time and 0.3/spl mu/W/MHz/gate power dissipation with a standard load.

Abstract: 1-V power supply high-speed low-power digital circuit technology with 0.5-/spl mu/m multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both low-threshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-/spl mu/W/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-/spl mu/m CMOS process. >

1,338 citations

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TL;DR: In this article, a fully analytical MOS transistor model dedicated to the design and analysis of low-voltage, low-current analog circuits is presented, which exploits the inherent symmetry of the device by referring all the voltages to the local substrate.

Abstract: Afully analytical MOS transistor model dedicated to the design and analysis of low-voltage, low-current analog circuits is presented. All the large-and small-signal variables, namely the currents, the transconductances, the intrinsic capacitances, the non-quasi-static transadmittances and the thermal noise are continuous in all regions of operation, including weak inversion, moderate inversion, strong inversion, conduction and saturation. The same approach is used to derive all the equations of the model: the weak and strong inversion asymptotes are first derived, then the variables of interest are normalized and linked using an appropriate interpolation function. The model exploits the inherent symmetry of the device by referring all the voltages to the local substrate. It is shown that the inversion chargeQ inv is controlled by the voltage differenceV P — Vch whereV ch is the channel voltage, defined as the difference between the quasi-Fermi potentials of the carriers. The pinch-off voltageV P is defined as the particular value of Vch, such that the inversion charge is zero for a given gate voltage. It depends only on the gate voltage and can be interpreted as the equivalent effect of the gate voltage referred to the channel. The various modes of operation of the transistor are then presented in terms of voltagesV P —V S andV P —V D Using the charge sheet model with the assumption of constant doping in the channel, the drain currentIDis derived and expressed as the difference between a forward componentI F and a reverse componentI R. Each of these is proportional to a function ofV P —V S respectivelyV P —V D through a specific currentI S This function is exponential in weak inversion and quadratic in strong inversion. The current in the moderate inversion region is then modelled by using an appropriate interpolation function resulting in a continuous expression valid from weak to strong inversion. A quasi-static small-signal model including the transconductances and the intrinsic capacitances is obtained from an accurate evaluation of the total charges stored on the gate and in the channel. The transconductances and the intrinsic capacitances are modelled in moderate inversion using the same interpolation function and without any additional parameters. This small-signal model is then extended to higher frequencies by replacing the transconductances by first order transadmittances obtained from a non-quasi-static calculation. All these transadmittances have the same characteristic time constant which depends on the bias condition in a continuous manner. To complete the model, a general expression for the thermal noise valid in all regions of operation is derived. This model has been successfully implemented in several computer simulation programs and has only 9 physical parameters, 3 fine tuning fitting coefficients and 2 additional temperature parameters.

1,244 citations

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TL;DR: In this paper, the distribution function for the current noise in Quantum point contacts is discussed and a new derivation of the Lesovik-Levitov formulae is suggested.

Abstract: We discuss the distribution function for the current noise in Quantum point contacts. Special interest is paid to contact of a superconductor with a normal metal. A new derivation of the Lesovik-Levitov formulae is suggested. It is shown, for the SN point contacts, that the distribution of the noise describes independent processes when charge ±e 0 or ±2e 0 passes through the contact. At low temperature and voltage only processes with double charge transfer are relevant. At zero temperature and low voltage the distribution has a binomial form.

1,174 citations

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TL;DR: A general conceptual circuit for high-step-up, low-cost, and high-efficiency dc/dc conversion is proposed to derive the next-generation topologies for the PV grid-connected power system.

Abstract: The photovoltaic (PV) grid-connected power system in the residential applications is becoming a fast growing segment in the PV market due to the shortage of the fossil fuel energy and the great environmental pollution. A new research trend in the residential generation system is to employ the PV parallel-connected configuration rather than the series-connected configuration to satisfy the safety requirements and to make full use of the PV generated power. How to achieve high-step-up, low-cost, and high-efficiency dc/dc conversion is the major consideration due to the low PV output voltage with the parallel-connected structure. The limitations of the conventional boost converters in these applications are analyzed. Then, most of the topologies with high-step-up, low-cost, and high-efficiency performance are covered and classified into several categories. The advantages and disadvantages of these converters are discussed. Furthermore, a general conceptual circuit for high-step-up, low-cost, and high-efficiency dc/dc conversion is proposed to derive the next-generation topologies for the PV grid-connected power system. Finally, the major challenges of high-step-up, low-cost, and high-efficiency dc/dc converters are summarized. This paper would like to make a clear picture on the general law and framework for the next-generation nonisolated high-step-up dc/dc converters.

1,162 citations