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Magnetoresistive random-access memory

About: Magnetoresistive random-access memory is a research topic. Over the lifetime, 2842 publications have been published within this topic receiving 61005 citations.


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Journal ArticleDOI
TL;DR: A giant MR ratio up to 180% at room temperature in single-crystal Fe/MgO/Fe MTJs is reported, indicating that coherency of wave functions is conserved across the tunnel barrier.
Abstract: The tunnel magnetoresistance (TMR) effect in magnetic tunnel junctions (MTJs)1,2 is the key to developing magnetoresistive random-access-memory (MRAM), magnetic sensors and novel programmable logic devices3,4,5. Conventional MTJs with an amorphous aluminium oxide tunnel barrier, which have been extensively studied for device applications, exhibit a magnetoresistance ratio up to 70% at room temperature6. This low magnetoresistance seriously limits the feasibility of spintronics devices. Here, we report a giant MR ratio up to 180% at room temperature in single-crystal Fe/MgO/Fe MTJs. The origin of this enormous TMR effect is coherent spin-polarized tunnelling, where the symmetry of electron wave functions plays an important role. Moreover, we observed that their tunnel magnetoresistance oscillates as a function of tunnel barrier thickness, indicating that coherency of wave functions is conserved across the tunnel barrier. The coherent TMR effect is a key to making spintronic devices with novel quantum-mechanical functions, and to developing gigabit-scale MRAM.

2,956 citations

Journal ArticleDOI
TL;DR: NVSim is developed, a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash and is expected to help boost architecture-level NVM-related studies.
Abstract: Various new nonvolatile memory (NVM) technologies have emerged recently. Among all the investigated new NVM candidate technologies, spin-torque-transfer memory (STT-RAM, or MRAM), phase-change random-access memory (PCRAM), and resistive random-access memory (ReRAM) are regarded as the most promising candidates. As the ultimate goal of this NVM research is to deploy them into multiple levels in the memory hierarchy, it is necessary to explore the wide NVM design space and find the proper implementation at different memory hierarchy levels from highly latency-optimized caches to highly density- optimized secondary storage. While abundant tools are available as SRAM/DRAM design assistants, similar tools for NVM designs are currently missing. Thus, in this paper, we develop NVSim, a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies.

1,100 citations

Proceedings ArticleDOI
05 Dec 2005
TL;DR: In this article, a spin torque transfer magnetization switching (STS) based nonvolatile memory called spin-RAM was presented for the first time, which is based on magnetization reversal through an interaction of a spin momentum-torque-transferred current and a magnetic moment of memory layers in magnetic tunnel junctions (MTJ).
Abstract: A novel nonvolatile memory utilizing spin torque transfer magnetization switching (STS), abbreviated spin-RAM hereafter, is presented for the first time The spin-RAM is programmed by magnetization reversal through an interaction of a spin momentum-torque-transferred current and a magnetic moment of memory layers in magnetic tunnel junctions (MTJs), and therefore an external magnetic field is unnecessary as that for a conventional MRAM This new programming mode has been accomplished owing to our tailored MTJ, which has an oval shape of 100 times 150 nm The memory cell is based on a 1-transistor and a 1-MTJ (ITU) structure The 4kbit spin-RAM was fabricated on a 4 level metal, 018 mum CMOS process In this work, writing speed as high as 2 ns, and a write current as low as 200 muA were successfully demonstrated It has been proved that spin-RAM possesses outstanding characteristics such as high speed, low power and high scalability for the next generation universal memory

961 citations

Journal ArticleDOI
TL;DR: This work shows that films of La (0.1)Bi(0.9)MnO(3) (LBMO) are ferromagnetic and ferroelectric, and retain both ferroic properties down to a thickness of 2 nm, and represents an advance over the original four-state memory concept based on multiferroics.
Abstract: Multiferroics are singular materials that can exhibit simultaneously electric and magnetic orders. Some are ferroelectric and ferromagnetic and provide the opportunity to encode information in electric polarization and magnetization to obtain four logic states. However, such materials are rare and schemes allowing a simple electrical readout of these states have not been demonstrated in the same device. Here, we show that films of La0.1Bi0.9MnO3 (LBMO) are ferromagnetic and ferroelectric, and retain both ferroic properties down to a thickness of 2 nm. We have integrated such ultrathin multiferroic films as barriers in spin-filter-type tunnel junctions that exploit the magnetic and ferroelectric degrees of freedom of LBMO. Whereas ferromagnetism permits read operations reminiscent of magnetic random access memories (MRAM), the electrical switching evokes a ferroelectric RAM write operation. Significantly, our device does not require the destructive ferroelectric readout, and therefore represents an advance over the original four-state memory concept based on multiferroics.

958 citations

Journal ArticleDOI
TL;DR: The state of microprocessors and DRAMs today is reviewed, some of the opportunities and challenges for IRAMs are explored, and performance and energy efficiency of three IRAM designs are estimated.
Abstract: Two trends call into question the current practice of fabricating microprocessors and DRAMs as different chips on different fabrication lines. The gap between processor and DRAM speed is growing at 50% per year; and the size and organization of memory on a single DRAM chip is becoming awkward to use, yet size is growing at 60% per year. Intelligent RAM, or IRAM, merges processing and memory into a single chip to lower memory latency, increase memory bandwidth, and improve energy efficiency. It also allows more flexible selection of memory size and organization, and promises savings in board area. This article reviews the state of microprocessors and DRAMs today, explores some of the opportunities and challenges for IRAMs, and finally estimates performance and energy efficiency of three IRAM designs.

671 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023125
2022230
202197
2020150
2019162
2018154