Showing papers on "Mask inspection published in 2009"

Experimental result and simulation analysis for the use of pixelated illumination from source mask optimization for 22nm logic lithography process

Abstract: We demonstrate experimentally for the first time the feasibility of applying SMO technology using pixelated illumination. Wafer images of SRAM contact holes were obtained to confirm the feasibility of using SMO for 22nm node lithography. There are still challenges in other areas of SMO integration such as mask build, mask inspection and repair, process modeling, full chip design issues and pixelated illumination, which is the emphasis in this paper. In this first attempt we successfully designed a manufacturable pixelated source and had it fabricated and installed in an exposure tool. The printing result is satisfactory, although there are still some deviations of the wafer image from simulation prediction. Further experiment and modeling of the impact of errors in source design and manufacturing will proceed in more detail. We believe that by tightening all kind of specification and optimizing all procedures will make pixelated illumination a viable technology for 22nm or beyond. Publisher's Note: The author listing for this paper has been updated to include Carsten Russ. The PDF has been updated to reflect this change.

Mask defect auto disposition based on aerial image in mask product

Abstract: At the most advanced technology nodes, such as 45nm and below, aggressive OPC and Sub-Resolution Assist Features (SRAFs) are required. However, their use results in significantly increased mask complexity, making mask defect disposition more challenging than ever. In an attempt to mitigate such difficulties, new mask inspection technologies that rely on hardware emulation and software simulation to obtain aerial image at the wafer plane have been developed; however, automatic mask disposition based on aerial image is still problematic because aerial image does not give the final resist CD or contour, which are commonly used in lithography verification on post OPC masks. In this paper, an automated mask defect disposition system that remedies these shortcomings is described. The system, currently in use for mask production, works in both die-to-die and die-to-database modes, and can operate on aerial images from both AIMSTM and aerial-image-based inline mask inspection tools. The disposition criteria are primarily based on waferplane CD variance. The system also connects to a post-OPC lithography verification tool that can provide gauges and CD specs, which are then used in the mask defect disposition.

Investigation of EUV mask defectivity via full-field printing and inspection on wafer

Abstract: Full-field printing on the ASML Alpha Demo Tool, followed by wafer inspection on a KLA-T 2800, is used to qualify typical defectivity levels of EUV reticles. Mask defects are found as repeaters among multiple dies on wafer. The uniform pattern consists of dense lines and spaces. In a first reticle with 40nm linewidth, high levels of natural defects have been found of which a relatively large share was considered as multilayer (ML) type defects, because they printed as rings. Simulation of ML defects could explain this printing behavior as a function of height, size and slope. The main parameter determining the printing behavior of a ML defect is its height. A local distortion of the upper part of the ML, as thin as ~2nm can already print. On-reticle analysis of the ring defects by SEM showed that the defects are present on the absorber, which already explains the printing result. Yet, still several other defects were found to print on the wafer, whereas they were not visible on the reticle and considered local distortions of the ML. Printing results with a second version of the mask that additionally includes programmed multilayer defects with 3nm height confirmed the pronounced printing impact of ML defects as they were simulated. Encouragingly low numbers of natural defects have been found on a third reticle. With this reticle also a first correlation has become possible between the defect maps obtained from wafer inspection, (direct) mask inspection, and blank inspection. This is a viable method to highlight potential gaps between the capability of these tools and printability of defects.

Improving the performance of the actinic inspection tool with an optimized alignment procedure

Abstract: Extreme ultraviolet (EUV) microscopy is an important tool for the investigation of the performance of EUV masks, for detecting the presence and the characteristics of defects, and for evaluating the effectiveness of defect repair techniques. Aerial image measurement bypasses the difficulties inherent to photoresist imaging and enables high data collection speed and flexibility. It provides reliable and quick feedback for the development of masks and lithography system modeling methods. We operate the SEMATECH Berkeley Actinic Inspection Tool (AIT), a EUV microscope installed at the Advanced Light Source at Lawrence Berkeley National Laboratory. The AIT is equipped with several high-magnification Fresnel zoneplate lenses, with various numerical aperture values, that enable it image the reflective mask surface with various resolution and magnification settings. Although the AIT has undergone significant recent improvements in terms of imaging resolution and illumination uniformity, there is still room for improvement. In the AIT, an off-axis zoneplate lens collects the light coming from the sample and an image of the sample is projected onto an EUV-sensitive CCD camera. The simplicity of the optical system is particularly helpful considering that the AIT alignment has to be performed every time that a sample or a zoneplate is replaced. The alignment is sensitive to several parameters such as the lens position and orientation, the illumination direction and the sample characteristics. Since the AIT works in high vacuum, there is no direct access to the optics or to the sample during the alignment and the measurements. For all these reasons the alignment procedures and feedback can be complex, and in some cases can reduce the overall data throughput of the system. In this paper we review the main strategies and procedures that have been developed for quick and reliable alignments, and we describe the performance improvements we have achieved, in terms of aberration magnitude reduction.

EUV Mask Inspection System

Abstract: Disclosed are apparatuses, methods, and lithographic systems for EUV mask inspection. An EUV mask inspection system can include an EUV illumination source, an optical system, and an image sensor. The EUV illumination source can be a standalone illumination system or integrated into the lithographic system, where the EUV illumination source can be configured to illuminate an EUV radiation beam onto a target portion of a mask. The optical system can be configured to receive at least a portion of a reflected EUV radiation beam from the target portion of the mask. Further, the image sensor can be configured to detect an aerial image corresponding to the portion of the reflected EUV radiation beam. The EUV mask inspection system can also include a data analysis device configured to analyze the aerial image for mask defects.

Study of Critical Dimensions of Printable Phase Defects Using an Extreme Ultraviolet Microscope

Abstract: We constructed an extreme ultraviolet microscopy (EUVM) system for actinic mask inspection that consists of Schwarzschild optics and an X-ray zooming tube. This system was used to inspect completed extreme ultraviolet lithography (EUVL) masks and Mo/Si coated substrates on ultralow expansion (ULE) glass. We also have fabricated programmed phase defects on the blanks used for inspection. The EUVM system was capable of resolving a programmed line-pit defect with a width of 40 nm and a depth of 10 nm and also that with a width of 70 nm and a depth of 2 nm. However, a 75-nm-wide, 1.5-nm-deep pit defect was not resolved. The EUVM system was also capable of resolving programmed hole-pit defects with widths ranging from 35 to 170 nm and depths ranging from 2.2 to 2.5 nm. However, 20-nm-wide, 1.5-nm-deep hole-pit defects were not resolved. These results agree with the simulation results perfectly. Thus, in this study, critical dimensions of a pit defects on mask blanks were determined to be a width of 20 nm and a depth of 2 nm.

EUV pattern defect detection sensitivity based on aerial image linewidth measurements

Abstract: As the quality of EUV-wavelength mask inspection microscopes improves over time, the image properties and intensity profiles of reflected light can be evaluated in ever-greater detail. The SEMATECH Berkeley Actinic Inspection Tool (AIT) is one such microscope, featuring mask resolution values that match or exceed those available through lithographic printing in current photoresists. In order to evaluate the defect detection sensitivity of the AIT for dense line patterns on typical masks, the authors study the linewidth roughness (LWR) on two masks, as measured in the EUV images. They report the through-focus and pitch dependence of contrast, image log slope, linewidth, and LWR. The AIT currently reaches LWR 3σ values close to 9nm for 175nm half-pitch lines. This value is below 10% linewidth for nearly all lines routinely measured in the AIT. Evidence suggests that this lower level may arise from the mask’s inherent pattern roughness. While the sensitivity limit of the AIT has not yet been established, it ...

Study of EUVL mask defect inspection using 199-nm inspection tool with super-resolution method

Abstract: In this paper, we will report on our experimental results on the impact of inspection system optics on mask defect detection sensitivity. We evaluated the capability of detecting defects on the EUVL masks by using a new inspection tool (NPI6000EUVα) made by NuFlare Technology, Inc. (NFT) and Advanced Mask Inspection Technology, Inc. (AMiT). This tool is based on NPI-5000 which is the leading-edge photomask defect inspection system using 199nm wavelength inspection optics. The programmed defect mask with LR-TaBN absorber was used which had various sized opaque and clear extension defects on hp-180nm, hp-128nm, and hp-108nm line and space patterns. According to the analysis, to obtain optimum sensitivity for various types of defects, using both C- and P-polarized illumination conditions were found to be effective. At present, sufficient defect-detection sensitivity is achieved for opaque and clear extension defects in hp128nm (hp32nm at wafer). For hp108nm (hp27nm at wafer), using both C- and P- polarized illumination is effective. However, further developments in defect-detection sensitivity are necessary.

Optical display device manufacturing system and optical display device manufacturing method

Abstract: Provided are an optical display device manufacturing system and an optical display device manufacturing method which can more preferably carry out a defect inspection. A detection condition of a defect in the inspection of an optical film before being bonded to an optical display unit carried out by a defect inspection apparatus (14, 24) is corrected based on the result of inspection of the optical display device with the optical film bonded, carried out by an inspection apparatus (30), and the optical film including the defects detected by the defect inspection apparatuses (14, 24) based on the corrected detection condition are excluded. Accordingly, since it is possible to adjust the standard of the defect inspection carried out by the defect inspection apparatus (14, 24) in conformity to the standard of the defect inspection which is later carried out by the inspection apparatus (30), it is possible to more preferably carry out the defect inspection, and it is possible to improve a yield ratio of the optical film.

Mask Pattern Recovery by Level Set Method based Inverse Inspection Technology (IIT) and its Application on Defect Auto Disposition

Abstract: At the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features (SRAFs) are required. However, their use results in significantly increased mask complexity, making mask defect disposition more challenging than ever. This paper describes how mask patterns can first be recovered from the inspection images by applying patented algorithms using Level Set Methods. The mask pattern recovery step is then followed by aerial/wafer image simulation, the results of which can be plugged into an automated mask defect disposition system based on aerial/wafer image. The disposition criteria are primarily based on wafer-plane CD variance. The system also connects to a post-OPC lithography verification tool that can provide gauges and CD specs, thereby enabling them to be used in mask defect disposition as well. Results on both programmed defects and production defects collected at Samsung mask shop are presented to show the accuracy and consistency of using the Level Set Methods and aerial/wafer image based automated mask disposition.

Mask defect verification using actinic inspection and defect mitigation technology - eScholarship

Abstract: Mask Defect Verification Using Actinic Inspection and Defect Mitigation Technology Sungmin Huh 1, Patrick Kearney1, Stefan Wurm 1, Frank Goodwin 1, Kenneth Goldberg2, Iacopo Mochi2, Eric GuIIikson 2 1SEMATECH 255 Fuller Road, Suite 309, Albany, NY 12203 USA 2 2-400, Lawrence Berkeley National Laboratory, Berkeley, CA 94720 ABSTRACT The availability of defect-free masks remains one of the key challenges for inserting extreme ultraviolet lithography (EUVL) into high volume manufacturing. The successful production of defect-free masks will depend on the timely development of defect inspection tools, including both mask blank inspection tools and absorber pattern inspection tools to meet the 22 nm half-pitch node. EUV mask blanks with embedded phase defects were inspected with a reticle actinic inspection tool (AIT) and the Lasertec M7360. The Lasertec M7360 is operated at SEMA TECH's Mask blank Development Center (MBDC) in Albany, with sensitivity to multilayer defects down to 40-45 nm, which is not likely sufficient for mask blank development below the 32 nm half-pitch node. Phase defect printability was simulated to calculate the required defect sensitivity for the next generation blank inspection tool to support reticle development for the sub-32 nm half-pitch technology node. This paper will also discuss the kind of infrastructure that will be required in the development and mass production stages. Keywords: EUV, mask, phase defect, DUV inspection, actinic inspection 1. INTRODUCTION Over the past year, the interest by leading edge chip manufacturers has tangibly shifted towards the insertion of extreme ultraviolet lithography (EUVL) into production. This emphasis is increasing the pressure to overcome the lack of defect- free blanks, which remains one of the key challenges impeding the insertion of EUVL into manufacturing. The success of the industry'S mask blank defect reduction effort critically depends on the timely availability of inspection tools that can precisely and reliably find ever smaller defects. SEMA TECH's Mask Blank Development Center (MBDC) facility has provided the world's best defect inspection capability starting in 2003 with the Lasertech M1350 tool, followed by the second generation defect inspection tool, the M7360, in 2006. Both tools use deep ultraviolet (DUV) light sources for defect detection: the 488 nm wavelength for the M1350 and 266 nm wavelength for the M7360. However, to meet high volume manufacturing (HVM) requirements for sub-32 nm half-pitch (HP) patterning, the industry needs a third generation of defect inspection tools capable of finding defects :s: 20 nm on mask blanks with a high capture rate and high blank throughput. In addition, these tools will also need to support extendibility assessments of low defect deposition technologies and the associated infrastructure development towards meeting 22 nm HP defect specifications. SEl\1A TECH operates the actinic inspection tool (AIT) at Lawrence Berkeley National Lab (LBNL) and a state of the art Lasertec M7360 to support the development of inspection tools and reticle blanks to eventually meet HVM requirements. In this paper, we simulated the required defect sensitivity for sub-32 nm HP [1-3] and have prepared an EUV mask blank, fabricated in SEMATECH's MBDC, to be inspected using the M7360 in the MBDC and the AIT at LBNL to compare the sensitivity of these tools. We prepared a mask blank with a real phase defect and then compared the detected image using the M7360 and AIT to explain why we need an actinic inspection tool for the mass production of EUV mask blanks. Most of the cost of ownership (COO) of EUV masks depends on the defect-free mask blank cost. Consequently, defect mitigation technology using mask blanks with some phase defects should be developed to reduce mask blankcosts during mass production. In this paper, we identif)' what is needed for defect mitigation technology and propose possible defect inspection scheme for EUV pilot line applications [4].

Novel EUV mask inspection tool with 199-nm laser source and high-resolution optics

Abstract: A novel EUV mask inspection tool with 199nm laser source and super-resolution technique has been developed. This tool is based on NPI-5000PLUS, which is a photo-mask inspection tool for hp2X nm node and beyond. In order to implement EUV mask inspection with only a short time for mask set-up, reflected illumination type alignment optics to guide alignment mark and adjust mask coordinate with visible illumination light are equipped. Moreover, to inspect EUV masks for hp2X nm and beyond, the image detection optics with the novel polarized illumination technique is incorporated in this tool. Image contrast enhancement was confirmed by experiments and simulations.

Simulation based mask defect repair verification and disposition

Abstract: As the industry moves towards sub-65nm technology nodes, the mask inspection, with increased sensitivity and shrinking critical defect size, catches more and more nuisance and false defects. Increased defect counts pose great challenges in the post inspection defect classification and disposition: which defect is real defect, and among the real defects, which defect should be repaired and how to verify the post-repair defects. In this paper, we address the challenges in mask defect verification and disposition, in particular, in post repair defect verification by an efficient methodology, using SEM mask defect images, and optical inspection mask defects images (only for verification of phase and transmission related defects). We will demonstrate the flow using programmed mask defects in sub-65nm technology node design. In total 20 types of defects were designed including defects found in typical real circuit environments with 30 different sizes designed for each type. The SEM image was taken for each programmed defect after the test mask was made. Selected defects were repaired and SEM images from the test mask were taken again. Wafers were printed with the test mask before and after repair as defect printability references. A software tool SMDD-Simulation based Mask Defect Disposition-has been used in this study. The software is used to extract edges from the mask SEM images and convert them into polygons to save in GDSII format. Then, the converted polygons from the SEM images were filled with the correct tone to form mask patterns and were merged back into the original GDSII design file. This merge is for the purpose of contour simulation-since normally the SEM images cover only small area (~1 μm) and accurate simulation requires including larger area of optical proximity effect. With lithography process model, the resist contour of area of interest (AOI-the area surrounding a mask defect) can be simulated. If such complicated model is not available, a simple optical model can be used to get simulated aerial image intensity in the AOI. With built-in contour analysis functions, the SMDD software can easily compare the contour (or intensity) differences between defect pattern and normal pattern. With user provided judging criteria, this software can be easily disposition the defect based on contour comparison. In addition, process sensitivity properties, like MEEF and NILS, can be readily obtained in the AOI with a lithography model, which will make mask defect disposition criteria more intelligent.

Mask inspection apparatus, and exposure method and mask inspection method using the same

Abstract: The present invention provides a mask inspection apparatus and method capable of inspecting masks used in double patterning with satisfactory accuracy. Optical images of two masks are acquired (S 100 ). The acquired optical images of the two masks are combined together (S 102 ). Relative positional displacement amounts of patterns of the first mask and patterns of the second mask are measured at the combined image (S 104 ). The measured relative positional displacement amounts are compared with standard values to thereby determine whether the two masks are good (S 106 ).

Mask inspection apparatus and mask inspection method

Abstract: The present invention provides a mask inspection apparatus and method capable of eliminating distortion of each optical image, which is caused by distortions of mirrors and flexure of a mask, and performing a mask inspection with satisfactory accuracy. A stage with the mask held thereon is moved in X and Y directions and an optical image of each pattern written onto the mask is acquired while using the results of measurement by laser interferometers (Step S 100 ). A positional displacement of the acquired optical image is corrected using polynomial equations in which pre-measured amounts of positional displacement of optical images have been fitted (Step S 102 ). Each positional displacement that remains after the polynomial correction is corrected using a map descriptive of pre-measured amounts of positional displacements (S 104 ). Each optical image subsequent to the map correction and a reference image are compared (Step S 108 ).

Photomask inspection method, semiconductor device inspection method, and pattern inspection apparatus

Abstract: A plurality of photomasks used to manufacture the same semiconductor device, each of the photomasks having a plurality of mutually replaceable unit regions set therein, are inspected to detect a defect. It is determined whether or not the detected defect has a redundancy defect positioned in a unit region replaceable with another unit region to remedy the photomask. Then, when inspecting the second or subsequent photomask, a unit region including the coordinate of a redundancy defect detected in another photomask inspected previously is set to be a non-inspection region, and the non-inspection region is not inspected.

Mask defect verification using actinic inspection and defect mitigation technology

Abstract: The availability of defect-free masks remains one of the key challenges for inserting extreme ultraviolet lithography (EUVL) into high volume manufacturing. The successful production of defect-free masks will depend on the timely development of defect inspection tools, including both mask blank inspection tools and absorber pattern inspection tools to meet the 22 nm half-pitch node. EUV mask blanks with embedded phase defects were inspected with a reticle actinic inspection tool (AIT) and the Lasertec M7360. The Lasertec M7360 is operated at SEMA TECH's Mask blank Development Center (MBDC) in Albany, with sensitivity to multilayer defects down to 40-45 nm, which is not likely sufficient for mask blank development below the 32 nm half-pitch node. Phase defect printability was simulated to calculate the required defect sensitivity for the next generation blank inspection tool to support reticle development for the sub-32 nm half-pitch technology node. This paper will also discuss the kind of infrastructure that will be required in the development and mass production stages.

Euv mask inspection.

Abstract: A system for inspecting an extreme ultra violet (EUV) mask. The system includes an array of sensors and an optical system. The array of sensors is configured to produce analog data corresponding to received optical energy. The optical system is configured to direct EUV light from an inspection area of an EUV patterning device onto the array of sensors, whereby the analog data is used to determine defects or to compensate for irregularities found on the EUV mask.

Mask fabrication method, exposure method, device fabrication method, and recording medium

Abstract: The present invention provides a method including generating mask data to be used in an exposure apparatus including an illumination optical system and a projection optical system which projects a pattern of the mask onto a substrate, and fabricating a mask based on the generated mask data.

Microscope for reticle inspection with variable illumination settings

Abstract: During mask inspection predominantly defects of interest which also occur during wafer exposure. Therefore, the aerial images generated in the resist and on the detector have to be as far as possible identical. In order to achieve an equivalent image generation, during mask inspection the illumination and, on the object side, the numerical aperture are adapted to the scanner used. A further form of mask inspection microscopes serves for measuring the reticles and is also referred to as a registration tool. The illumination is used by the stated conventional and abaxial illumination settings for optimizing the contrast. The accuracy of the registration measurement is thus increased. The invention relates to a mask inspection microscope for variably setting the illumination. It serves for generating an image of the structure (150) of a reticle (145) arranged in an object plane in a field plane of the mask inspection microscope. It comprises a light source (5) that emits projection light, at least one illumination beam path (3, 87, 88), and a first diaphragm for generating a resultant intensity distribution of the projection light in a pupil plane (135) of the illumination beam path (3, 87, 88), that is optically conjugate with respect to the object plane. According to the invention, the mask inspection microscope has at least one further diaphragm for generating the resultant intensity distribution. The first diaphragm and the at least one further diaphragm influence the resultant intensity distribution of the projection light at least partly at different locations of the pupil plane (135).

Using metrology capabilities of mask inspection equipment for optimizing total lithography performance

Abstract: The demand for aggressive image placement accuracy and CD uniformity for each generation is being increasingly accelerated by DPT deployment. The method of the correction with the scanner is in effect devised by obtaining the CD and IP maps of each mask after the mask pattern is drawn. We are developing a technology that generates CD and IP maps for each mask from the image data of inspection equipment with the ultimate goal of "in-die overlay improvement" optimizing scanner as well as writer performances. We evaluated the positional measurement function by using NPI inspection system with the evaluation mask.

Aerial imaging for source mask optimization: mask and illumination qualification

Abstract: As the semiconductor industry moved to 4X technology nodes and below, low-k 1 ArF lithography approached the theoretical limits of single patterning resolution, a regime typically plagued by marginally small process windows. In order to widen the process window bottleneck, projection lithography must fully and synergistically employ all available degrees of freedom. The holistic lithography source mask optimization (SMO) methodology aims to increase the overall litho performance and achieve a robust process window for the most challenging patterns by balancing between the mask and illumination source design influences. The typical complexity of both mask and illumination source that results from a generic SMO process exceeds the current norm in the lithographic industry. In particular, the SMO literature reports on masks that fully operate as diffractive optical elements, with features that have little resemblance to the final wafer-level pattern. Additionally, SMO illumination sources are characterized by parametric or pixelated shapes and a wide range of transmission values. As a consequence of the new mask and source designs, qualifying the mask for printing and non-printing defects and accurate assessment of critical dimensions becomes one of the main mask inspection challenges. The aerial imaging technologies of Applied Material’s Aera2™ mask inspection tool provide enabling solutions by separating out only the defects that matter and accurately measures aerial imaging critical dimensions. This paper presents the latest numerical and experimental SMO mask qual ifications research results performed at Applied Materials with a mask containing two-dimensional DRAM production structures. Key words: Inspection, Mask, Reticle, Source-Mask Optimization, Logic, Memory

Implementation strategy of wafer-plane and aerial-plane inspection for advanced mask manufacture

Abstract: Inspection of aggressive Optical Proximity Correction (OPC) designs, improvement of usable sensitivity, and reduction of cost of ownership are the three major challenges for today's mask inspection methodologies. In this paper we will discuss using aerial-plane inspection and wafer-plane inspection as novel approaches to address these challenges for advanced reticles. Wafer-plane inspection (WPI) and aerial-plane inspection (API) are two lithographic inspection modes. This suite of new inspection modes is based on high resolution reflected and transmitted light images in the reticle plane. These images together with scanner parameters are used to generate the aerial plane image using either vector or scalar models. Then information about the resist is applied to complete construction of the wafer plane image. API reports defects based on intensity differences between test and reference images at the aerial plane, whereas WPI applies a resist model to the aerial image to enhance discrimination between printable and non-printable defects at the wafer plane. The combination of WPI and API along with the industry standard Reticle Plane Inspection (RPI) is designed to handle complex OPC features, improve usable sensitivity and reduce the cost of ownership. This paper will explore the application of aerial-plane and wafer-plane die-to-die inspections on advanced reticles. Inspection sensitivity, inspectability, and comparison with Aerial Imaging Measurement System (AIMSTM[1]) or wafer-print-line will be analyzed. Most importantly, the implementation strategy of a combination of WPI and API along with RPI leading-edge mask manufacturing will be discussed.

SMO photomask inspection in the lithographic plane

Abstract: Source Mask Optimization (SMO) describes the co-optimization of the illumination source and mask pattern in the frequency domain. While some restrictions for manufacturable sources and masks are included in the process, the resulting photomasks do not resemble the initial designs. Some common features of SMO masks are that the line edges are heavily fragmented, the minimum design features are small and there is no one-to-one correspondence between design and mask features. When it is not possible to link a single mask feature directly to its resist counterpart, traditional concepts of mask defects no longer apply and photomask inspection emerges as a significant challenge. Aerial Plane Inspection (API) is a lithographic inspection mode that moves the detection of defects to the lithographic plane. They can be deployed to study the lithographic impact of SMO mask defects. This paper briefly reviews SMO and the lithography inspection technologies and explores their applicability to 22nm designs by presenting SMO mask inspection results. These results are compared to simulated wafer print expectations.

Fine pattern fabrication property of Binary Mask and Attenuated Phase Shift Mask

Abstract: For 45nm and 32nm node technology, the challenges for resolution and CD control of mask patterns become the steeper mountain path. Especially, Sub Resolution Assist Feature (SRAF) is the smallest pattern on mask and amplifies the difficulty of mask fabrication. In order to improve the resolution of fine patterns, the influence of wet processing cannot be neglected, because it causes the pattern collapsing. Wet processing of mask-making can be divided into resist development and cleaning. In this study, the root causes of pattern collapsing are investigated at each wet processing. It is confirmed that thin resist can enhance the resolution limit of resist pattern and hard-mask blank, such as OMOG: Opaque MoSi On Glass, is suitable for thinner resist under 1500A. The pattern collapsing of OMOG is compared with that of Att.PSM at the cleaning before and after Cr stripping. Mask inspection finds that pattern collapsing can be suppressed by OMOG at both cleanings. It is because OMOG has lower cleaning stress than Att.PSM due to lower aspect-ratio. This benefit is demonstrated by cleaning stress simulation. Additionally, it is found that the SRAF size of OMOG can be wider than Att.PSM by optical simulation. From these results, OMOG has much advantage of fine pattern fabrication and is the optimal blank for 32nm node and beyond.

Defect printability analysis by lithographic simulation from high resolution mask images

Abstract: We report the development of Mask-LMC for defect printability evaluation from sub-200nm wavelength mask inspection images. Both transmitted and reflected images are utilized, and both die-to-die and die-to-database inspection modes are supported. The first step of the process is to recover the patterns on the mask from high resolution T and R images by de-convolving inspection optical effects. This step uses a mask reconstruction model, which is based on rigorous Hopkins-modeling of the inspection optics, and is pre-determined before the full mask inspection. After mask reconstruction, wafer scanner optics and wafer resist simulations are performed on the reconstructed mask, with a wafer lithography model. This step leverages Brion's industry-proven, hardware-accelerated LMC (Lithography Manufacturability Check) technology1. Existing litho process models that are in use for Brion's OPC+ and verification products may be used for this simulation. In the final step, special detectors are used to compare simulation results on the reference and defect dice. We have developed detectors for contact CD, contact area, line and space CD, and edge placement errors. The detection results on test and production reticles have been validated with AIMS TM .

Printability verification function of mask inspection system

Abstract: In addition to the conventional demands for high sensitivities with which the mask inspection system detects the minute size defects, capability to extract true defects from a wide variety of patterns that should not be counted as pseudo defects has been quite demanding. It is necessary to ascertain suppression of MEEF incurred by the combination of parameters such as LER and defects of SRAF. NFT and Brion are jointly developing a mask-image based printability verification system with functions combining their respective technologies with the results from ASET's research. This report describes such defect detection results and introduces the development of a mask inspection system with printability verification function.

Mask-LMC: lithographic simulation and defect detection from high-resolution mask images

Abstract: We report the development of Mask-LMC for defect printability evaluation from sub-200nm wavelength mask inspection images. Both transmitted and reflected images are utilized, and both die-to-die and die-to-database inspection modes are supported. The first step of the process is to recover the patterns on the mask from high resolution T and R images by de-convolving inspection optical effects. This step uses a mask reconstruction model, which is based on rigorous Hopkins-modeling of the inspection optics, and is pr e-determined before the full mask inspection. After mask reconstruction, wafer scanner optics and wafer resist simulati ons are performed on the reconstructed mask, with a wafer lithography model. This step leverages Brion’s indu stry-proven, hardware-accel erated LMC (Lithography Manufacturability Check) technology 1 . Existing litho process models that are in use for Brion’s OPC+ and verification products may be used for this simulation. In the final step, special detectors are used to compare simulation results on the reference and defect dice. We have developed detectors for contact CD, c ontact area, line and space CD, and edge placement errors. The detection resu lt has been validated with AIMS

A study of mask inspection method with pattern priority and printability check

Abstract: The cost of mask is increasing dramatically along with the continuous semiconductor scaling. ASET started a 4-year project to reduce mask manufacturing cost and TAT by optimizing Mask Data Preparation (MDP), mask writing, and mask inspection in 2006, with the support from the New Energy and Industrial Technology Development Organization (NEDO). Concerning the mask inspection, the project aims at shortening the review time after inspection. In mask inspection it approaches the limit to inspect the entire surface of a mask in the unique defect judgment algorithm without a pseudo defect. In addition, a nuisance defect including a pseudo defect increases by raising the defect detection sensitivity, and the review time after inspection increases. Mask inspection total time increases too and this will raise the mask inspection cost. Practical mask inspection can be conducted now by inputting the judgment level based on directions of design data there and by making a defect judgment level of every domestic area changeable. We can also shorten the review time by analyzing the printability on the wafer of the detected defect by the simulation, and by using the result for the defect judgment. In this report, we will show the latest research result about an inspection system technology that the defect judgment level for each domestic area can be changed, and a method to input the defect judgment level based on the pattern importance, which a device designer intended, into inspection equipment. In addition, we will show a design of the interface technology that hand over the information of the detected defect to a process simulator (wafer image simulator).