Showing papers on "Mask inspection published in 2016"

Scanning scattering contrast microscopy for actinic EUV mask inspection

Abstract: Actinic mask inspection for EUV lithography with targeted specification of sensitivity and throughput is a big challenge and effective solutions are needed. We present a novel method for actinic mask inspection, i.e. scanning scattering contrast microscopy. In this method the EUV mask is scanned with a beam of relatively small spot size and the scattered light is recorded with a pixel detector. Since the mask layout is known, the scattering profile of a defect-free mask at the detector can be calculated. The signal between the measured and calculated signal provides the deviation between the real mask and its ideal counterpart and a signal above a certain threshold indicates the existence of a defect within the illumination area. Dynamic software filtering helps to suppress strong diffraction from defect free structures and allows registration of faint defects with high sensitivity. With the continuous scan of the whole mask area, a defect map can be obtained with high throughput. Therefore, we believe that this method has the potential of providing an effective solution for actinic mask inspection. Here we discuss the basic principles of the method, present proof-of-principle experiments, describe the basic components of a feasible stand-alone tool and present early results of the performance estimations of such a tool.

Scanning coherent diffractive imaging method and system for actinic mask inspection for euv lithography

Abstract: Reflective and scanning CDI for identifying errors in mask patterns and defects on mask blanks. Providing a set-up for scanning the mask in reflection mode with low and/or high NA. Illuminating the mask pattern with EUV light at 2 to 35°. Detecting the diffracted light beam with a position sensitive detector. Analyzing the detected intensities using ptychographic algorithms and thereby obtaining a high resolution image of the sample of arbitrary patterns. Analyzing the detected intensities for intensity variations deviating from the normal intensity distribution caused by the periodic mask pattern in order to detect defects on the mask. This novel technique may be referred to as differential CDI. For periodically structured masks, a fast inspection can be executed by steps of multiples of period, which should give the same diffraction pattern. The investigation for only the deviation from the normal diffraction pattern allows rapid identification of periodic mask pattern defects.

Printability of buried extreme ultraviolet lithography photomask defects

Abstract: Native acting phase-programmed defects, otherwise known as buried program defects, with attributes very similar to native defects, were successfully fabricated using a high-accuracy overlay technique. The defect detectability and visibility were analyzed with conventional amplitude and phase-contrast blank inspection at 193-nm wavelength, pattern inspection at 193-nm wavelength, and scanning electron microscopy. The mask was also printed on wafer, and printability is discussed. Finally, the inspection sensitivity and wafer printability are compared, leading to the observation that the current blank- and pattern-inspection sensitivity is not enough to detect all of the printable defects.

EUV mask and wafer defectivity: strategy and evaluation for full die defect inspection

Abstract: Over the past few years numerous advancements in EUV Lithography have proven its feasibility of insertion into High Volume Manufacturing (HVM).1, 2 A lot of progress is made in the area of pellicle development but a commercially solution with related infrastructure is currently unavailable.3, 4 Due to current mask structure and unavailability of a pellicle, a comprehensive strategy to qualify (native defects) and monitor (adder defects) defectivity on mask and wafer is required for implementing EUV Lithography in High Volume Manufacturing. In this work, we assess multiple strategies for mask and wafer defect inspection including a two-fold solution to leverage resolution of e-beam inspection along with throughput of optical inspection are evaluated. Defect capture rates for inspections based on full-die, critical areas based on priority and hotspots based on design and prior inspection data are evaluated. Each strategy has merits and de-merits, particularly related to throughput, effective die coverage and computational overhead. A production ready EUV Exposure tool was utilized to perform exposures at the IBM EUV Center of Excellence in Albany, NY for EUV Lithography Development along with a fully automated line of EUV Mask Infrastructure tools. We will present strategies considered in this study and discuss respective results. The results from the study indicate very low transfer rate of defect detection events from optical mask inspection. They also suggest a hybrid strategy of utilizing both optical and e-beam inspection can provide a comprehensive defect detection which can be employed in High Volume Manufacturing.

Non-traditional inspection strategy for inline monitoring in excursion scenarios: Defect inspection

Abstract: Different tool platforms are used in conjunction for patterned wafer inspection like 9xxx & 29xx provided by KLA Tencor. Depending on the sensitivity & throughput requirements, a chip fabrication plant mixes and matches the inline inspection strategies to ensure early detection of defects on the chip, which could cause yield loss or reliability problems. This paper discusses the use of a novel concept of high sensitivity & high throughput inspection strategy using the 29xx tool. This is achieved by using a unique combination of Broad-Band light with Dark Field Apertures. This application can be used to monitor and screen a large number of wafers affected by out of control situations. A use-case is also discussed where optically strong defect locations uniquely seen on 29xx tool were found to be invisible after SEM review. After analyzing defects using see-through imaging on Scanning Electron Microscope (SEM), along with Transmission Electron Microscope (TEM) of the defect locations, those defects were confirmed to be buried defects inside the current layer. Due to low sampling on inspection tools, it was difficult to determine the quantity of wafers affected by the issue. By using high throughput (TPT) 29xx features, a methodology to screen out a high volume of wafers at high throughput was implemented & used to monitor the variability in the process and identify wafers at risk. This methodology enabled inspection of ∼15 wafers per hour. The same methodology was subsequently successfully implemented to verify/monitor multiple excursion scenarios at different process steps.

Mask inspection apparatus and mask inspection method

Abstract: An inspection target is illuminated by an illumination optical unit using a light source Optical image data of a pattern disposed in the inspection target is acquired by an imaging unit by causing light transmitted or reflected to be incident to a first and second area of a sensor Reference image data is generated, corresponding to the optical image data, from design data of the pattern The optical image data is corrected by obtaining a fluctuation of a gradation value of optical image data acquired using light incident to the second area, and correcting a gradation value of optical image data acquired using the light incident to the first area A line width of the pattern of the corrected data, and a line width error which is a difference between the line widths of corrected data and reference image data are obtained by the line width error obtaining unit

Simulating semiconductor structures for next-generation optical inspection technologies

Abstract: We present a technique for optimizing advanced optical imaging methods for nanoscale structures, such as those encountered in the inspection of cutting-edge semiconductor devices. The optimization flow is divided to two parts: simulating light-structure interaction using the finite-difference time-domain (FDTD) method and simulating the optical imaging system by means of its optical transfer function. As a case study, FDTD is used to simulate 10-nm silicon line-space and static random-access memory patterns, with irregular structural protrusions and silicon-oxide particles as defects of interest. An ultraviolet scanning-spot optical microscope is used to detect these defects, and the optimization flow is used to find the optimal imaging mode for detection.

Pattern inspection of etched multilayer extreme ultraviolet mask

Abstract: Patterned mask inspection for an etched multilayer (ML) extreme ultraviolet mask was investigated. In order to optimize the mask structure from the standpoint of a pattern inspection the mask structure not only from the standpoint of a pattern inspection by using a projection electron microscope but also by using a projection electron microscope but also by considering the other fabrication processes using electron beam techniques such as critical dimension metrology and mask repair, we employed a conductive layer between the ML and substrate. By measuring the secondary electron emission coefficients of the candidate materials for the conductive layer, we evaluated the image contrast and the influence of the charging effect. In the cases of 40-pair ML, 16-nm-sized extrusion and intrusion defects were found to be detectable more than 10 sigma in half pitch 44, 40, and 32 nm line-and-space patterns. Reducing 40-pair ML to 20-pair ML degraded the image contrast and the defect detectability. However, by selecting B4C as a conductive layer, 16-nm-sized defects and etching residues remained detectable. The 16-nm-sized defects were also detected after the etched part was refilled with Si. A double-layer structure with 2.5-nm-thick B4C on metal film used as a conductive layer was found to have sufficient conductivity and also was found to be free from the surface charging effect and influence of native oxide.

Through-pellicle defect inspection of EUV masks using an ArF-based inspection tool

Abstract: The use of EUV photomasks in a semiconductor manufacturing environment requires their periodic inspection to ensure they are continually free of defects that could impact device yield. Defects typically occur from fall-on particles or from surface degradation such as “haze”. The proposed use of a polycrystalline-based EUV pellicle to prevent fall-on particles would preclude periodic through-pellicle mask defect inspection using e-beam, as well as, DUV inspection tools (the pellicle is opaque at DUV wavelengths). Thus, to use these types of defect inspection tools would require removal of the EUV pellicle before inspection. After inspection, the pellicle would need to be re-attached and the mask re-qualified using a test wafer, thus causing expense and delays. While EUV-wavelength inspection tools could inspect through such a pellicle precluding the need to remove the pellicle, these tools are not likely to be available in the commercial marketplace for many years. An alternate EUV pellicle material has been developed that is semi-transparent to 193nm wavelengths, thus allowing through-pellicle inspection using existing ArF-based, or other 193nm wavelength mask inspection tools. This eliminates the requirement to remove the pellicle for defect inspection and the associated time and expense. In this work, we will conduct an initial evaluation of through-pellicle EUV mask defect inspection using an existing 193nm mask inspection tool. This initial evaluation will include durability of the pellicle to defect inspection, and impact of the pellicle on inspection tool performance.

Scanning coherent scattering methods for actinic EUV mask inspection

Abstract: Actinic mask inspection for EUV lithography with targeted specifications of resolution, sensitivity, and throughput remains a big hurdle for the successful insertion of EUVL into high volume manufacturing and effective solutions are needed to address this. We present a method for actinic mask inspection based on scanning coherent scattering microscopy. In this method, the mask is scanned with an EUV beam of relatively small spot size and the scattered light is recorded with a pixel detector. Customized algorithms reconstruct the aerial image by iteratively solving the phaseproblem using over-determined diffraction data gathered by scanning across the specimen with a finite illumination. This approach provides both phase and amplitude of actinic aerial images of the mask with high resolution without the need to use high NA (numerical aperture) lenses. Futher, we describe a reflective mode EUV mask scanning lensless imaging tool (RESCAN), which was installed at the XIL-II beamline and later at the SIM beamline of the Swiss Light Source and show reconstructed aerial images down to 10 nm (on-wafer) resolution. As a complementary method, the a-priori knowledge of the sample is employed to identify potential defect sites by analyzing the diffraction patterns. In this method, the recorded diffraction patterns are compared with the die or database data (i.e. previously measured or calculated diffraction data from the defect-free mask layout respectively) and their difference is interpreted as the defect signal. Dynamic software filtering helps to suppress the strong diffraction from defect-free structures and allows registration of faint defects with high sensitivity. Here, we discuss the basic principles of these Fourier domain techniques and its potential for actinic mask inspection with high signal-to-noise ratio and high throughput.

Detection of printable EUV mask absorber defects and defect adders by full chip optical inspection of EUV patterned wafers

Abstract: The ability to rapidly detect both printable EUV mask adder defects as well as mask absorber defects across the entire mask image field is a key enabler for EUV lithography. Current optical wafer-based inspection techniques are only capable of detecting repeater defects on a Die-to-Die basis for chiplets within the image field. Larger server-type chips that encompass the entire mask image field cannot rely on such a scheme, since the presence of the defect in every die prevents their detection. In this study, a prototype optical wafer defect inspection methodology designed to detect repeater defects over the entire image field, termed Die-to-Baseline Reference Die (D2BRD), is investigated. The sensitivity of this inspection technique is demonstrated and compared to eBeam inspection over a range of defect sizes for both opaque and clear type mask absorber programmed defects. Moreover, the D2BRD methodology is used to monitor printing defect adders present in a lithographic defect test mask, as well as 7 nm metal mask layer. Using defect repeater analysis, SEM review and patch image classification of full chip wafer inspections over several mask cycles, the D2BRD scheme is shown to allow the unambiguous identification of both mask adder and absorber "native" mask defects, while suppressing random process defects. Thus, this methodology has the potential to help define the risk assessment of mask adder defects in the absence of an EUV pellicle, and can play an integral part of the wafer print protection strategy.

Automatic inspection of a residual resist layer by means of self-organizing map

Abstract: Photolithography allows large-scale fabrication of nanocomponents in the semiconductor industry. This technique consists of manufacturing a desired pattern on a photoresist film transferred onto the substrate during the etching process. Therefore, the mask quality is essential for reliable etching. For example, the presence of a residual layer of resist might be considered as a mask defect and can lead to the failure of the etching process. We propose the use of a Kohonen self-organizing map for automatic detection of a residual layer from an ellipsometric signature. The feasibility of the suggested inspection by the use of a classification technique is discussed and simulations are carried out on a 750-nm period grating.

Mask inspection device and method

Abstract: PROBLEM TO BE SOLVED: To provide a mask inspection device and a mask inspection method capable of creating a reference image having high accuracy, and improving inspection accuracy, using an optical image which is collected in advance, in a whole image collection inspection method.SOLUTION: A reference image created on a reference circuit 14 is stored in a buffer memory 15a, and an optical image collected by an optical image acquisition part 101 is stored in a buffer memory 15b. A reference image learning/creation estimation re-configuration circuit 15c determines defects based on difference of a comparison result of the reference image and the optical image in a specific area, and when a defect number is larger than a predetermined threshold, uses a reference image learning/creation point candidate to re-configure reference image learning/creation estimation of the reference image stored in the buffer memory 15a. The reference image stored in the buffer memory 15a with the re-configured reference image learning/creation estimation and the optical image stored in the buffer memory 15b are input to a comparison circuit 15d, and comparison in off-line is executed.SELECTED DRAWING: Figure 5

An automatic optical system for micro-defects inspection on 5 surfaces of a chip

Abstract: The novelty of three-dimensional integrated circuit (3DIC) chips indicates the thin-chip stacks on both front side and back side, so relative thinness is easily to affect the dicing quality while cutting wafers into species of chips. For the common defects of the chipping and glue, they are usually occurred on chip surfaces of front side, backside and edgesides, accompanied by the cutting process, and it is the dominant role to lower the yield rate. Therefore, the main purpose of the study is to implement the efficient defect inspection system for five surfaces (1 backside and 4 edgesides) of each chip and assess the quality in almost real-time fabricating. Here a new architecture with multiple pick and place heads to suck chips and move synchronously for image acquisition. Additionally, an opto-mechanical module and defect inspection procedures are also proposed and implemented for verifying the chips quality. The preliminary system integration and tests are completed and the inspection performance can be achieved around 95% correctness.

Study of extreme ultraviolet lithography patterned mask inspection tool for half-pitch 11-nm node defect detection performance

Abstract: Extreme ultraviolet lithography (EUVL) patterned mask defect detection is one of the major issues to overcome for realization of EUVL-based device fabrication. We have designed projection electron microscope (PEM) optics that have been integrated into a new inspection system called EBEYE-V30 (“Model EBEYE” is EBARA’s model code), and the PEM system performs well in half-pitch (hp) 16-nm node EUVL patterned mask inspection applications. We also discuss the extendibility of this system to 11-nm node defect detection. The progress made in the performance of the PEM optics is not simply about producing an image sensor with higher resolution but is also about improvement of the image processing to enhance the defect signal. A high-speed image sensor, a high-speed image-processing circuit, and a bright and stable electron source are necessary for hp 11-nm defect inspection. We describe the experimental results for EUVL patterned mask inspection using the above system for the hp 11-nm node. Programmed hp 11-nm defects (equivalent to 44 nm on the mask) are used for defect detection sensitivity evaluation. Defects as small as 16 nm on the mask could be detected using the current PEM system configuration.

Recent results from extreme ultraviolet lithography patterned mask inspection for 11 nm half-pitch generation using projection electron microscope system

Abstract: Extreme ultraviolet lithography (EUVL) is a promising technique for 1X nm half-pitch (hp) generation lithography. The inspection of patterned EUVL masks is one of the main issues that must be addressed during mask fabrication for manufacture of devices with 11 nm hp feature sizes. We have already designed projection electron microscope (PEM) optics that have been integrated into a new inspection system called Model EBEYE-V30 (where “Model EBEYE” is an EBARA’s model code) and this system seems quite promising for 16 nm hp generation EUVL patterned mask inspection. The defect inspection sensitivity of this system was evaluated via capture of an electron image that was generated at the mask by focusing the image through the projection optics onto a time-delay integration (TDI) image sensor. For increased throughput and higher defect detection sensitivity, a new electron-sensitive area image sensor with a high-speed data processing unit, a bright and stable electron source, and a simultaneous deflector for the image capture area that follows the mask scanning motion have been developed. Using a combination of synchronous deflection and mask scanning, the image can be integrated into both the fixed area image sensor and the TDI image sensor. We describe our experimental results for EUV patterned mask inspection using the above system. Elements have been developed for inspection tool integration and the designed specification has been verified. The system performance demonstrates the defect detectability required for 11 nm hp generation EUVL masks.

Reticle decision center: a novel applications platform for enhancing reticle yield and productivity at 10nm technology and beyond

Abstract: In the semiconductor IC manufacturing industry, challenges associated with producing defect-free photomasks have been dramatically increasing. At the 10nm technology node, since the 193nm immersion scanner numerical aperture has remained the same 1.35 as in previous nodes, more multi-patterning and aggressive SMO illumination sources are being used to effectively print smaller feature CDs and pitches. To accommodate such specialized sources, more model-based mask OPC and ILT have been used making mask designs very complicated. This in turn makes mask manufacturing very challenging especially for the defect inspection, repair, and metrology processes that need to guarantee defect-free masks. Over the past few years, considerable innovation have been made in the areas of defect inspection and disposition that has ensured continued predictability of mask quality to wafer and final chip yields. The accurate disposition of each mask defect before and after repair has been facilitated by a suite of automated applications such as ADC, LPR, RPG, AIA, etc. that work together with the inspection, repair, and metrology tools and effectively also provide the best possible utilization of the tool capability, capacity and operator resources. In this paper we introduce a new consolidated applications platform called the Reticle Decision Center (RDC) which hosts all these supporting software applications on a centralized server with direct connectivity to mask inspection, repair, metrology tools and more. The paper details how the RDC server is architected to host any application in its native operating system environment and provides for high availability with automatic failover and redundancy. The server along with its host of applications has been tightly integrated with KLA-Tencor’s Teron mask inspectors. The paper concludes with showing benefits realized in mask cycle-time and yield as a result of implementing RDC into a high-volume 10nm mask-shop production line.

Automated klarf-based defect inspection by electron-beam inspection tool: a novel approach to inline monitoring and/or process change validation

Abstract: We report an optical inspection guided e-beam inspection method for inline monitoring and/or process change validation. We illustrate its advantage through the case of detection of buried voids/unlanding vias, which are identified as yield-limiting defects to cause electrical connectivity failures. We inspected a back end of line (BEOL) wafer after the copper electro plating and chemical mechanical planarization (CMP) process with bright field inspection (BFI) and employed EBI to inspect full wafer with guidance of BFI klarf file. The dark voltage contrast defects were detected and confirmed as buried voids by transmission electron microscopy (TEM).

Polygon-based geometry classification for semiconductor mask inspection

Abstract: Disclosed are methods and apparatus for providing feature classification for inspection of a photolithographic mask. A design database for fabrication of a mask includes polygons that are each defined by a set of vertices. Any of the polygons that abut each other are grouped together. Any grouped polygons are healed so as to eliminate interior edges of each set of grouped polygons to obtain a polygon corresponding to a covering region of such set of grouped polygons. Geometric constraints that specify requirements for detecting a plurality of feature classes are provided and used for detecting a plurality of feature classes in the polygons of the design database. The detected features classes are used to detect defects in the mask.

Take a byte out of MEEF: VAMPIRE: Vehicle for Advanced Mask Pattern Inspection Readiness Evaluations

Abstract: MEEF, or Mask Error Enhancement Factor, is simply defined as the ratio of the change in printed wafer feature width to the change in mask feature width scaled to wafer level. It is important in chip manufacturing that leads to the amplification of mask errors, creating challenges with both achieving dimensional control tolerances and ensuring defect free masks, as measured by on-wafer image quality. As lithographic imaging continues to be stressed, using lower and lower k1 factor resolution enhancement techniques, the high MEEF areas present on advanced optical masks creates an environment where the need for increased mask defect sensitivity in high-MEEF areas becomes more and more critical. There are multiple approaches to mask inspection that may or may not provide enough sensitivity to detect all wafer-printable defects; the challenge in the application of these techniques is simultaneously maintaining an acceptable level of mask inspectability. The higher the MEEF, the harder the challenge will be to achieve and appropriate level of sensitivity while maintaining inspectability…and to do so on the geometries that matter. The predominant photomask fabrication inspection approach in use today compares the features on the reticle directly with the design database using high-NA optics. This approach has the ability to detect small defects, however, when inspecting aggressive OPC, it can lead to the over-detection of inconsequential, or nuisance defects. To minimize these nuisance detections, changing the sensitivity of the inspection can improve the inspectability of a mask inspected in high-NA mode, however, it leads to the inability to detect subtle, yet wafer-printable defects in High-MEEF geometry, due to the fact that this ‘desense’ must be applied globally. There are also ‘lithography-emulating’ approaches to inspection that use various means to provide high defect sensitivity and the ability to tolerate inconsequential, non-printing defects by using scanner-like conditions to determine which defects are wafer printable. This inspection technique is commonly referred to as being ‘lithography plane’ or ‘litho plane,’ since it’s assessing the mask quality based on how the mask appears to the imaging optics during use, as proposed to traditional ‘reticle plane’ inspection which is comparing the mask only with its target design. Regardless of how the defects are detected, the real question is when should they be detected? For larger technology nodes, defects are considered ‘statistical risks’…i.e., first they have to occur, and then they have to fall in high-MEEF areas in order to be of concern, and be below the detection limits of traditional reticle-plane inspection. In short, the ‘perfect storm’ has to happen in order to miss printable defects using well-optimized traditional inspection approaches. The introduction of lithographic inspection techniques has revealed this statistical game is a much higher risk than originally estimated, in that very subtle waferprintable CD errors typically fall into the desense band for traditional reticle plane inspection. Because printability is largely influenced by MEEF, designs with high-MEEF values are at greater risk of traditional inspection missing printable CD errors. The question is… how high is high… and at what MEEF is optical inspection at the reticle plane sufficient? This paper will provide evaluation results for both reticle-plane and litho-plane inspections as they pertain to varying degrees of MEEF. A newly designed high-MEEF programmed defect test mask, named VAMPIRE, will be introduced. This test mask is based on 7 nm node technology and contains intentionally varying degrees of MEEF as well as a variety of programmed defects in high-MEEF environments…all of which have been verified for defect lithographic significance on a Zeiss AIMS system.

Mask inspection system for inspecting lithography masks

Abstract: One aspect of the present invention relates to a mask inspection system for inspecting lithography masks, including a placement table for placing a lithography mask to be inspected, a first optical unit with a first beam path for examining structures of the lithography mask, and a second optical unit with a second beam path for establishing a position of at least one edge of the lithography mask. Here, the second beam path of the second optical unit passes at least once through a plane defined by the placement table.

Enhanced defect detection capability using learning system for extreme ultraviolet lithography mask inspection tool with projection electron microscope optics

Abstract: Extreme ultraviolet lithography (EUVL) patterned mask defect detection is a major issue that must be addressed to realize EUVL-based device fabrication. We have designed projection electron microscope (PEM) optics for integration into a mask inspection system, and the resulting PEM system performs well in half-pitch (hp) 16-nm-node EUVL patterned mask inspection applications. A learning system has been used in this PEM patterned mask inspection tool. The PEM identifies defects using the “defectivity” parameter that is derived from the acquired image characteristics. The learning system has been developed to reduce the labor and the costs associated with adjustment of the PEM’s detection capabilities to cope with newly defined mask defects. The concepts behind this learning system and the parameter optimization flow are presented here. The learning system for the PEM is based on a library of registered defects. The learning system then optimizes the detection capability by reconciling previously registered defects with newly registered defects. Functional verification of the learning system is also described, and the system’s detection capability is demonstrated by applying it to the inspection of hp 11-nm EUV masks. We can thus provide a user-friendly mask inspection system with reduced cost of ownership.

Defect inspection and printability study for 14 nm node and beyond photomask

Abstract: Two different mask inspection techniques are developed and compared for 14 nm node and beyond photomasks, High resolution and Litho-based inspection. High resolution inspection is the general inspection method in which a 19x nm wavelength laser is used with the High NA inspection optics. Litho-based inspection is a new inspection technology. This inspection uses the wafer lithography information, and as such, this method has automatic defect classification capability which is based on wafer printability. Both High resolution and Litho-based inspection methods are compared using 14 nm and 7 nm node programmed defect and production design masks. The defect sensitivity and mask inspectability is compared, in addition to comparing the defect classification and throughput. Additionally, the Cost / Infrastructure comparison is analyzed and the impact of each inspection method is discussed.

Identification of multilayer structures using secondary electron yield curves: effect of native oxide films on EUV-patterned mask inspection

Abstract: The impact of EUV mask surface conditions on the patterned mask inspection process was investigated. The results of simulations show that the defect detection capability is degraded by the formation of a native oxide film on the surface of a Ru capped multilayer. This effect was assessed by constructing the secondary electron yield (SEY) curves of the EUV mask materials. These experimentally-obtained SEY curves were examined using semi-empirical Monte Carlo simulations. The simulation results demonstrated that a native oxide film increased the SEY, and that this effect varied with film thickness. The results suggest that defect detection capability will vary according to the thickness of the native oxide when employing an inspection system using an electron beam technique. Also of interest is the finding that the thickness of the native oxide film can be ascertained by fitting the SEY curves.

Semiconductor device inspection apparatus and semiconductor device inspection method

Abstract: A semiconductor device inspection apparatus includes probe sockets and an insulating plate that holds probes via the probe sockets. The probe sockets each include an opposing part that opposes the insulating plate in the direction in which the probe is pressed and has a pressure passive member disposed in the opposing part. The insulating plate is transparent. When pressing force is applied to the tips of the probes, the pressure passive members are pressed between the opposing parts of the probe sockets and the insulating plate. The semiconductor device inspection apparatus further includes a camera to capture an image of the pressure passive members from the opposite side of the insulating plate to the side on which the pressure passive members are disposed, and an image processor to process the image captured by the camera to detect the presence or absence of pressure received by the pressure passive members.

Wafer inspection method

Abstract: [Problem] To provide a wafer inspection method whereby inspection accuracy and operation efficiency can be improved. [Solution] In this wafer inspection method for performing electrical inspection by bringing, at one time, a plurality of probes into contact with a plurality of pads in chips on a wafer, said probes being provided in a probe card, the inspection is performed through: a chuck step S1 for heating the wafer to an inspection temperature by holding the wafer by means of a wafer chuck; a first position recognition step S2 for recognizing all the positions of the pads of the chips in the wafer; a second position recognition step S3 for re-recognizing, before performing the electrical inspection, the positions of the pads for the purpose of recognizing the positional shifts of the pads due to thermal expansion generated when the wafer chuck is heated; and a correction step S4 for correcting contact positions with respect to the probes, said contact positions being corrected on the basis of pad positions, which have been re-recognized in the second position recognition step S3 on the basis of the pad positions recognized in the first position recognition step S2, and which have been updated.

Accurate characterization of mask defects by combination of phase retrieval and deterministic approach

Abstract: In this paper, we present a method to characterize not only shape but also depth of defects in line and space mask patterns. Features in a mask are too fine for conventional imaging system to resolve them and coherent imaging system providing only the pattern diffracted by the mask are used. Then, phase retrieval methods may be applied, but the accuracy it too low to determine the exact shape of the defect. Deterministic methods have been proposed to characterize accurately the defect, but it requires a reference pattern. We propose to use successively phase retrieval algorithm to retrieve the general shape of the mask and then deterministic approach to characterize precisely the defects detected.

Photomask inspection machine

Abstract: The invention relates to a photomask inspection machine. An optical image processing module positioned above a carrying table is arranged on a rack; the linear displacement of the optical image processing module relative to the carrying table can be carried out; the optical image processing module can capture the image of a photomask on the carrying table; or an upper detection module is provided with a light guiding unit on one side of the optical image processing module; the light guiding unit is provided with a light source and a light guiding plate, wherein the light guiding plate can guide the light rays of the light source to shoot at a scanning position of the optical image processing module in a linear manner; therefore, the optical image processing module formed by a linear image photosensitive element can rapidly scan the surface of the photomask; due to the effect of the light guiding plate of the inclined light guiding unit, the light rays of the light source can shoot the scanning position of the optical image processing module in an inclined manner to improve the focusing effect so as to improve the recognition rate of pollutants; and therefore, the inspection efficiency and accuracy can be effectively improved, unnecessary manpower and misjudgment can be reduced, and the percent of pass of the subsequent processing of wafers can be further improved.

A study of an alignment-less lithography method as an educational resource

Abstract: A simplification of the lithography process was studied. The simplification method of photolithography, named “alignment-less lithography” was proposed by omitting the photomask alignment process in photolithography process using mechanically aligned photomasks and substrate by using a simple jig on which countersinks were formed. Photomasks made of glass and the photomasks made of transparent plastic sheets were prepared for the process. As the result, approximately 5µm in the case of the glass mask, and 20µm in the case of the OHP mask were obtained with repetitive accuracies, respectively. It was confirmed that the alignment-less lithography method was successful. The possibility of the application to an educational program, such as a heuristic for solving problems was suggested using the method with the OHP mask. The nMOS FET fabrication process was successfully demonstrated using this method. The feasibility of this process was confirmed. It is expected that a totally simplified device fabrication process can be achievable when combined with other simplifications, such ass the simplified impurity diffusion processes using PSG and BSG thin film as diffusion source prepared by the Sol-Gel material under normal air environment.

Extreme ultraviolet patterned mask inspection performance of advanced projection electron microscope system for 11nm half-pitch generation

Abstract: Novel projection electron microscope optics have been developed and integrated into a new inspection system named EBEYE-V30 (“Model EBEYE” is an EBARA’s model code) , and the resulting system shows promise for application to half-pitch (hp) 16-nm node extreme ultraviolet lithography (EUVL) patterned mask inspection. To improve the system’s inspection throughput for 11-nm hp generation defect detection, a new electron-sensitive area image sensor with a high-speed data processing unit, a bright and stable electron source, and an image capture area deflector that operates simultaneously with the mask scanning motion have been developed. A learning system has been used for the mask inspection tool to meet the requirements of hp 11-nm node EUV patterned mask inspection. Defects are identified by the projection electron microscope system using the “defectivity” from the characteristics of the acquired image. The learning system has been developed to reduce the labor and costs associated with adjustment of the detection capability to cope with newly-defined mask defects. We describe the integration of the developed elements into the inspection tool and the verification of the designed specification. We have also verified the effectiveness of the learning system, which shows enhanced detection capability for the hp 11-nm node.