Mask inspection

About: Mask inspection is a research topic. Over the lifetime, 1072 publications have been published within this topic receiving 8696 citations.

Direct Mask Overlay Inspection

Abstract: Direct mask overlay inspectionLiang -Choo Hsia and Lo -Soun SuMask Engineering, General Technology DivisionIBM Corporation, East Fishkill, New York 12533AbstractIn this paper, we present a mask inspection methodology and procedure that involvesdirect X -Y measurements. A group of dice is selected for overlay measurement; four measure-ment targets were laid out in the kerf of each die. The measured coordinates are then fit-ted to either a "historical" grid, which reflects the individual tool bias, or to an idealgrid squares fashion. Measurements are done using a Nikon X -Y laser interferometric mea-surement system, which provides a reference grid. The stability of the measurement systemis essential. We then apply appropriate statistics to the residual after the fit to deter-mine the overlay performance.Statistical methods play an important role in the product disposition. The acceptancecriterion is, however, a compromise between the cost for mask making and the final deviceyield. In order to satisfy the demand on mask houses for quality of masks and high volume,mixing lithographic tools in mask making has become more popular, in particular, mixingoptical and E -beam tools. In this paper, we also discuss the inspection procedure formixing different lithographic tools.IntroductionThe trend towards denser circuits, smaller device geometries, and larger wafer size hasmade mask overlay inspection most critical in VLSI manufacture. Misregistration problemscan give rise to large yield losses. Therefore, a reliable mask overlay inspection pro-cedure is essential. The measurements must be accurate and repeatable. On the other hand,the advent of projection aligner has dramatically increased the working life of a mask andhas made the number of masks needed per level decrease continuously. The near future maysee a situation where one to two masks suffice for each masking level, even for high volumeVLSI device manufacture. Therefore, it will be more economical to inspect each mask verycarefully. In particular, for bipolar device fabrication, which requires more than 16lithographic steps, the quality of each photomask has great impact on yield losses.As improvements have been made over the years, E -beam lithographic tools have beengradually accepted by mask makers for 1X mask making. Compared with optical mask making,E -beam mask making has the advantages of design flexibility, quick turnaround time, betterresolution, and perhaps better placement accuracy. However, E -beam mask making is expen-sive and the equipment is difficult to maintain. A cost -effective approach lies in mixingE -beam with optical mask making. The overlay matchability between the two, therefore,must first be guaranteed. In this paper, we present an inspection methodology and proced-ure for solving this problem.

Spatial heterodyne interferometry techniques and applications in semiconductor wafer manufacturing

Abstract: Spatial heterodyning is an interferometric technique that allows a full complex optical wavefront to be recorded and quickly reconstructed with a single image capture. Oak Ridge National Laboratory (ORNL) has combined a high-speed, image capture technique with a Fourier reconstruction algorithm to produce a method for recovery of both the phase and magnitude of the optical wavefront. Single frame spatial heterodyne interferometry (SHI) enables high-speed inspection applications such as those needed in the semiconductor industry. While the wide range of materials on wafers make literal interpretation of surface topology difficult, the wafers contain multiple copies of the same die and die-to-die comparisons are used to locate defects in high-aspect-ratio structures such as contacts, vias, and trenches that are difficult to detect with other optical techniques. Metrology with SHI has also been investigated by ORNL, in particular the use of SHI to perform metrology of line widths and heights on photolithographic masks for semiconductor wafer production. Several types of masks are currently in use with phase shifting techniques being employed to extend the wafer printing resolution. With the ability to measure the phase of the wavefront, SHI allows a more complete inspection and measurement of the phase shifting regions.

Alignment technique for a scanning beam

Abstract: An alignment system for registration of a scanning beam in a mask inspection tool. Minimum scan widths (W) in the registration process are attained, thereby increasing registration sensitivity. This technique allows initial placement of the E-beam to be outside the capture range so that the scan (1A) on one side of a mask portion (3) is completely off the metal (on glass) and the scan (1 B) on the other side is completely on the metal. Correction signals are obtained by comparing (subtracting) the backscattered electron signals from the two scans, with the magnitude of the resulting signal being indicative of the amount of correction required and the sign being indicative of the direction of correction.

A novel approach to the mask inspection for proximity electron lithography based on electron beam imaging

Abstract: We report the first evaluation results for the printability and detectability of mask defects on a 1x stencil mask as used for proximity electron lithography (PEL). The defect printability has been defined for the patterns after the multi-step etching process through the tri-layer resist system inherently required for the use of low-energy electrons and the substrate. According to the three-dimensional lithography simulation, this definition is preferable to the conventional one based on the resist patterns prior to the etching process in the point that smoothing effects on defects are automatically taken into account. The critical size of printable defects as defined is 22 nm for 140 nm contact holes, while the stringent value of 16 nm is predicted in the conventional definition. Also, the detectability of the printable defects has been assessed by using the transmission electron-beam (EB) inspection tool. The assessment has been performed for both programmed defects and real defects occurred in contact-hole arrays. For the programmed defects, the perfect repeatability has been demonstrated for all the defects with printable sizes. In addition, real defects with the size of 15 nm have been successfully detected in the contact-hole arrays. Therefore, this study has demonstrated the manufacturability of PEL masks from the viewpoint of defect inspection.

Results of new mask contamination inspection capability STARlight2+ 72nm pixel with cell-to-cell HiRes5 for qualifying memory masks in wafer fabs

Abstract: As the industry embarks on sub 50nm half pitch design nodes, higher resolution and advanced photomask inspection algorithm are needed to resolve shrinking features and find critical yield limiting defects In this paper, we evaluate the detection capability of STARlight2+ 72nm pixel on sub-50nm memory masks The mask sets targeted for this evaluation were focused on critical layers Although memory mask sets are dominated by multi-die layout, single die layout masks were also inspected because of their significance during research and development Inspection results demonstrated the performance of STARlight2+ based on its sensitivity to contamination defects and the inspectability of masks with this detection method The most common plan of record for mask inspection in a wafer fab is die-to-die transmitted pattern inspection modes, which limits the inspection area to the die region only and cannot be used for single-die reticle inspections However, STARlight2+ has single die inspection capability, which is also needed in order to inspect scribe-lines and frame areas The primary defects of interest are photo induced crystal defects or haze Haze continues to be the primary reason for mask returns at 193nm exposure across the industry The objective of this paper is to demonstrate STARlight2+ 72nm capability to support memory wafer fab mask qualification requirements