Mask inspection

About: Mask inspection is a research topic. Over the lifetime, 1072 publications have been published within this topic receiving 8696 citations.

Defects analysis of mask blanks

Abstract: As photomask making procedures extend to more and more complex and difficult, the detected numbers of the quartz defects are increasing trend. These kinds of defects have been less detected frequently or not detected before. But, it can be found enough now because inspection machines are developed high resolution, short wavelength light source and low pixel size to find small size defects. Defect shapes and sizes detected by inspection machine are evaluated and classified to several types with SEM and then analyzed the wafer printing result with transmission data of the inspection and AIMS simulation result. By this analyzed result, the judge reference of the quartz defect was provided when the defect was detected by inspection machine during producing photomask. This will improve mask yield by reducing mask reject ratio classified blank mask defect problems.

Lithography printability review: the ultimate step in reticle analyzer to avoid killer mask defects in wafer fab manufacturing

Abstract: Comprehensive disposition of reticle defects is critical for process and yield control. Misjudging a real defect on mask may not only reduce its lithography process window but also kill thousands of wafers causing unbearable economic loss. With the development of OPC and ILT technology, manual judgement of reticle defects has become more challenging. The situation is even worse in advanced logic fab, especially for foundry, where pattern complexity and diversity vary from worldwide fabless upstream firms. Working with KLA, USCXM adopted and reported ADC (Automated Defect Classification) and DPM (Defect Progressing Monitor) solutions to avoid defect misclassification and to alarm defects degrading [1]. These solutions run smoothly and shorten the cycle time in daily routine production. However, both functions cannot well predict the defect printability on wafer when there are questionable mask defects. Usually, the problematic mask has to be sent back to mask shop, where an AIMSTM tool evaluates printing risk, leading to a very time-consuming verification cycle. Thus, a cutting-edge technology called LPR (Lithography Printability Review) has been fully qualified and applied in a logic foundry for the first time. Using the optical mask inspection images, with LPR, the aerial image CD error can be accurately modeled thereby eliminating possibility of any related yield loss, while also dramatically shortening the cycle time for verifying such defects. In this paper, we introduce a series of strict qualification processes for LPR adoption. The qualification flow involves both PDM (Programmed Defect Mask) and production mask with respective purpose. The PDM verification covers various defect types while the production mask provides abundant pattern geometry. The LPR vs AIMSTM simulation efficiency is over 90% without missing one killer defect. Furthermore, LPR operates as part of an integrated solution with ADC and DPM. Typical production cases are also presented in this paper to demonstrate its invaluable contribution to avoiding yield loss. The RA (Reticle Analyzer) product including ADC, DPM and LPR, is the only mature solution, and is now deployed in full volume mask manufacturing production, driving intelligent automation with zero misoperation, shortened cycle time, and increased fab productivity.

Reflective mask, its inspection method, and method for manufacturing semiconductor device

Abstract: PROBLEM TO BE SOLVED: To provide a reflective mask capable of mask inspection by pattern comparison on a layout in a mode of scan exposure by injecting exposure light slantly to the mask, and its inspection method. SOLUTION: The reflective mask for irradiating the exposure light slightly incident to a mask surface over a predetermined exposure area and projecting light reflected on the mask surface to a wafer for scan exposure includes a plurality of rectangular chip regions 11a-11f containing the same mask patterns arranged in a scanning direction 12. When shape correction is made depending on a distance from the center line of an exposure area 21 (azimuth angle θ), the two chip regions 11a and 11b have the identical mask patterns after the shape correction. Thus the identical patterns can be compared with each other on the layout to perform die-to-die inspection for defect inspection of the mask pattern. COPYRIGHT: (C)2010,JPO&INPIT

Open issues in mask technology as EUV enters high volume manufacturing

Abstract: After years of optimistic projections and false starts, 2019 is finally the year that EUV will enter volume production. Mask shop investment in EUV-capable equipment, including writing, inspection, metrology, repair, review and cleaning tools as well as related infrastructure for storage, transportation, and pellicle support has been substantial. However, in both mask shops and wafer fabs, key questions remain unanswered even as high volume manufacturing (HVM) begins in the fab. We will highlight several of these questions that still need to be answered to develop comprehensive, end-to-end strategies for mask inspection, use, and qualification strategies. In particular, we will show how uncertainty over pellicle technology options and timing cascade into a series of questions related to reticle qualification flows throughout the lifetime of a mask. Additional uncertainty comes from the lack of data on reticle contamination mechanisms during use in high-power EUV exposure tools. Concerns over hydrocarbon deposition and reaction with intense EUV photons as well as with the out-of-band DUV present in the system, will require the development of careful monitoring and re-qualification plans. Reticle requalification cycles will be gated not just by the number of wafers exposed, but by the number of times a reticle is loaded and unloaded from the scanner and how long it sits in storage between cycles. We anticipate that a combination of wafer-based and reticle-based inspection will be required to fully ensure reticle quality, especially if a pellicle solution is adopted which does not allow 193nm based inspection. These tradeoffs and uncertainties will be discussed in the context of a full, mask blank to wafer fab reticle qualification strategy for EUV volume manufacturing.

Aerial image based mask defect detection in dense array structures

Abstract: For leading mask technologies the mask inspection for finding critical defects is always a difficult task. With the introduction of chrome-less, high-transmission and alternating mask types, new absorber material and the possibility of quartz defects the defect inspection and -classification becomes even more challenging. To decide whether a defect is critical or a repair is successful, the Zeiss AIMS tool is used to classify defects. For conventional imaging the optical settings are usually chosen such that resolution is maximized, for example a dipole illumination is used for imaging a dense line-space array at an optimum contrast. In this paper we will do the opposite and reduce the optical resolution, such that we can filter out the array pattern and study the resulting defect image. This technique allows using a simple threshold detector to find and classify defects.