Mask inspection

About: Mask inspection is a research topic. Over the lifetime, 1072 publications have been published within this topic receiving 8696 citations.

New method of identification of false or nuisance defects using defect imaging system DIS-05

Abstract: This article presents novel defect review tool developed from CD-SEM, and its application for identification, classification and judgment of false or nuisance defects. Mask inspection tool is indispensable for mask production. Since conventional inspection tools use the optical source, some of the defects are difficult to be identified and classified in the proper manner because the tool resolution is not sufficient. We have developed the Defect Imaging System (DIS-05) based on CD-SEM which uses secondary electron and backscattered electron images. These SEM images are used for reviewing the defects detected in advance by optical inspection tools. This system also includes Die-to-Die, Die-to-Database and "any shaped pattern area measurement" of Holon original development.

Impact and characterization of mask repair on wafer CD uniformity

Abstract: The performance of an IC device, as we know, depends upon excellent linewidth control in lithography as the geometry of circuits is being decreased. The quality of the mask always plays an important role in this issue. As far as a wafer fab is concerned, the defective mask can lead to not only a dramatic drop in production yield, but also fatal damage for single-chip products. It is observed that a loss of transmission on a mask, detected by a reticle inspection system KLA303-UV STARlight (Simultaneous Transmitted And Reflected light) can bring about unacceptable CD variation on wafers. One major reason for the loss of transmission on masks is from the defect repair process, during which Gallium stain (Ga+) deposits onto the quartz on the chrome side of mask. This problem will become more and more critical for both mask houses and wafer fabs as long as the linewidth keeps shrinking and the design of denser pattern is inevitable. This purpose of this paper is to detail the correlation between wafer CD variation and the relative loss of transmission on the mask. By way of a designed test reticle processed with Gallium deposition by repair tool, inspection, exposure, CD data collection and analysis, we can clearly define the relationship based on I-line mask inspection light source. Following this work, the fab will be able to set up the inspection specifications for any incoming masks to prevent poor CD uniformity occurring in wafers. More importantly, with the design of a variety of patterns with different line/space ratios and device characteristics on this test reticle, we can try to predict the feasibility and severity of the transmission rate loss of mask for 0.15, 0.13 micrometers generations or beyond in order to help mask houses as well as wafer fabs get prepared and work out this problem prior to the advent of the next IC generation.

A pattern-based design analysis method by using inline inspection data more efficiently

Abstract: The IC chip manufacturing process is an integrated working flow where after each manufacturing step, a yield inspection team will apply great effort and machine resources to inspect and sort through various check points to detect silicon failures. However, despite the great effort, they cannot efficiently cover a whole chip and cross check all the different layers and products at the same time. This paper will present a smart and efficient working flow that can map inspection data back onto a design and produce more diverse monitor points for inspection, and each set of monitor points links to a set of statistical design data that shows insight on design structures that are more sensitive to the process variations. A full-chip post-processing flow is also implemented to process design layout so that the particular patterns that may cause certain function blocks to fail can be directly checked on post-processed layout.

Integration of KLA Starlight for phase-shift mask manufacturing

Abstract: In the chrome-on-glass photomask inspection arena, KLA Starlight tool is mostly used in manufacturing mode as a particle detector and final plate quality verification, before mounting the pellicle, after pelliclization or both. When it applies to phase-shift reticles -- embedded attenuated as well as PhaseEdge --, there are other applications of Starlight defect detectivity, in addition to the above. This paper describes uses of Starlight technology at several process steps of PSM manufacturing. It addresses case of I-line and DUV Cr/MoSi embedded attenuated and multiple level quartz- etched alternating. Illustrations provided show several typical defect. Finally challenge to migrate from a development use into a full manufacturing integration is discussed. Based on Starlight performance, the price to pay to extend use of initially binary chrome-on-glass tool designed for production of phase-shift reticles is seized.

Computational Methods for Design-Assisted Mask Flows

Abstract: Author(s): Kagalwalla, Abde Ali Hunaid | Advisor(s): Gupta, Puneet | Abstract: The cost per die benefit of semiconductor technology scaling that has driven Moore's law is being threatened by increasing manufacturing cost. Masks, which reproduce circuit patterns on the wafer, are the biggest contributor to this manufacturing cost. The need to print sub-wavelength patterns on the wafer and ensure tight dimension control has significantly increased the cost and complexity of mask manufacturing that consists of three key steps: mask data preparation, mask write and mask inspection. In this thesis, we propose novel computational approaches to reduce mask manufacturing cost by using design information to reduce the pessimism of mask manufacturing processes. We further explore benchmarking of computational mask data preparation algorithms.To reduce the pessimism of geometric approaches to estimate lithographic process window, we propose electrical process window (EPW), which accounts for electrical specifications of the circuit layout such as delay, power and static noise margin, thereby reducing pessimism by 1.5 to 8×. To reduce the pessimism in mask inspection, which can take up as much as 30% of the total mask manufacturing time, we propose design-aware mask inspection. We first locate non-functional features in a circuit layout, and then use that information along with the timing information of the design, to assign criticality to different layout shapes. This information can be exploited by mask inspection tools to reduce defect review time and first pass yield of masks. Our results demonstrate 39% reduction in the number of defects reported by the inspection tool and 19%-point improvement in first pass yield of a critical polysilicon mask.Mask fracturing is a key component of mask data preparation that determines the e-beam shots required to write the mask. Since shot count is directly proportional to mask write time, reducing shot count is a key objective for mask fracturing solutions. To evaluate the suboptimality of modern model-based mask fracturing heuristics, we propose an integer programming based benchmarking method and an optimal benchmark generation method. Our methods show that even a state-of-the-art prototype [version of] capability within a commercial tool for e-beam mask shot decomposition can be suboptimal by as much as 2.3X for real mask shapes and by 6X for generated benchmarks.Extreme ultraviolet (EUV) lithography, a front-runner to replace the incumbent 193nm lithography, suffers from hard-to-repair mask blank defects. To mitigate these defects, we propose a defect avoidance method based on random walk and gradient descent that can allow mask makers to use masks with even 30 defects without any significant yield impact for a 14nm polysilicon layer of a design. However, at sub-10nm technology node, tight CD tolerances and dense layouts would make the task of using a defective mask blank challenging. To aid the design of EUV layouts that are robust to mask defects, we propose a new metric called critical density, which can quickly evaluate the robustness of EUV layouts. Using this metric, we show that regularity actually reduces the ability of EUV layouts to tolerate mask defects.