Mask inspection

About: Mask inspection is a research topic. Over the lifetime, 1072 publications have been published within this topic receiving 8696 citations.

Evaluation of printability and inspection of phase defects on hidden-shifter alternating phase-shift masks

Abstract: Inspection and repair of defects represent some of the challenges for the fabrication of 'defect-free' alternating phase-shift masks needed for performance improvements in patterning the polysilicon gate layer of integrated circuit devices. Inspection, metrology, repair, and printability of defects on dark-field alternating phase-shift masks used in dual exposure processes for polysilicon gate layer patterning are discussed in this study. The impact of phase and chrome defects on photoresist features printed at an exposure wavelength of 248 nm is evaluated and compared to the defect signals measured on a mask inspection tool operating at 364 nm. Experimental data on printability and inspection of programmed glass defects with several different phase errors as well as programmed chrome defects are compared to simulations. The effects of the exposure tool focus conditions on phase defect printability are discussed in detail. Phase defect contrast enhancement mechanisms that may enable improvements in phase defect detection during mask inspection using conventional inspection tools are also addressed. Finally, successful repairs of real glass bump defects are demonstrated.

Development and characterization of a thinner binary mask absorber for 22-nm node and beyond

Abstract: The lithography challenges posed by the 22 nm node continue to place stringent requirements on photomasks. The dimensions of the mask features continue to shrink more deeply into the sub-wavelength scale. In this regime residual mask electromagnetic field (EMF) effects due to mask topography can degrade the imaging performance of critical mask patterns by degrading the common lithography process window and by magnifying the impact of mask errors or MEEF. Based on this, an effort to reduce the mask topography effect by decreasing the thickness of the mask absorber was conducted. In this paper, we will describe the results of our effort to develop and characterize a binary mask substrate with an absorber that is approximately 20-25% thinner than the absorber on the current Opaque MoSi on Glass (OMOG) binary mask substrate. For expediency, the thin absorber development effort focused on using existing absorber materials and deposition methods. It was found that significant changes in film composition and structure were needed to obtain a substantially thinner blank while maintaining an optical density of 3.0 at 193 nm. Consequently, numerous studies to assess the mask making performance of the thinner absorber material were required and will be described. During these studies several significant mask making advantages of the thin absorber were discovered. The lower film stress and thickness of the new absorber resulted in improved mask flatness and up to a 60% reduction in process-induced mask pattern placement change. Improved cleaning durability was another benefit. Furthermore, the improved EMF performance of the thinner absorber [1] was found to have the potential to relieve mask manufacturing constraints on minimum opaque assist feature size and opaque corner to corner gap. Based on the results of evaluations performed to date, the thinner absorber has been found to be suitable for use for fabricating masks for the 22 nm node and beyond.

Modeling OPC complexity for design for manufacturability

Abstract: Increasing design complexity in sub-90nm designs results in increased mask complexity and cost. Resolution enhancement techniques (RET) such as assist feature addition, phase shifting (attenuated PSM) and aggressive optical proximity correction (OPC) help in preserving feature fidelity in silicon but increase mask complexity and cost. Data volume increase with rise in mask complexity is becoming prohibitive for manufacturing. Mask cost is determined by mask write time and mask inspection time, which are directly related to the complexity of features printed on the mask. Aggressive RET increase complexity by adding assist features and by modifying existing features. Passing design intent to OPC has been identified as a solution for reducing mask complexity and cost in several recent works 2,3,4 . The goal of design-aware OPC is to relax OPC tolerances of layout features to minimize mask cost, without sacrificing parametric yield. To convey optimal OPC tolerances for manufacturing, design optimization should drive OPC tolerance optimization using models of mask cost for devices and wires. Design optimization should be aware of impact of OPC correction levels on mask cost and performance of the design. This work introduces mask cost characterization (MCC) that quantifies OPC complexity, measured in terms of fracture count of the mask, for different OPC tolerances. MCC with different OPC tolerances is a critical step in linking design and manufacturing. In this paper, we present a MCC methodology that provides models of fracture count of standard cells and wire patterns for use in design optimization. MCC cannot be performed by designers as they do not have access to foundry OPC recipes and RET tools. To build a fracture count model, we perform OPC and fracturing on a limited set of standard cells and wire configurations with all tolerance combinations. Separately, we identify the characteristics of the layout that impact fracture count. Based on the fracture count (FC) data from OPC and mask data preparation runs, we build models of FC as function of OPC tolerances and layout parameters.

Improvement of a DUV mask inspection tool to hand over the baton for next-generation tool smoothly

Abstract: Various technologies such as multiple patterning (MP) are being developed to extend the current DUV optical lithography to deal with the delay of next generation lithography such as EUV and NIL Likewise, it is necessary to continue to develop technologies for mask inspection tools for masks fabricated for the DUV optical lithography so that they can be appropriately inspected, until the next generation EB or EUV actinic inspection tools is put into practical use To fabricate 1x nm devices with the present lithography process, the industry will likely further extend double patterning (DP) to multiple patterning (MP) For MP, the requirements for the inspection sensitivity of traditional defects such as intrusions or extrusions do not change much, but those for CD control and overlay tolerances will become more critical In this paper, we will discuss the main features of NPI-7000, a DUV based mask inspection tool for the 1x nm node devices, and our challenges in enhancing the CD error sensitivities to enable the inspection of masks

Sub-0.18-μm line/space lithography using 248-nm scanners and assisting feature OPC masks

Abstract: The downscaling of critical dimensions (CD) in semiconductor circuits has been pushing photolithography to print features below the wavelength of the light source. However, severe proximity effect and small DOF for isolated lines have brought challenges to sub-0.18 micrometer lithography in manufacturing using 248 nm scanners. To improve proximity effect and DOF for isolated lines, assisting features (AF) on masks are considered. However, the practical application of this technique has been limited because of difficulties in mask fabrication. In this paper, we discuss items that concern both photolithographers and mask-makers as AF is applied in manufacturing. These items include mask error factor (MEF), depth of focus (DOF) improvement, AF line width control, lithographic impact caused by the drift of the mean value of mask CD, defect printability in resist, and defect sensitivity during mask inspection.