Showing papers on "Master clock published in 1969"

Digital memory area correlation tracker

Abstract: A digital tracker which provides a continuous display of the area tracked mprising a delay line coupled in circuit with a comparator, a video digitizer and a sensor. The digital tracker further comprises circuit means connected between the delay line and the sensor for deriving an error correction signal in response to any mismatch between the present, delayed video scene and the reference scene, stored in the delay line. A staircase raster generator which can be positively synchronized with the delay line through the use of a common master clock is used as the sensor and the delay line is a shift register which enables any desired bit of the stored signal to be available for use at any time.

Communications system with frequency and time division techniques

Abstract: A communication system for a substantial number of subscribers is shown having random access capabilities without the requirement for the usual central exchange. The system uses a frequency division scheme for separating the several communication information channels. The individual subscriber units are interconnected as by means of one or more wires which are also connected to a master clock which continually generates time division digital information consisting of a plurality of pulses and unused time spaces (ones and zeros) including binary circuit code information and synchronizing pulses. A relatively limited band width is required for carrying this control information which is substantially displaced in frequency from the band containing the several communication information channels. These channels are generated by means of a frequency synthesizer in each of the subscriber units, each of which continually monitors the digital control information to determine whether its address is being called and the circuit code representing the channel of the incoming call. Similarly, outgoing calls are initiated by picking up a headset at the subscriber unit which causes an unused channel to be selected, inserting its circuit code into the digital stream and causing the frequency synthesizer in responding to this code to generate the corresponding carrier frequency. The audio information is then converted to single side band (or other) modulation of the particular carrier frequency signal.

Video data display system

Abstract: A data display system is disclosed utilizing a conventional television receiver for selectively displaying groups of characters comprising stored data and particularly data of the general type and quantity conventionally recorded on the usual computer punch cards. The video display system is adapted for transferring data already recorded or being recorded in a memory storage unit to the television antenna terminals or video inputs of a monitor without requiring any modification of the receiver or monitor. The display system operates with a master clock or timer circuit which facilitates the read out and conversion of the information from the coded memory data to a video bit stream. The master clock provides standard synchronizing signals for the video display and these same signals also are used to synchronize the several subcircuits utilized in the data transfer from a data memory to the video display.

Variable multiphase clock system

Abstract: A multiphase clock system operated from a master clock oscillator which is capable of providing a plurality of clock signals having remotely controllable variable pulsewidths as well as mutually variable phase shifts utilizing J-K flip-flop integrated circuit components of the emitter coupled current mode logic type in combination with field effect transistors of the MOSFET type which are operated as voltage controlled variable resistances and suitable timing capacitors for transforming integrated circuit J-K flip-flops into monostable multivibrators The invention herein described was made in the course of contract with the Department of the Army under contract No DAAB03-67-A-0010

Synchronizing clock system

Abstract: In a data processing system, apparatus for synchronizing a slave clock in an input/output device with a master clock in a central processing unit. A set of clock signals from a CPU are received in parallel, converted to serial and pulses are generated in response to the leading and trailing edge of each of the series of signals. The series of pulses is then delayed and shaped to drive a slaved I/O clock. A delay line is adjusted so that the total equivalent system delay is equal to an integral number of CPU pulse durations.

Improvements in and relating to electrical signalling systems

Abstract: 1,149,752. Selective signalling. F. C. ROBINSON & PARTNERS Ltd. 6 Sept., 1966 [11 June, 1965; 13 Sept., 1965 (2)], Nos. 24852/65, 39035/65 and 39036/65. Heading G4H. In a signalling system a plurality of pairs of transmitter units and receiver units distributed between a local and a remote station are coupled together sequentially over a single channel in a time-division manner and the system is characterized in that (1) at the local station a master clock advances an eight-stage master binary, counter, the eight-bit output from which sequentially readies the units at the local station, (2) at the remote station an eight-stage slave binary counter is advanced by clock-pulses transmitted from the master clock so as to ready sequentially the units at the remote station and (3) synchronization is maintained by causing the master counter to inhibit the transmission to the remote station of the last eight clock-pulses in each cycle of 256 clock-pulses determined by the master counter, which synchronizing gap when detected at the remote station causes the slave counter to be reset to zero in readiness for the start of the next cycle. As described each transmitter can transmit a single bit in accordance with the position of a switch contact and each receiver controls an indicating lamp via a relay which could also control remote machinery. The system described is particularly adapted for use between a mine and the surface in that a plurality of failsafe features are incorporated. Outline circuits of conventional transistor gating and switching units are given.

A System for Controlling Secondary Clocks from a Master Clock Location.

Abstract: 1,170,969. Electric clocks. EDWARDS CO. Inc. June 28, 1967 [Dec.27, 1966], No.29761/67. Heading G3T. In a system for controlling a secondary clock by a master clock 10, the secondary clock has first resetting means 15 and second resetting means, the first resetting means being operable to drive the secondary clock a variable amount depending on the duration of a power failure and the second resetting means being operable at an instant determined by the master clock to drive the secondary clock to a predetermined setting, switching means comprising a relay RE and a contact 45 being controllable by the master clock to render the first or the second resetting means operative. A device 11 which registers the length of time that power is cut off is associated with the master clock so that in the event of a power failure a switch contact 13 is made and a contact 12 broken. When the power is restored, power is supplied to both the reset drive motor 15 and a normal drive motor 14, the motor 15 driving a gear 28 of a differential 28-30 to add to the normal rate of rotation of a minute hand M. The normal rotation of the minute hand M is provided by the gear 29 rotated by the motor 14, the gear 29 rotating a minutes sleeve 27 by rotation of a spider sleeve 31. The reset motor 15 drives the gear 28 at a speed greater than time keeping speed and at the same time the device 11 is driven in reverse at a similar speed until it shows a zero indication, the contact 13 then being opened. During the resetting operation, the reset motor 15 is energized through the contact 45 of the relay RE, a reset solenoid RS therefore remaining de-energized. The master clock 10 is also reset by operating its reset motor at the same time as the secondary clock motor is operated. To provide an hourly resetting of the secondary clock, a clutch 49 is secured by a pin 55 to a clutch disc 48. A detent 49a is held away from a toothed wheel SEC by the pressure on the clutch of an arm 21a of a spring biased lever 21 pivoted at 60. At a given time, for example 58 minutes past each hour, the master clock energizes a relay 1HR so that a contact 18 is opened to cut off the A.C. supply to the relay RE and a D.C. pulse is applied to a wire 20 through a contact 63. The contact 45 therefore switches over to enable the reset solenoid RS to be energized. The D.C. pulse causes the solenoid to rotate the lever 21 until a detent 65 on the lever engages a slot 66 on a latch 22. The movement of the arm 21a allows the detent 49a of the spring loaded clutch to engage the wheel SEC which is driven at the rate of the seconds hand S. The clutch disc 48 is therefore quickly rotated and the end 50a of a spring 50 engages a slot 53 in a disc 52, after one revolution of the disc 48 if the secondary clock is on time or before one revolution of the secondary clock is slow. A detent 21c of the lever is raised out of a notch 67 of the disc 48 to allow rotation of the disc 48 and a projecting portion of the clutch 49 raises the latch 22 away from the detent 65 of the arm 21a about eight seconds after the start of the hourly correction to position the lever for a twelve hour correction. A stop 69 on the lever co-operates with a detent 68 to maintain the seconds hand in the 60 second position during hourly and twelve hourly resetting operations. Toprovide a correction once every twelve hours, a second pulse is transmitted by closure of a contact 63a by the master clock about eight seconds after the first pulse. Since the detent 65 is disengaged from the latch 22, the solenoid RS can fully actuate the lever 21. A detent 70 on the lever 21 therefore engages a notch 71 in a latch 23 pivoted at 72 so that, since the clutch 49 cannot be disengaged from the wheel SEC whilst the latch 23 engages the lever 21, the clutch makes several revolutions for the twelve hour correction until the hour hand H indicates the same hour as the master clock. At the termination of the correction the latch 23 engages a pin 74 on the hour wheel HR to disengage the detent 70 from the notch 71 thus permitting the returning of the resetting devices to their normal positions on rotation of the disc 48 to the position shown in Fig.1.

Frequency control requirements for the MALLARD communication system

Abstract: The results of work so far performed in the area of synchronization techniques have been promising. It was found that of the four techniques investigated, i.e., master-slave, bit stuffing, frequency averaging and independent atomic clocks, frequency averaging and independent atomic clocks might have application in a future field army communication network.

Voltage variable clock oscillator

Abstract: A clock oscillator which can be used as a master clock in a digital system comprising an emitter coupled logic gate operated as a free running bistable device by means of a resistancecapacitance network coupled thereto and which is alternately charged and discharged at the desired output frequency and wherein the resistive element in the network is comprised of a metal oxide silicon field effect transistor (MOSFET) the drainsource resistance of which is selectively varied by means of a potential applied to the gate thereof from an externally controlled source for establishing a desired frequency of operation.

Mass-Frequency Effect on VLF and Portable Clock Comparisons of Atomic Frequency Standards

Abstract: : A recent publication, 'The effect of mass on frequency' by SADEH, KNOWLES, and AU, describes two experiments in which the frequency of electromagnetic radiation was apparently decreased due to the proximity of a large mass. If such is actually the case, then all comparisons of frequency standards by means of radio transmissions should be corrected for this effect. In addition all remote clocks synchronized via VLF transmissions to a distant master clock would actually run slow with respect to the master clock. Our investigation indicates that if any disagreement between radio and flying clock measurements of frequency exists, it is, at most, about an order of magnitude smaller than that predicted by SADEH, KNOWLES, et al. It thus appears that there is good reason to doubt the suggestion that the frequency of electromagnetic radiation is altered by passage near to large masses. (Author)