Showing papers on "Master clock published in 1973"
Patent•
06 Apr 1973
TL;DR: In this article, the system clock is designed in such a way that a single failure of any kind will not prevent the generation of clock pulses, and the clock card is wired for redundant operation.
Abstract: The system clock of the present invention is designed in such a manner that it is ''''fail-safe,'''' and a single failure of any kind will not prevent generation of clock pulses. More particularly, the system clock consists of two identical clock cards wired for redundant operation. One clock card functions as the main system clock (MSC), and the other functions as the standby system clock (SSC). Clock pulses normally are provided by the MSC to the appropriate subsystem timing generators, however, if a fault develops in the MSC, the pulse output of the MSC is inhibited and the function of providing pulses is transferred to the SSC. The transfer feature always takes place when an ALARM lead on the MSC goes to a logic one.
41 citations
Patent•
IBM1
TL;DR: In this article, the carry pulses from all time-of-day (TOD) clocks are combined in an OR circuit with each clock to provide common carry pulses for synchronizing each TOD clock in the system.
Abstract: Circuits and method for synchronizing and checking a plurality of time-of-day (TOD) clocks in a multiprocessing system. Unique hardware synchronizes the low order part of the TOD clocks and a unique method synchronizes the high order part in the same clocks by using carry pulses derived from an intermediate bit position in each TOD clock. The carry pulses from all TOD clocks are combined in an OR circuit with each clock to provide common carry pulses for synchronizing each TOD clock in the system.
33 citations
Patent•
17 Jan 1973
TL;DR: In this article, a master clock at a central station transmits time indicating signals from a slave clock to a peripheral station via a two-wire line as binary values represented by pulsed duration modulated signals.
Abstract: Time indicating signals are transmitted from a master clock at a central station to a slave clock at a peripheral station via a two-wire line as binary values represented by pulsed duration modulated signals. Clock, coding and transmitting circuitry at the central station are normally energized by an a.c. power line source. In the event of failure of the a.c. power source, the clock is energized by a battery and transmission from the central station to the remote station ceases. On resumption of power, the first transmission from the central station to the peripheral station enables the slave clock to provide a correct time indication. Transmission can be over any existing lines interconnecting the central and peripheral stations, such as a 60-cycle power line, television cable, or a telephone link. If television cable or 60-cycle line is employed, the presence and absence of voltage is indicated by frequency shift keying transmission. Transmission of the time indication requires only a fraction of the total transmission time, and is constant for all time indications, whereby other data signals can be transmitted between the central and peripheral stations.
24 citations
Patent•
05 Jan 1973
TL;DR: In this article, a clock highway interconnects the transmitters and receivers and to which the clock number signals are applied, and a comparison network at each transmitter and receiver which sequentially compares the clock numbers signals on the clock highway with a number at the transmitter or receiver for the purpose of selecting the time slot during which each transmitter operates to transmit and receive audio information, respectively, over an audio information highway.
Abstract: A time-division multiplex system including multiple transmitters and receivers; a master clock cyclically generating once per clock frame a series of different clock numbers in the form of differing sequences of binary signals, each clock number constituting a different time slot; a clock highway interconnecting the transmitters and receivers and to which the clock number signals are applied; a comparison network at each transmitter and receiver which sequentially compares the clock number signals on the clock highway with a number at the transmitter and receiver for the purpose of selecting the time slot during which each transmitter and receiver operates to transmit and receive audio information, respectively, over an audio information highway which also interconnects the transmitters and receivers.
21 citations
Patent•
28 Mar 1973
TL;DR: In this paper, a master clock oscillator phase-locked to the incoming signals and a standby clock phase locked to the output of the master clock are used to recover signal signals from an outage of the incoming signal.
Abstract: Clocking signals are recovered from an incoming signal train by a master clock oscillator phase locked to the incoming signals and, in the event of failure of the master clock, by a standby clock similarly phase locked to the incoming signals. When an outage of the incoming signal is detected, or when it is presumed that the incoming signals are being improperly received, both clocks are unlocked from the incoming signals and the standby clock is phase locked to the output of the master. If there is subsequent phase slippage of the standby, it is unlocked from the master and both clocks run free. In one operational sequence, both clocks are again phase locked to the incoming signals if signal reception is restored.
17 citations
Patent•
09 Apr 1973
TL;DR: In this paper, a plurality of slave clocks are controlled and synchronised from a central station which transmits to each slave clock frequent coded signals each of which conveys in coded form complete information as to the time, and possibly also the date, to be displayed by each clock.
Abstract: A plurality of slave clocks are controlled and synchronised from a central station which transmits to each slave clock frequent coded signals each of which conveys in coded form complete information as to the time, and possibly also the date, to be displayed by each slave clock.
12 citations
Patent•
19 Oct 1973
TL;DR: In this paper, a master clock having an oscillator, a divider, a signal shaper, an output amplifier, and power feed either by means of an electric circuit or by a battery at the time of power failure in the circuit is provided.
Abstract: A master clock having an oscillator, a divider, a signal shaper, an output amplifier, and power feed either by means of an electric circuit or by means of a battery at the time of power failure in the circuit. A detector for circuit voltage is provided which upon a fall in circuit voltage switches signals from the output of the divider to an electronic memory. Upon reestablishment of power in the circuit, the time signals are fed out of the memory at an accelerated rate to cause the secondary clocks controlled by the master clock to catch up. It is thus possible to use only a small and inexpensive standby battery for use during power failure.
7 citations
Patent•
09 Mar 1973
TL;DR: In this paper, a ranging signal is transmitted to each of a number of aircraft in turn in response to received interrogation signals, allowing a clock carried by each aircraft to be accurately synchronised with a master clock on the ground to permit the range to be measured precisely.
Abstract: A navigation aiding system primarily for aircraft consists of a number of spaced apart ground stations. A ranging signal is transmitted to each of a number of aircraft in turn in response to received interrogation signals. The system allows a clock carried by each aircraft to be accurately synchronised with a master clock on the ground to permit the range to be measured precisely.
4 citations
01 Jan 1973
TL;DR: In the past year, the increase in Precise Time And Time Interval data to be reduced to the U.S. Naval Observatory Master Clock and the requirement for its quick dissemination has necessitated development of more efficient methods of data handling and reduction.
Abstract: In the past year, the increase in Precise Time And Time Interval data to be reduced to the U.S. Naval Observatory Master Clock and the requirement for its quick dissemination has necessitated development of more efficient methods of data handling and reduction. An outline of the data involved and of the Time Service computerization of these functions is presented.
3 citations
01 Jan 1973
TL;DR: The prototype system for Deep Space Network clock synchronization by VLBI has been demonstrated to operate successfully over intercontinental baselines in a series of experiments between Deep Space Stations at Madrid, Spain, and Goldstone, California.
Abstract: The prototype system for Deep Space Network clock synchronization by VLBI has been demonstrated to operate successfully over intercontinental baselines in a series of experiments between Deep Space Stations at Madrid, Spain, and Goldstone, California. As predicted by analysis and short baseline demonstration, the system achieves reliable synchronization between 26m and 64m antenna stations with 17 and 37K nominal system temperatures using under one million bits of data from each station. Semi-real-time operation is feasible since this small amount of data can be transmitted to JPL and processed within minutes. The system resolution is 50 to 400ns, depending on the amount of data processed and the source intensity. The accuracy is believed to be comparable to the resolution, although it could be independently confirmed to only about 5 microseconds using LORAN C.
1 citations