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Showing papers on "Master clock published in 1980"


Journal ArticleDOI
Debasis Mitra1
TL;DR: A hybrid of two well-known techniques, "mutual synchronization" and "masterslave," offering certain unique advantages for synchronizing the clocks in a digital switching network to a more select group of "master clocks".
Abstract: The paper contains a proposal and an analysis of a hybrid method for synchronizing the clocks in a digital switching network to a more select group of "master clocks." The scheme is a hybrid of two well-known techniques, "mutual synchronization" and "masterslave," offering certain unique advantages. It allows different synchronizing disciplines for the masters (such as the toll switching machines) and the remaining subnetwork (composed, for example, of local switches). We begin by considering an idealized model containing only one master with constant clock frequency. The behavior of the controlled frequencies in the subnetwork is described by linear delay-differential equations with the delays determined by distances separating switches. We show that in all cases all clocks in the subnetwork approach in steady state the master clock frequency. Considerable emphasis is placed on the rate of synchronization, as determined by the principal root, the root with largest real part, of the characteristic function of the differential equations. The idealized model is extended in stages. First we consider the effects of many masters with constant but possibly nonidentical frequencies and show that the steady state frequencies in the subnetwork are narrowly bounded. Next, we allow clock drift and the master clocks to fluctuate about nominal centers with given tolerances. An expression for the residual steady-state departures from perfect synchronization shows the tradeoff between transient and stead-state behavior. Finally, two illustrative examples are numerically solved.

35 citations


Patent
25 Jun 1980
TL;DR: In this paper, a method for synchronizing a master clock and a remote slave clock which nominally has the same pulse frequency but may be out of time-phase was proposed.
Abstract: A method for synchronizing a master clock and a remote slave clock which nominally has the same pulse frequency but may be out of time-phase comprising transmitting a master pulse to the slave, measuring the time delay, Δτ, between the received pulse and the nearest succeeding (in time) slave pulse, delaying the latter slave pulse by Δτ to provide a conjugate slave pulse, transmitting the conjugate pulse to the master station and measuring the time difference Δ between time of reception of the conjugate pulse and time of generation of the original master pulse. The time Δ is equal to twice the error between the master and slave pulses. The process can also be done at the slave station if the slave pulse is transmitted to the master and a conjugate-phase master pulse is retransmitted to the slave where the measurement is accomplished. The phase of the slave pulse can then be adjusted by Δ/2 to synchronize it with the master pulse.

32 citations


Patent
28 Jul 1980
TL;DR: In this article, the authors present an apparatus for stopping timing circuits in a central processing unit and for restarting the timing circuits to produce timing signals synchronized with an asynchronous external signal, where the continuous running master clock is employed to generate a plurality of phase related new clock signals.
Abstract: The present apparatus includes logic for stopping timing circuits in a central processing unit and for restarting the timing circuits to produce timing signals synchronized with an asynchronous external signal. The continuous running master clock of the central processing unit is employed to generate a plurality of phase related new clock signals. Logic circuit means are provided to sequentially attempt to employ each of the new clock signals until one of the new clock signals synchronizes with the external asynchronous signal. The logic circuit means include circuits for selecting a new clock signal to be employed by the timing circuits of the central processing unit so that the new clock is synchronized with the external asynchronous signal.

21 citations


Patent
17 Jun 1980
TL;DR: In this article, a data capture circuit for a logic state analyzer includes a qualifier pattern comparator circuit that responds to a collection of input qualifier signals by producing a number of qualifier pattern signals each representative of the occurrence of a preselectable pattern in the input qualified signals.
Abstract: A data capture circuit for a logic state analyzer includes a qualifier pattern comparator circuit that responds to a collection of input qualifier signals by producing a number of qualifier pattern signals each representative of the occurrence of a preselectable pattern in the input qualified signals. A like number of clock detection circuits each responds separately to the values of separate clock signals by producing separate qualified clock signals, each of the like number of which represents the simultaneous occurrence of a preselected transition in each particular clock signal and of a qualifier pattern signal associated with that clock signal. The several separate qualified clock signals generally occur at separate times, and each is used to individually capture into several temporary storage registers separate collections of data signal values occurring at those separate times. A master clock selection means allows the user to designate as a master clock signal a qualified clock signal that is expected to occur not earlier in sequence than the others. The master clock signal causes transfer of the contents of the temporary storage registers into intermediate storage registers whose outputs are then merged and combined by subsequent and simultaneous forwarding as a single parallel entity to the main data memory of the logic state analyzer, while at the same time the temporary storage registers are freed to capture fresh data.

15 citations


Patent
12 Feb 1980
TL;DR: In this article, a phase comparison of the two clocks (T ', T") is made, at (in the order of one intermediate clock period coming phase difference between the two clock T', T ) is "shortened by an intermediate clock periods or longer".
Abstract: having Direction for generating two with one another at most limited phase differences clocks (T ', T ") by doubly provided, in each case by a master clock (M', M"), servo-synchronized clock generator (CCG ', CCG ") generate this first respectively a higher-frequency intermediate clock (H' , H "), which is then turned down to the desired clock frequency, wherein a phase comparison of the two clocks (T ', T") is made, at (in the order of one intermediate clock period coming phase difference between the two clocks T', T ") is "shortened by an intermediate clock period or longer. This is done with the aid of the intermediate clock generators (Z-PD-VCO) downstream digital Taktuntersetzungs- and phase synchronization circuit (UVR ', UVR one clock period of a clock (T)"). is connected such Taktuntersetzungs- and phase synchronization circuit (UVR ") has a Zwischentakt- frequency halving stage which is connected downstream via a Phasenumtaster a further frequency divider and to which a phase comparing circuit for phase comparison between guided clock (T") and leading clock (T ') ,

8 citations


Patent
07 Nov 1980
TL;DR: In this paper, the authors proposed a scheme to select the recording time and audio quality freely, by changing the sampling frequency according to the amount of information recordable at the changeover of tape speed.
Abstract: PURPOSE:To enable to select the recording time and audio quality freely, by changing the sampling frequency according to the amount of information recordable at the change-over of tape speed. CONSTITUTION:The tape running speed variable circuit is constituted with the master clock generating circuit 31, frequency dividing circuit 30, servo circuit 29, and capstan motor 28. The master clock suitably frequency-divided at the circuit 30 is fed to the sample hold circuits 5, 6 and time axis conversion circuit 11. When the bit rate of recording signal is kept as it is and the running speed is made slow, the recording wave length lambda is smaller. Then, the bit rate is lowered to obtain excellent output. Accordingly, when the tape speed is halved, the clock is halved at the clock recording. When the master clock is selected with the switch SW1, the interlocked SW2 is also operated and the cut-off frequency of LPF is switched. Thus, since the tape speed, sampling frequency, and recording clock can be changed by only changing the master clock, the recording time and sound quality can be selected.

5 citations


Patent
14 Aug 1980
TL;DR: In this paper, an electronically controlled data recording clock is used for logging work periods and absences of personnel in a production control system for automatic logging of work periods over a predetermined period eg one month.
Abstract: An electronically controlled data recording clock is used for logging work periods and absences of personnel In particular the system allows automatic logging of work periods over a predetermined period eg one month The system runs from a master clock pulse generator ie crystal controlled oscillator This provides signals over a logic unit to a variety of peripherals; display, printer, clock and calendar and an interfacer for connection to a mains production control system A two-way bus connects an adder-subtractor with a random access memory The memory is accessed by the operator's identification card and allows start and finish times to be automatically logged Operating with the adder subtractor, the system allows cumulative times to be evaluated and stored

4 citations


Patent
29 Mar 1980
TL;DR: In this article, a low-speed clock break detection circuit with only digital elements is presented, where high-speed reference clocks and low-time frame clocks are sent from a master clock unit.
Abstract: PURPOSE:To reduce a cost and a space by constituting a low-speed clock break detection circuit with only digital elements by utlizing points where high-speed reference clocks and low-speed frame clocks are sent from a master clock unit. CONSTITUTION:The existence of coming of frame clocks are stored in shift registers 72 and 73 by anti-phase clocks of the reference input, which pass through gate 71, while shifting them successively. The output is inputted to exclusive OR gate 74, so that the output of reference input 2-clock components gate 74 becomes high- level after the frame clock comes. At this time, counter 78 is reset and does not reach 1023; however, when even one of frame clocks lacks, counter 75 reaches 1023, and a pulse appears at the 1023 output of decoder 76 to set a flip flop through OR gate 79, and alarm is indicated to software similarly to reference clock break.

2 citations


Patent
16 May 1980
TL;DR: In this article, a digital computer has a master clock for generating master clock pulses at a first frequency and a counter for counting secondary clock pulses having a frequency less than the frequency of the master clock.
Abstract: A digital computer has a master clock for generating master clock pulses at a first frequency and has a counter for counting secondary clock pulses having a frequency less than the frequency of the master clock pulses. The secondary clock pulses are counted and used in the assignment of real times to bytes of input data, and in the comparison of real times with desired output times assigned to binary output data.The input data preferably is placed in a FIFO stack and the output data in a self-sorting stack. The sorting in the output stack occurs between changes in count in the counter con-taining the secondary clock pulses.

2 citations


Patent
16 May 1980
TL;DR: In this article, a driver circuit for time unit with electronic circuits such as photo coupler and transistors was proposed. But the driver circuit was not used to increase the reliability in comparison with the relay circuit consisting of relay circuits.
Abstract: PURPOSE:To increase the reliability in comparison with the driver circuit consisting of relay circuits, by constituting the driver circuit for time unit with electronic circuits such as photo coupler and transistors. CONSTITUTION:The signal A of the master clock 1 is converted into the signals C,B signals to turn off the transistors 17,18 alternately with the conversion circuit 2. When the transistor 18 is ON, the remote control terminal RC of the second switching regulator 12 is closed to the potential of the - terminal with the photo coupler 16 to turn off the switching regulator 12. When the transistor 18 is turned off, the output a of the switching regulator 12 produces a positive voltage. Similarly, negative voltage is produced from the first switching regulator 11 to drive the slave clocks with the polarity pulse.

1 citations


04 Feb 1980
TL;DR: In this article, the NTS-2 was successfully launched on June 23, 1977, and maneuvered into a preassigned constellation position as part of the Phase I demonstration for NAVSTAR GPS.
Abstract: : NTS-2 was successfully launched on June 23, 1977, and maneuvered into a preassigned constellation position as part of the Phase I demonstration for NAVSTAR GPS. NTS-2 carried two cesium frequency standards. Precise timing signals, derived from one of the cesium frequency standards, were continuously transmitted. Time differences were then measured by the NTS ground stations. The NTS-2 time differences were used to fit an orbit to the observations over a (typical) 6-day span. Clock offsets were then obtained using the reference orbit and other measured parameters; these clock offsets were then used to estimate the cesium frequency stability. Estimates of frequency stability have been obtained for one of the two cesium frequency standards for sample times of from 1 to 9 days. Analysis of the results indicates a white frequency noise of 0.00000000011 divided by the square root of the sample time in days for sample times of 1 to 5 days with a flicker floor of 0.00000000000017 for sample times from 5 to 9 days. For sample times of 10 days or longer an attempt was made to check for cesium aging with respect to the Universal Time Coordinated of Master Clock 1 at the United States Naval Observatory. The value for aging was not significantly different from zero; that is, no cesium aging was found.

Patent
22 Aug 1980
TL;DR: In this paper, a master clock is controlled by a single master clock with a rhythm signal on the same conductors, which is used to suppress the rhythm signal when other clock signals appear on the line.
Abstract: The electrical system for the control of slave clocks from a single master clock includes the transmission of coded signals with a rhythm signal on the same conductors. The circuit producing these signals suppresses the rhythm signal when other clock signals appear on the line. The circuits receiving these signals include absence of the rhythm signal the whole coded message is invalidated. The coded message to be sent includes the tens and units digits or the hour, minutes and seconds as well as data information in a binary coded decimal form. The binary signals are transmitted in a split-phase mode. The clock system may be used in conjuction with an existing system but by using the rhythm signal, the slave clocks are not disturbed by the appearance of other clock pulses on the transmission lines.