Showing papers on "Master clock published in 1981"

Data processing system with processors having different processing speeds sharing a common bus

Abstract: There is disclosed a data processing system comprising a plurality of processors having different processing speeds and connected with a synchronous common bus, the processors being able to access a common memory connected with the common bus. A high frequency master clock signal generating means is provided in common for the processors of the system and the respective processors can be operated with the associated different machine cycles determined in accordance with the corresponding different processing speeds by frequency-dividing the master clock signal. In addition, each processor can be operated with different machine cycles depending on its operations.

Synchronous data bus with automatically variable data rate

Abstract: A digital data bus system operating asynchronously with a fixed clock and having a automatically variable data rate selected by sending and receiving units. A master clock is generated by a master controller and distributed to one or more peripheral controllers of the data bus system through a single clock line. In addition to address/data lines, a single handshake hold signal is shared by the master and all peripheral controllers. All data transfers are executed on a bus clock pulse and data transfer rate is controlled by the sending and receiving units through operation of the hold signal. A receiving unit not ready to receive information on the bus will assert hold signal on hold signal line and the transmitting unit will maintain the information presently on the bus during each clock period in of which hold signal is asserted. Data transfer is executed on next clock pulse after termination of hold signal. All information transfers are thereby synchronous with the single frequency bus clock, but data transfer rate is variable and automatically determined by the sending and receiving units.

Frequency-dividing circuit

Abstract: A frequency-dividing circuit comprises an asynchronous counter having a plurality of one-half frequency-dividers connected in series in a plurality of stages in which a master clock signal is applied to an input terminal of the initial stage, for asynchronously producing output signals of each of the one-half frequency-dividers, where the asynchronous counter is set with a preset data n (n is an integer) which is preset according to a desired frequency-dividing ratio when a load pulse is applied, a coincidence detection circuit for detecting the coincidence of a plurality of outputs supplied from the asynchronous counter, and a frequency-divided output signal and load pulse generation circuit supplied with the master clock signal and an output signal of the coincidence detection circuit, for generating a frequency-divided output signal and a load pulse The frequency-divided output signal and load pulse generation circuit supplies a load pulse to the asynchronous counter

Remote correlation of sequence of events

Abstract: A method for correlating in a digital data acquisition system the time sequence of a group of events at locations remote from the master station. The method corrects the time tags on the events record for the signal transmission time between the master and remote stations and also takes into account the turnaround time at the remote station. In addition, compensation is made for the drift of the remote clocks with reference to the master clock.

Clock control for digital computer

Abstract: A master clock for a microprogrammed digital computer generates output pulses whose separation in time can be varied in response to each microinstruction or to a process-related signal. The output pulses are formed from basic time units from a clock generator which are combined, in digital logic circuitry, to form a minimum time interval and supplemented, under command, with the necessary additional time units to delay the next output pulse by the required amount of time.

Improvements in or relating to wafer scale integrated circuits

Abstract: A wafer scale integrated circuit wherein a plurality of data processing cells (12), such as memory cells, all on a single wafer (10) are connectable into a chain (18) starting at a port (14) for passing data away from the port (16) via a serial connection of forward registers (38) and back towards the port (14) via a serial connection of reverse registers (40), has a reduced risk of any individual, otherwise perfect cell (12) being non-functional as a result of a failure elsewhere on the wafer (10) of an associated Global line by achieving a reduction in the number of Global lines required by providing a data shift controlling master clock signal which is transferred between the cells (12) in parallel with the data and is used to operate a multiple clock generator (46) in each cell.

Signal transmission system with time sequence control - measures unspecified interval between signal recognition and transmission to central processor

Abstract: The signal transmission system allows the central processor to place the signal from the detection circuit in the correct time raster sequence. The detection circuit incorporates a counter which records the time interval between recognition of the signal and its subsequent transmission to the central processor in response to a call signal. The contents of this counter are transmitted ot the central processor together with the signal and subtracted by the processor from the contents of a control counter, both counters indexed by the same clock frequency. The result of this subtraction allows the signal to be correctly inserted in the time raster sequence for the control processor. Pref. both counters comprise microsecond counters. The system is employed with a process control circuit allowing the instant of detected signal values to be measured precisely or for a clock synchronisation circuit, to allow precise measurement of any differences in the indicated time of slave clocks and a master clock.

Pulse code modulation signal recording and reproducing

Abstract: A pulse code modulation (PCM) signal recording system includes a first signal processor (1 to 7) for processing a recording signal into a predetermined PCM signal, a second signal processor (18 to 24) for processing a reproduced PCM signal into a recording signal, a first clock signal generator (9) generating a master clock signal, a second clock signal generator (12 to 14) generating at least one recording clock signal from the master clock signal, the recording clock signal being supplied to the first signal processor (1 to 7), a third clock signal generator (27) generating at least one reproducing clock signal from the master clock signal, the reproducing clock signal being supplied to the second signal processor (18 to 24), a comparator (32) digitally comparing the phases of the second and third clock signals and producing a control signal, and a controller (29) receiving the control signal and controlling the second or third clock signal so that they are synchronized.

Circuit arrangement for clock conversion

Abstract: The invention relates to a circuit arrangement for converting a clock with the frequency f1 into a clock with the frequency At clock frequencies in the MHz range, it is no longer possible to start from a master clock which is higher by a multiple than the required clock in the clock conversion. It is therefore proposed to divide the original clock with the frequency f1 by the factor m and logically to combine the resultant pulse sequence with the original pulse sequence. The required frequency f2 is then filtered out by means of a narrow-band filter from the frequency mixture of the logically combined pulse sequence.

Time synchronization control system

Abstract: PURPOSE:To improve the absolute time precision of sample values in each observation station, by time-synchronizing the internal counter of each observation station with the internal counter of the center station in the earthquake observation system and so on CONSTITUTION:Center station 1 is provided with internal counter 12 which generates the internal clock synchronized with the clock of master clock generator 11 corrected by the absolute time, and observation station 2 is provided with internal counter 22 which generates internal clocks controlled by variable frequency oscillator 21 Counter 22 generates a signal of the same period as the clock from counter 12 The frame signal is transmitted from station 2 at internal clock time (o), and the arrival time is counted on a basis of the internal clock by time measuring circuit 17 in station 1, and the lapse time from time (o) is obtained, and the local frame signal is transmitted the lapse time before from time (o) In station 2, the frame signal from station 1 is counted on the basis of the local internal clock by time measuring circuit 27, and oscillator 21 is so controlled that the 1/2 of the lapse time from time (o) may be a prescribed value, and the time error between internal counters of both stations is set to zero

System for information transmission

Abstract: PURPOSE:To make the information transmission high-speed without restricted by a low-speed function part, by providing high-speed and low-speed local station internal bus clocks and by using selectively two clocks for access objects. CONSTITUTION:When a main processor 4 accesses an input/output part 9, an internal low-speed bus clock 22 is used as an internal bus clock 24 to operate an internal bus 10. When the main processor 4 accesses other function parts, an internal high-speed bus clock 23 is used as the clock 24 to operate the internal bus 10. Low-speed and high-speed bus clocks are switched by a clock selecting signal 25 issued from the processor 4. Thus, the information transmission becomes high-speed without restricted by the access to the input/output part 9 of a considerably long access time.

Optical type hand scanner

Abstract: PURPOSE:To obtain the video signal with good quality and to improve the operativity, by providing the means producing the signal driving the CCD and relating member in the hand scanner, in using CCD as photoelectric conversion element. CONSTITUTION:The photoelectric conversion element CCD4 in the hand scanner 1 requires 4-phase clock pulse and the storage and readout sections connected to the CCD respectively require the same clock pulse. The drive circuit 10 produced the pulse and it is provided in the hand scanner 1. The drive circuit 10 only receives the master clock from the signal processing section 11 and it produces the 4-phase clock pulse required by taking this clock as the reference and supplies to each section.

Master clock repeater for the cambridge digital communication ring

Abstract: Digital synchronisation in the repeaters of the Cambridge ring is achieved through the use of phase-locked loops A practical solution to the resulting problem of frequency stability, based on the dynamic adjustment of ring length, is presented A repeater which implements this solution has been built and tested in the Cambridge ring

Frame synchronizing circuit

Abstract: PURPOSE:To shorten the pull-in time during a change-over, by exercising control always to set the state position of the frame of a bus which is not used in the 1st and 2nd buses to the state position of the frame of a bus which is used. CONSTITUTION:A master clock oscillating circuits of 1/n dividing circuits 22a and 22b that set the outputs of the master clock oscillating circuits 4a and 4b to the 1/n frequency, the dividing circuit and the signal change-over circuits 23a and 23b that have three change-over positions of the nonconnection are provided in the transmission multiplex converters 51a and 51b. Furthermore a frame phase comparator 19 is added to compare the phases of synchronous codes of the synchronous code generating circuits 5a and 5b along with a control circuit 20 which controls the circuits 23a and 23b based on the result of phase comparison.