Showing papers on "Master clock published in 1983"

Data communication system and method and communication controller and method therefor, having a data/clock synchronizer and method

Abstract: A communication system and method is provided, in which synchronous (i.e., clocked) serial digital data may be sent and received from any given node to any other given node along a multinode loop of any desired mode quantity, with each node being capable of and maintained ready to assume the role and function of master node to provide the time-base or master clock for the loop. One node will serve as master node and all other nodes as slave nodes until the master becomes inoperable in its master clock function or until it is removed from the loop, at which time another node will assume the role of master node, and this status will continue as above-indicated. Small loop size is accommodated by adding a suitable delay to retransmitted data at the master node. Each node has clock recovery and both recovered clock/data synchronization means and its on-board master clock/data synchronization means (which latter is close to the same frequency at each node, but independent in frequency and phase at each node) to enable each node to serve as either master or slave node by internal switching selection of communication control output of either recovered clock data or master clock data for use and retransmission at each node, dependent on its instant self-intended role as slave or master. Master clock data synchronization at the master node is effected by shifting recovered clock data by a selected phase as a function of phase difference between the instant master node master clock and recovered clock at such master node, the selected phase shift being an amount sufficient to enable effective sampling by the master clock, to thereby provide absolute phase synchronization of receive data with master clock for internal serial processing, utilization, and retransmission by the instant master node. Each instant slave node has its own on-board such master clock data synchronizing means which may be maintained on standby, for enabling each assumption of the master node role, as may be required.

Multiple task oriented processor

Abstract: The computer system for missile guidance comprises five parallel processors interconnected by a global bus; with each processor having its own CPU, program memory, temporary memory, and two critical variable memories, interconnected by a local bus. The program memory and critical variable memory are hard MNOS to survive nuclear radiation. Each processor has its own cycle time, synchronized by a master clock. In each processor, the cycle has three phases for intercommunication, task processing, and critical variable storage. Thus the critical variables are stored only after task processing is completed.

Multiple redundant clock system comprising a number of mutually synchronizing clocks, and clock circuit for use in such a clock system

Abstract: A multiple redundant clock system comprises at least n=4 clocks and is self-synchronizing and fault tolerant against the failure of at the most 1/2(n-1) clocks. Each clock comprises an oscillator circuit which activates a dividing circuit at the end of each period in order to form its own clock signal on the output of the dividing circuit. Each clock furthermore comprises a deviation-determining device which compares the own clock signal with the clock signals originating from the other clocks in the system. When an excessively large number of the other clock signals deviate during the first half of the (own) period, the own oscillator circuit is decelerated. When an excessively large number of the other clock signals deviate during the second half of the own period, the own oscillator circuit is accelerated.

Servicing system for reproduction machines

Abstract: To facilitate servicing of xerographic type reproduction machines or printers, diagnostic routines are used (1) to operate the machine in a predetermined copy run while recording the clock count on a global counter on the arrival of a copy sheet at a first selected jam station in the paper path and the count on arrival of the same copy sheet at the next jam station, and then display the clock difference on the machine display console for comparison by the Tech Rep with a master clock count; (2) to operate the machine in a preset copy run while fetching the current timing parameter of a machine subassembly from memory, displaying the timing parameter to the Tech Rep on the machine display console, and permitting the Tech Rep to use the machine control panel keyboard to reset the timing parameter while watching the effect of the timing change on the copies as they are produced; and (3) to delay the arrival of the copy sheet at the machine image transfer station so that the normally unprinted interdocument area wherein process control images are formed is printed out to enable the process control images to be visually examined.

4-Phase clock generator

Abstract: A 4-phase clock generator comprises four gates for generating four clock signals from a master clock signal. The logic levels of four clock signals change in predetermined order after the master clock signal changes from a first logic level to a second logic level and they change in inverse order after the master clock signal changes back to the first logic level. The four clock signals are suitable to operate a shift register without making the adjoining transfer gates of the shift register conductive simultaneously.

Master/slave clock system

Abstract: A master/slave clock system including a slave clock configured for inexpensive and reliable control from the master. Each slave clock has an unregulated d-c supply adapted to be supplied with a-c power from the master clock. Threshold switching means in each slave clock is coupled across the d-c supply to sense an abnormally low d-c voltage level intentionally created by lowering the a-c supply level from the master. The threshold switching means switches the clock from the normal operating mode to the set mode where time is incremented at a predetermined rate for a duration controlled by the master clock in order to controllably set all slave clocks in the system to the correct time of day. The system conveniently allows all slaves to be reset to the same time when time is reset at the master, provides for automatic recovery after power failures, and provides a convenient means for automatically resynchronizing all slave clocks twice a day.

Master clock generator for telecommunications system

Abstract: A very stable master clock for satellites is disclosed. Time division multiple access techniques are used to permit individual earth stations to be received by the satellite in separate non-overlapping time slots. The satellite switched time division multiple access systems are compatible with the onboard satellite clock by providing a comparator control logic loop to produce a signal representing the phase difference between the onboard oscillator clock and the earth station. Control signals are generated to correct the voltage controlled oscillator onboard the satellite.

Method for transposing time measurements from one time frame to another

Abstract: A method for transposing the time of an event as read at a remote station with one clock to the time frame of another clock at a master station when the clocks are not synchronized and are of insufficient accuracy to provide measurements to within a few microseconds relative to other time measurements which are likewise transposed to refer to the master clock. A list of TV line 10 synch pulse times are maintained at the master for a specific number of recent line 10 pulses. Along with the time reading for the event, the line 10 synch pulse time as read at the remote is sent to the master. The list of line 10 synch times maintained at the master is examined to find the time by the master clock for the same line 10 and the difference between the time by the remote clock and the time by the master clock is used as an indication of the time correction factor to be applied for the transposition. The time correction factor is compensated for the difference in propagation time for the TV signal transmission to the master as compared to the remote. The transposed time reading is compared to other transposed readings obtained from other remote stations to either determine the sequence of several events at the different remotes or to obtain a measure of quantities such as voltage phase angle or the position of a fault. Updating of the time correction factors is provided to compensate for drift of the clocks.

Circuit arrangement for suppressing outgoing-signal noises in system for bidirectional transmission of digitized signals over two-wire line

Abstract: In order to suppress noise due to reflected outgoing signals in a telephone receiver of a system for the bidirectional transmission of digitized voice signals over a two-wire telephone line connected by a hybrid coil to an outgoing section and an incoming section of a subscriber station or of an exchange, a shift register loaded with several (e.g. five) consecutive transmitted bits from the outgoing section addresses the cells of a memory containing the digitized amplitudes of corrective signals assigned to the several bit combinations which may be present at any time in that register. The corrective signal read out from the memory during each bit period is subtracted in the incoming section from an arriving signal and the result is fed on the one hand to a receiver and on the other hand to an algebraic adder as a modifying signal incrementing or decrementing, if need be, the contents of the corresponding cell during a writing interval which is a small fraction of a bit period. As the arriving signals are digitized with a balanced code (e.g. AMI), their presence does not significantly affect the magnitude of the modifying signal emitted by the adder. If this circuit arrangement is part of a subscriber station, all active components are timed by clock pulses extracted from the incoming bit stream; if it is part of an exchange, only the receiving section is controlled by extracted clock pulses while the reading and writing in the memory is controlled by pulses from a master clock, divergences between the two clock-pulse trains being compensated by the introduction of delays under the control of a coincidence circuit.

Radio controlled analogue clock

Abstract: The arrangement according to the invention serves for displaying radio clock time using mechanical hands, and consists of a combination of an electronic radio clock, electromechanical analogue clock and digital memory with non-volatile storage, in which the clock pulses coming from the electronic radio clock are constrained to be fed, e.g., in a series circuit, both to the memory and to the analogue clock, so that the memory contents always correspond with the hand position. Upon switching on, or after a power failure, the radio clock time no longer corresponds to the time indicated by the analogue clock. According to the invention, the radio clock time is continually compared electronically with the memory time, and as long as the two differ from one another clock pulses of a higher frequency are generated until the radio clock time once again corresponds with the memory time. In this way, the automatically running analogue clock also receives the correct radio clock time after a relatively short correction phase.

Real-Time Photoelectron Event-Detecting Video System

Abstract: We describe a system for localization of photoelectron events utilizing an intensified Plumbicon camera and a Grinnell video digitizer. The Grinnell digitizer, arithmetic unit and memory are used to produce a real-time video difference between current pixel value and previous pixel value thereby suppressing multiple detection of the same event. A master clock provides synchronization with the camera in operation at 60 Hz in 240 lines/field, repeat field mode. Our event-localization scheme provides double-buffered line-address and event-amplitude for up to 32 events along a 512 pixel video line. A software algorithm allows localization of multiple detections of the same event, and provides a unique address interpolated with 1/2 line resolution by the host minicomputer in a 480 x 512 format.© (1983) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Digital data reproducing circuit

Abstract: PURPOSE:To process reproduction such as decoding, by detecting the running speed of a recording medium with a simple constitution and reading reproduced data even at varying speed reproduction. CONSTITUTION:The reproduced data reproduced from a magnetic head 2 is applied to a bit clock reproduction circuit 4. The circuit 4 generates a bit clock synchronized with the reproduced data and gives an output after picking up data by the bit clock. The data and bit clock are applied to an FM decoder 5, where a reproduced time code is obtained. A tachogenerator 7 is provided on a timer roller 6 having the number of revolutions proportional to the running speed of a tape 1, an output having a frequency proportional to the running speed is generated and applied to a PLL circuit 8. The PLL circuit 8 generates a master clock synchronized with the output of an FG7 and high frequency and applies the clock to the circuit 4. An FM decoder 5 at the next stage performs decoding by using the data and bit clock thus obtained.

Digital signal multiplexing means

Abstract: PURPOSE:To multiplex high-speed signals, by multiplexing digital signals into which a synchronizing and a discrimination signal are inserted previously on bit multiplex basis. CONSTITUTION:A master clock 4-4 is frequency-divided by two at a DFF4-1, whose output is supplied to the 1st signal generation part 4-2 and the 2nd signal generation part 4-3; and their outputs 4-10 and 4-11 are ANDed with signals Q and Q' of the DFF4-1 by AND gates 4 and 4 and their outputs are ORed by an OR gate 4-12 to multiplex digital signals (the 1st signal 4-7 and the 2nd signal 4-8) into which the synchronizing signal and discrimination signal are inserted previously.

Method for controlling clock supply to computer system

Abstract: PURPOSE:To shorten the clock interruption processing time of each computer system by externally supplying computer systems with a clock frequency-divided according to a control period. CONSTITUTION:A master clock signal MCLK from a master clock signal generator 2 is supplied to computer systems 1a, 1b, and 1c through clock controllers 4a, 4b, and 4c. The clock controller 4a (4b and 4c) has its RS flip-flop 5 set by a start command signal STRT from an external sequencer 3 and reset by a stop command signal STP to decide on whether the MCLK is supplied to the computer system or not. When the flip-flop 5 is set, the MCLK is frequency- divided by a frequency divider 7, and the resulting signal is supplied as the control period synchronizing clock to each computer system. Thus, interruption judgement processing time is shortened.

Recording/reproducing device

Abstract: PURPOSE: To reduce remaining jitters and color dislocation by generating a writing clock by a horizontal synchronizing signal and a burst signal overlapped at every time-base-compression multiplex signal. CONSTITUTION: A burst signal of single frequency is overlapped at a front porth in a horizontal blanking period of plural video signals. Image signals applied with time-base-compression supplied to an input terminal 21 of a time-base corrector 15' at the time of reproduction are taken out at their horizontal synchronizing signals by a horizontal signal separation circuit 22, and a frequency fM of a master clock is generated in a PLL27. On the other hand, only burst information of said video signals is taken out by a burst gate BG37. An 1/i divider 36 is a circuit to divide the frequency fM of the master clock into 1/4 so as to write and generate the frequency f c of a writing clock; and by resetting signals by burst information, the rise of a burst signal and that of a writing clock of the output of the divider 36 are set closest in phase. Moreover, a phase comparator PC38 detects their fine dislocation in phase and coincides a writing clock with that of a burst from a phase shift circuit 39 in phase. COPYRIGHT: (C)1985,JPO&Japio

Recording and reproducing device of pcm system

Abstract: PURPOSE:To enable the dubbing between the devices of different sampling frequencies, by controlling the frequency of the master clock in response to the external synchronizing signal. CONSTITUTION:A switch 30 is switched to the side (a), and the signal (fSIN) delivered from a crystal oscillator 25 is applied as the reference frequency signal of a phase comparator 26. In this case, the constant of an LPF27 and the dividing ratio of a frequency dividing circuit 29 are decided previously in order to obtain a master clock (MCIN) of a prescribed frequency from a voltage control oscillator 28. The master clock is divided by a frequency dividing circuit 31 to obtain the frequencies (fS, fC1, fC2). While the switch 30 is set at the side (b) and at the same time an external digital data supplied through a terminal T2 is selected in case the external synchronizing signal (fSBX) is used for operation. Thus the master clock (MCBX) of the oscillator 28 is set as MCEX=f'SEX/fSIN.M CIN which is controlled by the external synchronizing signal. Then the clock (MCBX) is divided by the circuit 31 to obtain a new sampling frequency corresponding to the external digital data.

Power supply synchronizing device

Abstract: PURPOSE:To make recording/reproducing of the sound of movies possible and prevent the degradation of the tone quality, by synchronizing a PLL with an input AC voltage and supplying the output as a clock to a PCM device. CONSTITUTION:When a master clock MCK is supplied to a control pulse generator 31, various timing signals and control signals are formed and are supplied to a recording system 10 and a reproducing system 20, and recording and reproducing of audio signals for a VTR 200 are performed. In this case, the synchronization with a picture is performed synchronously with the power supply by a synchronizing circuit 40. The output of the circuit 40 is formed into a pulse through a filter 51 and a voltage comparing circuit 52, and this pulse is given to a PLL 60, and a signal synchronized with an input commercial AC voltage is supplied as the clock MCK to the generator 31 through a switch 55A, a PLL 56, and a switch 55B. As the result, the sound of movies are PCM-recorded/reproduced synchronously with the power supply.

Automated Timekeeping II

Abstract: An automated system presently used by the U. S. Naval Observatory (USNO) for determining, maintaining, and disseminating Precise Time and Time Interval (PTTI) to a worldwide community of scientific and military users is described and evaluated on the basis of present capabilities and future requirements. The objective of the system is to provide near-real-time dissemination of PTTI information from a Master Clock time scale with a stability in excess of a few parts in 10-14.

Driving circuit for master slave clock

Abstract: PURPOSE:To synchronize slave clocks with a master clock stably at a high accuracy by using a crystal resonator alone arranged in the master clock in common to each slave clock CONSTITUTION:A master clock 1 has a crystal resonator 1a and a pulse signal oscillated therewith is applied to an output circuit 1e through a division circuit 1d to rotate a step motor intermittently The crystal resonator 1a is also used in common to slave clocks 2 and 3 and a pulse signal oscillated is applied to output circuits 2e and 3e respectively through division circuits 2d and 3d to rotate a step motor of the slave clocks 2 and 3 intermittently

Synchronizing network loop connecting system

Abstract: PURPOSE:To attain the locking in clock phase and error correction at a receiving side, by encoding information symbols into codes possible for error correction at terminal stations on each network, when >=2 line networks are combined at a point respectively, and broad connection of communication networks is performed CONSTITUTION:Two loop networks alpha and beta are connected at a combining node C, and a transmission frame has a slot given to a node connected to the loop alpha and a slot given to a node connected to the loop beta In a master clock source 80, the frequency is adjusted by applying a timing signal obtained when a receiving signal of the loop is received at a receiving section 71, via a sample value data system 70 The receiving signal is received at each high order station of both the loops alpha and beta, processed for operation in accordance with the algebraic rules at vector circuits 72, 77 for the detection of errors, and the phase synchronism is controlled The receiving data is encoded for codes possible for error correction at vector circuits 74, 75 via transmission and reception circuits 73, 76 and transmitted to a low order stations

Motor servo circuit

Abstract: PURPOSE:To stably operate a regeneration servo system by correctly reproducing a frame synchronization signal after setting the regenerative stage and then operating a regeneration servo system. CONSTITUTION:A relay 21 is OFF at the recording time and tape feeding and stopping time, and a relay contact 21a is shifted to R side. The relay 21 is ON at the regenerative time, the relay contact 21a is shifted to P side, thereby switching the comparison signal. Thus, a reference signal in a motor servo system is shifted from a master clock 7 to frame synchronization signal during regeneration signal. A comparison signal switching circuit 20 switches the contact 21a after the frame synchronization signal is correctly reproduced.