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Showing papers on "Master clock published in 1985"


Patent
26 Sep 1985
TL;DR: In this paper, three hardware real-time clock subcircuits are connected in a triple modular redundancy configuration to assure continued operation if one subcircuit fails, but a power supply or processor failure will not cause a clock supplying other processors to fail.
Abstract: Three hardware real time clock subcircuits are connected in a triple modular redundancy configuration to assure continued operation if one subcircuit fails. A power supply or processor failure will not cause a clock supplying other processors to fail. Output of voted master clock pulses to the counter in every subcircuit is inhibited until all power supplies are turned on and stabilized, and the time base of the real time clock pulses is variable. The output pulses of all subcircuits are voted on and the voter output is the real time clock. The master clock can be the processor clock.

81 citations


ReportDOI
01 Dec 1985
TL;DR: The election algorithm that guarantees the reliability of TEMPO, a distributed clock synchronizer running on Berkeley UNIX 4.3BSD systems, is described.
Abstract: This paper describes the election algorithm that guarantees the reliability of TEMPO, a distributed clock synchronizer running on Berkeley UNIX 43BSD systems TEMPO is a distributed program based on a master-slave scheme that is comprised of time daemon processes running on individual machines The election algorithm chooses a new master from among the slaves after the crash of the machine on which the original master was running When the master is working, it periodically resets an election timer in each slave If the master disappears, the sl ave whose timer expires first will become a candidate for the new master The election algorithm covers this normal case, as well as the infrequent case where there may be two or more simultaneous candidates It also handles the case in which, due to a network partition that has been repaired, two masters are present at the same time

68 citations


01 Sep 1985
TL;DR: A stochastic model and algorithms for computing a good estimator from time-offset samples measured between clocks connected via network links are suggested.
Abstract: This RFC discussed clock synchronization algorithms for the ARPA- Internet community, and requests discussion and suggestions for improvements. The recent interest within the Internet community in determining accurate time from a set of mutually suspicious network clocks has been prompted by several occasions in which errors were found in usually reliable, accurate clock servers after thunderstorms which disrupted their power supply. To these sources of error should be added those due to malfunctioning hardware, defective software and operator mistakes, as well as random errors in the mechanism used to set and synchronize clocks. This report suggests a stochastic model and algorithms for computing a good estimator from time-offset samples measured between clocks connected via network links. Included in this report are descriptions of certain experiments which give an indication of the effectiveness of the algorithms.

42 citations


01 Jan 1985
TL;DR: Symmetric distributed termination algorithms are systematically developed and first presented in an abstract setting of Dijkstra, Feijen and Van Gasteren and gradually transformed into solutions to the distributed termination problem of Francez.
Abstract: Symmetric distributed termination algorithms are systematically developed. Solution are first presented in an abstract setting of Dijkstra, Feijen and Van Gasteren [DFG] and then gradually transformed into solutions to the distributed termination problem of Francez [F]. The initially used global real time clock is eventually replaced by local virtual clocks. A dependence between the degree of clock synchronization and the efficiency of the solutions is indicated.

30 citations


01 Sep 1985
TL;DR: This RFC discusses some experiments in clock synchronization in the ARPA-Internet community, and requests discussion and suggestions for improvements in one such clock service design described and its performance assessed.
Abstract: This RFC discusses some experiments in clock synchronization in the ARPA-Internet community, and requests discussion and suggestions for improvements. One of the services frequently neglected in computer network design is a high-quality, time-of-day clock capable of generating accurate timestamps with small errors compared to one-way network delays. Such a service would be useful for tracing the progress of complex transactions, synchronizing cached data bases, monitoring network performance and isolating problems. In this memo one such clock service design will be described and its performance assessed. This design has been incorporated as an integral part of the network routing and control protocols of the Distributed Computer Network (DCnet) architecture.

24 citations


Patent
29 Aug 1985
TL;DR: In this article, a synchronous clock circuit is provided on each module of an electronic digital system formed of a plurality of modules, with two control pins which are used by control logic to determine whether or not the clock on a particular module is disabled, is operating as the master clock for the system, or is providing a backup function.
Abstract: A synchronous clock circuit is provided on each module of an electronic digital system formed of a plurality of modules. Each clock circuit has two control pins which are used by control logic to determine whether or not the clock on a particular module is disabled, is operating as the master clock for the system, or is providing a backup function for the master clock. The common clock line is supplied through a buffer to the components on the module which require clocking. Logic circuitry on the backup clock mode insures the backup clock is in a ready condition in case there should be either failure of the master clock oscillator or if the master clock module is removed from the unit. All of the clock circuits of the different modules may be constructed in an identical manner, with the control of the function of the circuitry being provided simply by control of the logic level on the two terminals. A clock detecting time-out circuit is provided on each of the modules, which has a timing period which is slightly longer than the clock period. If the master clock fails to produce a clock pulse at the time that it should, the clock detect timing circuit, which is coupled to the buffer of the backup module, will sense that a failure has occurred and will control the turn-on of the clock circuit for the backup module.

24 citations


Patent
14 Jan 1985
TL;DR: In this paper, a clock synchronization system in a digital data switching system, such as a digital PBX, has been proposed, where a local clock generating timing signals at a frequency greater than a nominal frequency, a circuit for lowering the local clock frequency and a comparator coupled to a second clock operating substantially at the nominal frequency for activating the lowering circuit so that the Local Clock is synchronized with the second clock.
Abstract: A clock synchronization system in a digital data switching system, such as a digital PBX. The system has a local clock generating timing signals at a frequency greater than a nominal frequency, a circuit for lowering the local clock frequency and a comparator coupled to a second clock operating substantially at the nominal frequency for activating the lowering circuit so that the local clock is synchronized with the second clock. The system is distributed by placing the local clock and the lowering frequency on the control module of the switching system and placing the comparator to one or more of the line card modules which is receiving the second clock signals. Communication between the comparator and lowering circuit may be over a single line.

17 citations


Patent
26 Oct 1985
TL;DR: In this article, the transmission delay time from a master clock to a slave clock was used to adjust the slave clock time with high precision by using evaluation information on time information transmitted by the master clock.
Abstract: PURPOSE:To adjust slave clock time with high precision by using evaluation information on time information transmission delay time from a master clock to a slave clock as slave clock time adjustment information. CONSTITUTION:The time when the slave clock SCL sends a time information request signal TMD is denoted as T'O, the time when the master clock MCL receives the TMD and sends a time information annunciation signal TMI is denoted as T1, and the time on the SCL when CL receives the TMI from the MCL and make a time adjustment is denoted as T's. At this time, the transmission delay time DLTM on the SCL as to the MCL is evaluated from an equation I . The SCL uses time information and evaluated transmission delay time from the MCL to make a time adjustment by regarding the time equation II obtained by adding the delay time based upon the equation I to the time T1 of the time information as new time.

8 citations


Patent
16 Oct 1985
TL;DR: In this paper, a timing generator and verifier is provided in which a PROM stores the timing constants that are employed by the generator, and an address counter, which is driven by a clock timer, cycles through an associated portion of the PROM to provide a sequence of output signals which represent timing for a particular mode.
Abstract: A timing generator and verifier is provided in which a PROM stores the timing constants that are employed by the generator. An address counter, which is driven by a clock timer, cycles through an associated portion of the PROM to provide a sequence of output signals which represent timing for a particular mode. If a different mode is selected, the address counter selects a different sequence of output bits. During Normal mode the address counter operates on a cyclic basis driven by a fixed frequency free running master clock. In Verify mode the address counter is stepped by the Host computer. The outputs of the PROM are coupled through a buffer and logic section, where the outputs may be modified before being coupled to an adder which accumulates a checksum based on the outputs of all of the bits for a particular selected timing. The checksum provided by the adder is compared in a comparator with a stored checksum that indicates whether the correct operation of the complex timing cycle for the selected mode has been verified.

7 citations


Patent
17 Dec 1985
TL;DR: In this article, the authors proposed a scheme to prevent degradation in picture quality by placing a scanning line of an odd-numbered order into an odd numbered order even after the replacement of the scanning line.
Abstract: PURPOSE:To prevent degradation in picture quality by placing a scanning line of an odd-numbered order into an odd-numbered order even after the replacement and placing a scanning line of an even-numbered order into an even-numbered order even after replacement in replacing the scanning line. CONSTITUTION:An analog video signal to be scrambled is inputted to a terminal 1 in a scrambler at the broadcast station side, and after this signal passes through an LPF2, it is fed to an A/D converting circuit 3 and a master clock oscillator 4. Then the oscillator 4 produces a master clock having subcarrier frequencies fSC-3fSC based on a color burst signal of the video signal, and the clock is fed to an A/D converter 3, a synchronizing separator circuit 5 and a timing clock generating circuit 6. This converter 3 samples the input video signal by using the master clock and converts it into a digital video signal. This signal is fed to a frame memory 7, written in a ROM8, read from a ROM9 based on the scanning designation signal from a computer 10 and the scanning lines are replaced.

5 citations


Patent
15 Apr 1985
TL;DR: In this article, the authors propose to store accurate timing information to a 0 consecutive signal even if the Q of a single tuning circuit is low by applying a highly stable clock obtained from a master clock to an identification circuit or the like.
Abstract: PURPOSE:To store accurate timing information to a 0 consecutive signal even if the Q of a single tuning circuit is low by applying a highly stable clock obtained from a master clock to an identification circuit or the like CONSTITUTION:A part of a transmission signal applied to a terminal 21 is rectified (4) as full-wave A code subjected to full-wave rectification 4 is applied to the single tuning circuit 5, from which the timing component is extracted and the component is converted into the timing clock by a limiter amplifier 6 On the other hand, a transmission signal applied to the terminal 21 is fed to the identification circuit 2, where the signal is subjected to full-wave rectification and a sliced rectangular wave is obtained This rectangular wave is converted into the transmission signal Then a counter circuit 9 starts counting at the trailing of the transmission signal and an output signal is obtained Furthermore, an output signal of an AND circuit 10 and a clock from a master clock circuit 7 are applied to a digital phase-locked circuit 8, where a highly stable clock is extracted and the clock is fed to the circuits 2 and 9

Patent
19 Feb 1985
TL;DR: In this article, the authors propose to change easily the pitch of a reproduction signal by changing the frequency of a clock signal and changing the driving speed of a recording medium synchronously with the variation of the clock signal frequency.
Abstract: PURPOSE:To change easily the pitch of a reproduction signal by changing the frequency of a clock signal and changing the driving speed of a recording medium synchronously with the variation of the clock signal frequency. CONSTITUTION:The dividing ratio is controlled by a frequency control circuit 17, and a signal of a desired frequency is produced from a programmable dividing circuit 14 of a clock generating circuit 7. Then a master clock whose frequency is changed in response to the control of the circuit 17 is produced via a phase comparator 11 which compares the phase of a frequency signal supplied via a frequency dividing circuit 10, a voltage control oscillator 9 of a PLL circuit 8 which receives the feedback control through an LPF12, etc., a various clock generating circuit 15, etc. When the master clock is supplied to a drive control circuit 16, the driving speed of a disk 1 is varied synchronously with a clock. Then the reproduction digital signal is processed by a demodulating/decoding circuit 5 which is controlled by the clock and a D/A converter 6. Then the pitch of a reproducton analog signal is easily changed.

Patent
14 Dec 1985
TL;DR: In this article, the authors proposed a scheme to attain a high transmission factor with a ring-shaped network by setting the different monitor times for each node when the token is lost, by performing a switch immediately to an active monitor when the time-out is set and fixing a transmission master clock to said monitor.
Abstract: PURPOSE:To attain a high transmission factor with a ring-shaped network by setting the different monitor times for each node when the token is lost, by performing a switch immediately to an active monitor when the time-out is set and fixing a transmission master clock to said monitor. CONSTITUTION:The allowance conditions of a PLL input permission circuit 8 for transmission has different conditions from conventional ones and satisfies its conditions when it acquires the active monitor right. Thus the signals, i.e., the transmission clocks which are supplied hereafter to a reproduction circuit 12 for transmission are fixed at the self-traveling frequency of a PLL7 for transmission after the active monitor right is once acquired. Then an active monitor right acquisition signal 13 is transmitted. That is, the semipermanent transmission right of master clock is acquired and the transmission clocks on a ring are never switched as long as the active monitor has its breakdown. Therefore, the synchronism is always set up for a PLL6 for reception and the PLL7 of each node of the ring. Thus it is possible to make full use of the transmission speed for communication.

Patent
30 May 1985
TL;DR: In this paper, a mask circuit is used to mask a specified part of a video clock and a data conversion circuit is installed at the free expansion device to expand picture data to an optional size.
Abstract: PURPOSE:To easily expand picture data to an optional size by converting the picture data to the series-parallel by synchronizing to a master clock obtained by a mask circuit. CONSTITUTION:A mask circuit 22 masking a specified part of a video clock 21, and a data conversion circuit 25 converting a picture data 24 to the series-parallel by synchronizing to a master clock 23 masked by the circuit 22 are installed at the free expansion device. The picture data 24 are supplied from a picture data supply source 26 to a data conversion circuit 25 successively and an expanded data 27 is obtained. The magnification of the data 27 can be expanded to the optional size according to the mask contents of the mask circuit 22.

01 Dec 1985
TL;DR: In this article, a portable clock trip is described, where the portable clock is initially synchronized as close as possible to the master clock (NC) time at that observatory, and closure is again made with the original master clock and a rate of the Portable Clock against the master Clock is measured.
Abstract: : Historically, precise time has been transferred between two sites by means of a method using portable atomic clocks. The method entails the carrying of an active frequency standard and its associated clock from site A to site B. Personnel from the United States Naval Observatory (USNO), Bendix Field Engineering Corporation (BFEC), Naval Research Laboratory (NRL), and others have made portable clock trips by airplane and surface vehicles for the past 15 years. The accuracy obtained using this method for the transfer of time ranges from a few nanoseconds (on a short surface trip) to hundreds of nanoseconds (on an extended overseas trip). Typically the origin of the portable clock trip is a major time keeping observatory, such as USNO, where the portable clock is initially synchronized as close as possible to the master clock (NC) time at that observatory. Prior to departure a stationary rate is determined between the two clocks. Upon return to the originating observatory, closure is again made with the master clock and a rate of the portable clock against the master clock is measured. These two rates (before and after) are then compared. Assuming no major difference occurs, the time accumulation between the two clocks is estimated and linearly applied to results obtained from each location on the trip. The important thing to note in such a method is that the portable clock must be kept running during the entire trip; that is, transported "hot". Many logistics problems and additional costs result from this necessity.

Patent
05 Sep 1985
TL;DR: In this article, the authors proposed to prevent the unlocked condition of a PLL so as to prevent generation of click noises and discontinuance of sounds, by setting the change in the center frequency of a bit clock reproducing circuit to a response speed following to the change of the rotational speed of a disk.
Abstract: PURPOSE:To prevent the unlocked condition of a PLL so as to prevent generation of click noises and discontinuance of sounds, by setting the change in the center frequency of a bit clock reproducing circuit to a response speed following to the change in the rotational speed of a disk. CONSTITUTION:A master clock frequency is supplied to a bit clock reproducing circuit 5 through a time constant circuit 25 after it is converted into a DC voltage by a converting circuit 16 and the center frequency of the circuit 5 is changed following to the change in the master clock frequency. When a time constant which is equivalent to the time constant of the change in the rotational speed of a disk 1 is selected as the time constant of the circuit 25, the change in the frequency (change in the rotational speed) of a bit clock contained in the information signal of the disk 1 and the change in the center frequency of a PLL (change in the output voltage of the time constant circuit 25) are made almost coincident with each other and deviation from a locking range can be prevented.

Patent
13 Feb 1985
TL;DR: In this paper, the current supply frequency (fp) is made exactly equal to the sample frequency (fs) for the collection of seismic data, or equal to an exact multiple of said sample frequency.
Abstract: The current supply frequency (fp) is made exactly equal to the sample frequency (fs) for the collection of seismic data, or equal to an exact multiple of said sample frequency (fs). The current supply 2 may be controlled to operate at the required frequency by means of a voltage controlled oscillator 7 having an input from a phase comparator 6. A master clock 4 is connected to a hydrophone cable 3 to control the data stream and also supply one of the inputs of comparator 6 via a divider 5. Alternatively, separate crystal oscillators may be used for the clock 4 and to control the supply 2.

Patent
19 Jun 1985
TL;DR: In this article, the 1st counter counts a master clock pulse from a clock pulse generator, and the 2nd counter also executes 1/n dividing operation through invertors 12, 13 and 14.
Abstract: PURPOSE:To obtain a bit clock pulse demodulating properly a regenerated signal by providing the 1st counter, which counts a master clock pulse from a master clock pulse generator, and the 2nd counter also executing 1/n dividing. CONSTITUTION:An output end of an edge detection part 4 is connected to, for instance, a clear terminal CLR of the 1st counter 10. An output terminal of a upper rank three bit out of output terminals Qa, Qb, Qc and Qd of four bits is connected to three terminals at the lower rank bit side out of preset terminals of four bits (a), (b), (c) and (d) of the 2nd counter 11 executing 1/n dividing operation through invertors 12, 13 and 14. An output end of a master clock pulse generator 17 is connected to a clock terminal CK of the 1st counter 10 and a clock terminal CK' of the 2nd counter 11.

Patent
20 Sep 1985
TL;DR: In this paper, an automatic program searching of an optical musical composition at the time of sound reproducing was achieved by multiplying an ID signal having information such as elapsed time from the head of each musical composition with a sound signal converted into a digital signal with time division.
Abstract: PURPOSE: To attain the automatic program searching of an optical musical composition at the time of sound reproducing by multiplying an ID signal having information such as elapsed time from the head of each musical composition with a sound signal converted into a digital signal with time division CONSTITUTION: As to a clock to be a reference for digital signal processing in a PCM processor, a master clock generated synchronously with the rotational phase of a cylinder is used at the time of normal reproducing, and at the time of rapid searching, a reproducing clock synchronizing with a PCM signal reproduced on the basis of PLL is used during the reproducing period of a PCM signal and a master clock is used in the other period Consequently, high quality of sound reduced at its time axial variation as low as possible can be reproduced at the normal reproducing, and at the rapid searching, an ID signal can be detected even if the frequency of the PCM signal is sharply changed In addition, the incorrect detection of the ID signal can be suppressed by stopping an error correcting function of the PCM processor at the rapid searching Thus, precise and rapid program searching can be attained at the time of sound reproducing COPYRIGHT: (C)1987,JPO&Japio



Patent
03 Apr 1985
TL;DR: In this paper, the retransmission correction control code is divided into an information code, an exchange control code and an exchange exchange code and the control code can be transferred by channels S1, R1 transmit information block, channels S2, R2 transmit the next information block and channels S3, R3 transmit interruptions.
Abstract: PURPOSE:To relieve the load of the processing of a computer in retransmission correction by dividing an information code part to parts corresponding to plural terminal device, and dividing again the parts into an information code, a retransmission correction control code and an exchange control code. CONSTITUTION:A reception section R receives a signal from a high-order station. A master clock source C of a terminal Ti station is adjusted automatically by voltage control. A sample value data system TI detects timing information of a bit clock of the Ti. A PR consists of a shift register, ''0'' detection circuit and a buffer resister, and inputs a code word subject to error corection to a buffer SR for code transfer between a transmission system and a terminal device. Channels S1, R1 transmit information block, channels S2, R2 transmit the next information block or request retransmission and the control code such as interruption is transferred by channels S3, R3. Complicated control is attained without imposing a considerably load on a communication program by dividing the S2, R2 further in details.

Patent
02 May 1985
TL;DR: In this paper, a master clock having a center frequency by inputting a ground level with a switch when an input signal is interrupted so as to switch the clock frequency is presented.
Abstract: PURPOSE:To output a master clock having a center frequency by inputting a ground level with a switch when an input signal is interrupted so as to switch the clock frequency. CONSTITUTION:Switches 12, 13 are driven by a drive signal of a switch drive circuit 14 at the interruption of an input signal, a terminal D of an FF circuit 2 is grounded, a clock f2 is selected by the switch 13 and fed to the terminal D of an FF circuit 4 of a differentiation circuit 3. The clock f2 is a frequency division from the master clock from a master clock generator 8 at a frequency divider 15. On the other hand, the FF circuits 4 and 5 of the circuit 3 are operated while the output of the circuit 2 is brought to logical 1 by the clock f2 and a differentiation pulse is outputted, and the master clock is transmitted from an NAND gate 9 so as to have the center frequency.

Patent
04 Jun 1985
TL;DR: In this paper, the pull-in action of an echo canceler at the slave side in a state in synchronization with a master clock of the master side was proposed to eliminate an echo component in an optimum phase after the end of a training period.
Abstract: PURPOSE:To eliminate an echo component in an optimum phase after the end of a training period by performing the pull-in action of an echo canceler at the slave side in a state in synchronization with a master clock of the master side. CONSTITUTION:The training signal containing sufficient 0 signals in one signal is transmitted repetitively from the master side in an early stage of communication. At the slave side the training signal of the master side is applied to an equalizer 4 via a hybrid circuit 3 and then to an echo canceler 5, a timing reproduction circuit 6 and a detection control circuit 7 via the equalizer 4. When 1 of the training signal is detected at the circuit 7, control signals (a)-(c) are outputted. Then the signal (a) is applied to a transmission part 1 in a prescribed period of time after a signal is received and detected. At the same time, the canceler 5 is pulled in by the signal (b) in a prescribed period including the transmission period of a signal. While this pull-in action is performed, the pull-in of the equalizer 4 and the timing extraction of the circuit 6 are discontinued by the signal (c). Then the timing phase is held in the corresponding phase.

Patent
07 Sep 1985
TL;DR: In this article, a master clock signal CKM is input to a signal control part 1 for the number of delay stages of the pulse delay circuit and a data signal XD of a necessary delay time value represented as the rate to the master clock rate is also inputted.
Abstract: PURPOSE:To perform pulse delay control over a delay time shorter than the master clock rate of a system and to output a stable delay pulse signal from the digital system by correcting variations in source voltage and temperature and variance in manufacture process on circuit system basis. CONSTITUTION:A master clock signal CKM is inputted to a signal control part 1 for the number of delay stages of the pulse delay circuit and a data signal XD of a necessary delay time value represented as the rate to the master clock rate is also inputted. This control part 1 outputs the corrected delay-stage number numeral yact of a unit delay circuit. This delay-stage number numeral yact is applied to a delay pulse signal selection part 2 and a selection reference pulse PB is inputted to the input terminal of the 1st stage of a unit delay circuit. Then, output pulses of (n) stages of unit delay circuits 31-3n connected in series are selected with switched 41-4n for unit delay circuit output pulse selection which are controlled by a decoder 5 for output pulse selection, thereby outputting the stable delay pulse PD.

05 Dec 1985
TL;DR: The first dedicated German Shuttle I Mission Dl with the Spacelab laboratory on board took place from Oct. 30 to Nov. 6 1985 as mentioned in this paper, where a Cs-and a Rb-clock onboard were used for the generation of PN-code navigation signals.
Abstract: : From Oct. 30 to Nov. 6 1985 the first dedicated German Shuttle I Mission Dl with the Spacelab laboratory on board took place. One of the more than 70 experiments on board was the Navigation I Experiment NAVEX. A Cs- and a Rb-clock onboard were used for the generation of PN-code navigation signals. During the experiment these clocks were compared with the ground master clock by one-way and two-way methods. In this paper a survey will be given on the progress of the experiment and on first raw data, which indicate already a satisfactory operation of the used spread spectrum technique and a very accurate confirmation of the predicted relativistic clock effects.

Patent
12 Feb 1985
TL;DR: In this paper, a Doppler frequency between a low frequency reference station and a slave station for the phase comparing frequency of a clock phase lock system in the reference station was used.
Abstract: PURPOSE:To digitize a phase comparator easily by using a Doppler frequency between a low frequency reference station and a slave station for the phase comparing frequency of a clock phase lock system in the reference station. CONSTITUTION:The output frequency (f) of a voltage control oscillator 28 in the reference station 200 is repeated through a satelite 20. The slave station 201 receives the repeated frequency (f) as frequency f+fd by Doppler shift and outputs the frequency f+fd from a voltage control oscillator 35. The output f+ fd is repeated by the satellite 20 and received by the reference station as frequency f+2fd. Said received frequency is multiplied by the oscillation frequency fo of a master clock oscillator 21 by a multiplier 22 and its low frequency component f+2fd-fo is extracted by an LPF23. The low frequency component is multiplied 25 by the outputs of the oscillators 28, 21 and the multiplied result is compared with the frequency fo-f obtained through an LPF24 by a phase comparator 26 and the oscillator 28 is controlled by a signal obtained by passing the compared output through a loop filter 27. During the clock phase lock system holds the synchronization, the reproducing clock frequency of the slave station 201 equals to fo.

Journal ArticleDOI
TL;DR: Problems of anomalous conversions on successive approximation-type A/D converters, in hybrid systems, are considered, and internal digital noise is shown as the cause, and the interruption of the master clock of the system is discussed as a solution.
Abstract: Problems of anomalous conversions on successive approximation-type A/D converters, in hybrid systems, are considered. Internal digital noise is shown as the cause, and the interruption of the master clock of the system is discussed as a solution. Experimental tests have substantiated the validity of this approach.

Patent
16 Apr 1985
TL;DR: In this paper, the authors proposed a scheme to supply a stable master clock signal with high reliability by detecting an abnormality of the phase of a reference clock signal before it has a considerable influence upon a generated master clock signals and switching this clock signal to a new reference signal.
Abstract: PURPOSE:To supply a stable master clock signal with high reliability by detecting an abnormality of the phase of a reference clock signal before it has a considerable influence upon a generated master clock signal and switching this clock signal to a new reference clock signal CONSTITUTION:In comparison with a selectivity Qe of a resonance circuit for extracting clock components included in a clock extracting circuit 1 of each system, an equivalent Qp of a phase locked oscillator PLO51 included in a master clock generaging circuit 5 is set to a sufficiently higher value For example, if an abnormal situation such as loss of a transmission signal in the reference side is caused, the speed of phase changed of the master clock signal generated from the oscillator PLO51 is made sufficiently lower than that of the clock signal of the clock extracting circuit 1 in the loss side, and the abnormality of the reference signal is detected by the phase difference between them exceeding a specific threshold, and the reference signal is switched to the reference signal of the other side where no abnormalities are detected in phase difference Thus, variance of the phase of the master clock signal for the occurrence of an abnormal situation is held down to a minimum

Patent
11 Jun 1985
TL;DR: In this article, the authors proposed a scheme to provide numbers of key codes for a request to secure privacy and prevent communication contents from being intercepted when they are received by the 3rd party by providing a privacy communication device with a variable delay circuit, frequency dividing circuit, counter circuit, and logical circuit.
Abstract: PURPOSE:To provide numbers of key codes for a request to secure privacy and prevent communication contents from being intercepted when they are received by the 3rd party by providing a privacy communication device with a variable delay circuit, frequency dividing circuit, counter circuit, and logical circuit. CONSTITUTION:The speed signal from the speech input terminal 1 of the privacy communication device is applied to the BBD delay circuit 3 through an LPF2, and the speed signal is sampled according to the clock of a clock circuit 4 and stored in the delay stage of the circuit 3. Then, those 2N sampled values which are stored are passed through an LPF5 and added by an adding circuit 7 to the output of a synchronizing signal circuit 6, and the sum is frequency-modulated by a transmitting circuit 8 and sent to a transmission system 9. This signal is demodulated by a receiving circuit 10 and applied to a BBD delay circuit 14 through an LPF11 to sample and store the receive speech according to the clock of a clock circuit 12. At the same time, sampled values which 2N samples before are outputted from an LPF13 in order simultaneously. Those circuits 4 and 14 are provided with a master clock oscillaor 17, frequency dividing circuit 18, counter 19, and logical circuit 20.