Showing papers on "Master clock published in 1986"

Master clock system for a parallel variable speed constant frequency power system

Abstract: A clock control system for a multiple channel electric power system includes a master clock circuit and control circuitry in each parallel connected channel. The channel control circuits are intially phase-locked to a master clock signal. If the master clock signal is out of a preselected frequency range, the individual channel control circuits are decoupled from the master clock signal and one of those circuits produces a backup clock signal. The control circuits in the remaining channels are then phase-locked with the backup clock signal to provide continued parallel system operation.

Deterministic clock control apparatus for a data processing system

Abstract: A clock control apparatus that stops a system clock in a high performance high speed computer a determined number of system clock cycles after the generation of the clock control signal by a digital computer. The apparatus receives a basic clock signal and the clock control signal and generates a system clock for the system. The system clock includes a normal system clock signal and at least one early system clock signal. The basic clock is provided through a delay tap generating a normal basic clock signal and at least one early basic clock signal. In addition, a control state machine receiving the normal basic clock signal and the at least one early basic clock signal and responsive to the clock control signal is provided for starting and stopping the system clock. The clock control signal is synchronized with the earliest system clock and supplied to the clock control state machine.

Phase synchronization system

Abstract: Basic operation clock generators for effecting frequency division of the system clock are provided for respective ones of a plurality of processors, and the basic operation clock generators associated with respective processors are connected in cascade. The basic operation clock generator of the preceding stage produces a synchronization signal in response to each particular state of the basic operation clock signal and supplies the synchronization signal to a basic operation clock generator of a succeeding stage, and the basic operation clock generator of the succeeding stage establishes the initial state in the basic operation clock signal by using the synchronization signal supplied from the basic operation clock generator as a control signal, whereby the phases of basic operation clock signals of respective processors are matched to each other.

Triplicated clock distribution device for use when each clock signal comprises a synchonization signal

Abstract: A triplicated clock distribution device, for use where each clock signal comprises a synchronization signal, comprises three slave clocks connected to receivers. Each slave clock comprises a clock generator and a synchronization generator and delivers a clock signal incorporating a synchronization signal the frequency of which is half that of the clock signal. Each receiver comprises a clock regenerator and a synchronization regenerator which respectively deliver a clock signal and a synchronization signal to user circuits to which the receiver is connected.

A synchronizing system

Abstract: A synchronizing system is provided for reliably passing data across a boundary between two independent, non-correlated clocks, referredto as the receiving and transmitting clocks. The system reduces occurrence of errors due to asynchronous samplings to an arbitrarily low level based on metastable operation. The system is organized as a two port memory with unit distance code addressing the memory cells. It performs a handshake between the two non-correlated clock systems to allow for any ratio between the two clocks.

Frequency divider circuit whose output frequency is partly missing

Abstract: PURPOSE: To minimize the occurrence of jitter by adopting the constitution that OR outputs of plural timing pulses are shifted in multistage to generate a mask signal so as to incorporate the entire circuit into one LSI. CONSTITUTION: A timing pulse generating circuit 11 receives a master clock to generate plural timing pulses with a different phase. The timing pulse outputted from the timing pulse generating circuit 11 enters an OR gate 12 and enters an OR gate 12, from which the pulse is converted into a pulse having a consecutive width corresponding to the region to be masked. The partly missing timing pulse is inputted to a mask signal generating circuit 13. The mask signal generating circuit 13 uses an output of the OR gate 12 by using the master clock to be shifted in multi-stage and the circuit 13 generates a mask signal masking the clock with the reception of the shift output of each stage. The mask signal enters the succeeding gate circuit 14 to mask the master clocks by a required number. As a result, a clock subject to frequency division and partly missing is obtained to minimize jitter from the gate circuit 14. COPYRIGHT: (C)1988,JPO&Japio

Clock control system for network synchronization

Abstract: PURPOSE: To attian the synchronizing control of an equipment connected always to a communication system by detecting the absence of a network synchronization clock so as to apply a prescribed fixed voltage to a clock source, thereby generating the clock internally. CONSTITUTION: The network synchronizing clock and a feedback clock from a clock source 101 are subjected to phase comparison by a phase comparing means 102, a control voltage from the means 102 is supplied to output a clock synchronously with the network synchronizing clock from the clock source 101. On the other hand, when the absence of the network synchronizing clock is detected by an input interruption detection circuit 103, a changeover means 104 selects a fixed voltage similar to the control voltage from the means 102 generated from the clock source 101 to supply the clock synchronously with the network synchronizing clock to the clock source 101. Thus, even when the network synchronizing clock is absent, the synchronizing clock is generated synchronously with the network synchronizing clock in the inside of the equipment and the equipment connected to the communication system is subjected to excellent synchronization control at all times. COPYRIGHT: (C)1988,JPO&Japio

Local area network

Abstract: PURPOSE: To prevent a fault of a part of node or a transmission line from being effected on the entire network by allowing each node to transmit master node decision information to the transmission line at the start of operation or the occurrence of a fault of the network, processing the information in a prescribed procedure to decide the master node of the network. CONSTITUTION: Nodes 2,1∼2,4 generate a synchronizing time division multiplex TDM frame and send it to transmission lines #0,, #1 based on the master clock of a clock source possessed by its own node at the start of operation. Then a TDM frame sent from the adjacent nodes is detected and the node becomes the master node in the descending order node number. For example, when the node number of the node 21 is least, the node 2,1 plays a role of the master for both the lines #0, #1 and the other nodes 2,2 2,4 act as slave stations. COPYRIGHT: (C)1987,JPO&Japio

Clock synchronisation in a distributed processing system

Abstract: The present invention provides a method for clock synchronisation in a distributed processing system comprising the steps of. - diffusing from a processor with a preferred clock value (for instance, a processor having a fastest correct clock) a synch signal indicating the preferred clock value to the other processors in the system; and - adjusting at the other processors in the system the local clocks in response to the synch signal such that the difference between the local clock values for each pair of processors in the system is bounded.

A Telephone-Based Time Dissemination System

Abstract: : Telephone time dissemination can serve a broad spectrum of users who require time accuracy in the millisecond range and who are reluctant to use radio time dissemination services. A system which uses a simple protocol for telephone loop-delay correction is presented. The protocol uses ASCII characters transmitted by the frequency shift keying techniques of standard 300 baud modems. The protocol is designed for the transfer of the correct time from a master clock to a slave clock. The slave clock places the telephone call, puts the master clock into a prompt echo mode, measures the loop delay time, and applies half the loop delay time as a correction to the time it receives from the master clock. The precision and accuracy of this protocol are discussed and measurements are presented on the precision of time transfer using Leitch CSD-5300 units as master and slave clocks. The capabilities of the full system, and the Leitch CSD 5300 units which are used at each distribution node, are discussed as possible solutions to questions that are often addressed (or misaddressed) to "Precise Time" research groups.

Continuously variable synchronizer apparatus

Abstract: A system is illustrated for making sure that received data and the master clock are in the proper relationship even though temperature, voltage supplies and aging cause variable transmission time delays between the source of data and the local circuit. This proper relationship is accomplished by detecting the phase difference between a local master oscillator and the received data and providing a clock signal to be used by the remote data sending device in a system phase-locked loop using a slave oscillator and the previously mentioned phase detection circuit. The slave oscillator tracks the frequency of the master oscillator and the phase of the incoming data. Since a clock signal was previously required for prior art systems, this approach eliminates the return clock that was required if the cable length and the associated data signal delay parameters could vary.

Digital circuit for frequency or pulse rate division

Abstract: The digital circuit is for receiving a master clock signal at a frequency te f on an input and delivering a rectangular shaped output signal at a lower frequency (M/N)f where M is an integer and N is an even integer greater than M. The circuit comprises an even number N of series connected flip-flops in a ring arrangement, each flip-flop being connected to receive input signals from the preceding flip-flop and from the following flip-flop and to receive a master clock signal on a clock input. The even numbered flip-flops are of a type different from the type of the odd numbered flip-flops. The outputs of the flip-flops each deliver a rectangular pulse signal having a duty ratio equal to 1/N of that of the master clock signal. The pulse signals are applied to a combination logic of OR type giving an output signal combining the outputs of said plurality of flip-flops.

Operational results of GPS in timekeeping

Abstract: In the Time Service Department of the U.S. Naval Observatory, there are several operational programs that utilize time from the Global Positioning System (GPS) satellites in one form or another. 1 The monitoring of GPS time, derived from the ensemble of satellites, to ensure that it stays within one microsecond of the U.S. Naval Observatory Master Clock and to determine the quality of its performance between uploads. 2 The monitoring of the individual spacecraft clocks to determine their performance, both over the short term and the long term. 3 The monitoring of Coordinated Universal Time (UTC) as derived from GPS time in order to ensure that the accuracy of GPS as a time distribution system is good to 100 nanoseconds. 4 The performance of common-view time transfers between the Naval Observatory and other worldwide laboratories, to monitor timescales and to investigate signal propogation through the ionosphere. This paper describes these four projects and discusses their importance to the Global Positioning System and to the world timing community.

Hologram scanner control device

Abstract: PURPOSE:To enable to correct magnification error due to variance of laser oscillation wavelength by changing number of rotation of a hologram scanner motor. CONSTITUTION:When the frequency of master clock signal generated by a master clock signal generator 16 is made to correspond to oscillation wavelength of a semiconductor laser by a master frequency selector switch 21, number of rotation of the motor of the hologram scanner is changed according to laser oscillation wavelegth through a detecting circuit 17 etc. that detects phase difference between output of a motor rotation detector 15 and master clock. Accordingly, scanning speed of the hologram scanner is varied corresponding to laser oscillation wavelength, and magnification error in the direction of main scanning is corrected.

Phase comparator of digital logic pll circuit

Abstract: PURPOSE:To attain high resolution and high speed for a PLL circuit by extracting a latch data based on the leading/trailing edge of a reference clock and detecting phase difference information at the half clock of the reference clock. CONSTITUTION:Frequency division ratio control signals +G, -G are generated by detecting a phase difference between the output of a variable frequency divider 22 and an input signal DRF when the phase of a channel bit clock PLCK is led or retarded by a half of a master clock pm. A phase comparator 25 latches the output data of FFs 21-23 to FFs 26-29, the data is selected by the Q output of the FF 25 to detect it as a phase difference level. The input signal DRF is controlled so that the trailing of the PLCK is in the center. Since the signal of the frequency divider 22 and the input signal DRF are compared by a digital logic PLL circuit 4 in the shortest way and they are used after comparison in other blocks, high speed processing is attained.

Access port clock synchronizer

Abstract: Method and apparatus for rapid, low-jitter acquisition of a clock signal at a serial communication port. In the absence of communication over the port, and during clock acquisition, a free-running clock is generated for local communication. Following clock acquisition by a circuit which performs coarse phase adjustments, a simple logic network generates refined phase adjustment signals which drive a variable, nominal divide-by-32, counter so that the clock generated thereby is smoothly brought into synchronization with the acquired clock in one bit increments. In a typical application, at most 48 bit periods at the port are required to synchronize the clock, with a clock phase jitter of less than 1.1%.

Bit slip detecting system

Abstract: PURPOSE:To obtain only a bit slip detecting signal by eliminating a hazard, by synchronizing write and read-out address counters with a master clock, and latching a result of comparison of both counter values. CONSTITUTION:Sampling circuits 11, 12 sample write and read-out clocks WCK, RCK by a master clock MCK, and operate write and read-out address counters 2, 3 by a clock which has synchronized with the MCK. A comparator 7 compares values of the counters 2, 3, and when they coincide with each other, a bit slip detecting signal is outputted. However, even when they do not coincide, a hazard is generated at the time of variation of the count value, therefore, the hazard is eliminated by relatching an output of the comparator 7 to an FF13 by a PCKS.

Digital signal reader

Abstract: PURPOSE:To prevent oscillation of a circuit at the absence of a digital signal by detecting the digital signal and applying a clock signal to a circuit discriminating and reading logical '1' or '0' in place of the digital signal when no digital signal exists. CONSTITUTION:An input terminal 1 of the digital signal reader 7 is provided with a detection circuit 40 detecting whether or not the digital signal is inputted with a prescribed state and the output changes over a switch 41. The switch 41 outputs selectively alternatively either a master clock signal fed from an inverse amplifier consisting of an inverter 42, and resistors 43, 44 or a digital signal fed from an inverter 10. A resistor 45 and a capacitor 46 constitute a low-pass filter. When the switch 41 is thrown to the position of the inverter 42, a master clock outputted, it is compared with a reference value by an inverter 13 to lock a PLL circuit 6 of the post-stage by using the clock signal.

Photovoltaic clock and time piece for such a clock

Abstract: A solar timepiece comprises a drive unit including a commercially available battery clock mechanism mounted to the back of a support plate for the solar cells. The clock mechanism includes hands arbors which pass through an opening in the support plate. The support plate is angularly adjustable about the axis of the hands arbors so that the longitudinal extent of the solar cells can be made to coincide with the decoratively adapted orientation of light passage areas in the dial face located directly in front of it.

Method and apparatus for changing synchronizing clock

Abstract: PURPOSE: To prevent malfunction of each part of the circuit used for the titled apparatus by using a clock supplied to the 1st input terminal normally as a master clock and using a substitution clock as the master clock in switching the frequency of the master clock. CONSTITUTION: A dot clock pulse DCK and a substitution clock pulse FCK are supplied to input terminals A, B of a selector 20 via terminals T 1 , T 2 . In switching the frequency of the clock DCK supplied to the 1st input terminal B, the clock FCK is used with switching. While the clock FCK is used as the master clock, the clock DCK supplied to the 1st input terminal B is switched and then the clock DCK supplied to the 1st input terminal B is outputted as the master clock. Thus, in switching the frequency of the master clock. The level period of the active side of the master clock is not decreased and the malfunction of each part of the circuit is prevented. COPYRIGHT: (C)1988,JPO&Japio

Clock synchronizing circuit

Abstract: PURPOSE:To attain accurate synchronizing with a reference clock frequency in a short time by adding a circuit by which a voltage controlled oscillator of a sampling synchronous circuit is synchronized with a highly stable clock source by switching and applying the switching according to the reception state so as to recover a clock even when a reference burst signal starts entering. CONSTITUTION:If it happens that the reference burst signal cannot be received, when a loop change-over switch SW 2 is thrown to the position shown by a solid line, a voltage representing a phase difference between a VCO 4 and a highly stable master clock oscillator 5 oscillated at a frequency very close to the clock frequency in the reference burst signal is a control voltage to the VCO 4 and when the phase difference is lost, the VCO 4 is made stable. When the sampling synchronization is started, the switch SW 2 is thrown to the position shown in dotted lines, and a signal representing a phase difference between the clock signal in the reference burst signal and the signal of the VCO 4 controls the VCO 4, but since the difference between the oscillating frequency of the VCO 4 and the clock frequency is kept to a very small value, the oscillation of the control voltage at the output of a loop filter 3 is minute when the switch SW 2 is changed over, and the VCO 4 is not mis-synchronized with a spurious signal.

Interface device for digital exchange

Abstract: PURPOSE:To relay data transmission with either asynchronous or synchronous method by utilizing a multi-point sampling circuit used for data transmission with asynchronous method. CONSTITUTION:In the synchronous method, data from a digital exchange 1 become a receiving signal RD through a transmission controlling part 2 and sent to a terminal 4. The receiving timing of the signal RD depends on a receiv ing signal element timing signal RT from a clock reproducing circuit 7. On the other hand, a transmission datum SD from the terminal 4 is inputted into a multi-point sampling circuit 5 and sampled by a sampling clock SC from a master clock reproducing circuit 3. The sampled data are sent to the exchange 1 through a control part 2. And then, in the asynchronous method, data from the exchange 1 are inputted into the terminal 4 subsequently through the control part 2. On the other hand, data from the terminal 4 are inputted to the sampling circuits 5 subsequently, and sampled by the sampling clock SC. Thus, the data transmission can be relayed by either asynchronous or synchronous system.

Improvements in clocks

Abstract: The invention relates to a method of synchronising a master clock with a slave clock in a building in which an encoded time signal is generated in a master clock 12 and is transmitted to the slave clock 14 through the power supply 16 In this way, it is possible to avoid the need to rewire a building to connect the master lock with the slave clocks

Traveling adjusting control circuit

Abstract: PURPOSE:To synchronize and follow in a wide range and to output a stable traveling adjusting synchronization clock by inputting an external reference clock, taking a synchronization by a phase locked loop,and dividing a synchronization clock thereof by a variable frequency divider to obtain the traveling adjusting synchronization clock. CONSTITUTION:An external reference clock is given to a phase detector 4 from an external reference clock input terminal 2 and constitutes a phase synchronization loop together with a voltage control crystal oscillator 5 to obtain a crystal originated oscillating master clock 10. A frequency comparator 7 inputs an external traveling adjusting signal from the master clock and an external traveling adjusting signal input terminal 1 and a frequency thereof is outputted to a variable divider 6 as a dividing ratio setting signal 9. The variable divider 6 inputs the master clock 10 and it is divided by the dividing ratio indicated by the dividing ratio setting signal 9 and outputted to a traveling adjusting synchronization clock output terminal 3. In such a manner, the traveling adjusting synchronization clock having the wide range of a following characteristic and the high accuracy can be obtained.

Multi-direction multiplex communication equipment

Abstract: PURPOSE:To eliminate the deterioration of a code error rate without special adjustment such as suppression of absolute delay fluctuation of each circuit by providing plural deciding clocks to a master station against the fluctuation of open loop absolute delay time among the master station and slave stations and selecting the discriminating clock having the timing suitable for the said fluctuation. CONSTITUTION:Plural combinations of a code recovery circuit 9 deciding '1', '0' as a digital signal from an output signal of a demodulator 8 and recovering the digital signal and a temporary storage memory 10 storing temporarily its output signal are provided. Then a clock phase delay device 14 generates plural discrimination clock signals having a different timing so as to correspond to the timing fluctuation of the demodulator output signal based on a master clock signal and applies them to the plural code recovery circuits 9. A clock extraction circuit 11 extracts a reception clock signal out of the demodulator output signal, a phase comparator 12 compares the phase of the reception clock signal with that of the master station clock to detect the phase shift of the reception clock signal. Then the output of the code recovery circuit using the deciding clock signal having the least code error rate so as to decide the said shift is selected.

Circuit arrangement for a slave clock network

Abstract: The aim of the circuit arrangement for a slave clock network is for it to be possible to transmit not only control pulses, coming from the master clock, for stepping the slave clocks but also additional signals, for example audio frequencies, speech announcements, without there being mutual influencing of the control pulses and the additional signals This is achieved when a transmitting network is arranged at the infeed point for the additional signals, and a receiving network is provided in the case of each slave clock Furthermore, provision is made of a pulse-shaping device by means of which the square-wave control pulses generated by the master clock are converted into pulses having a low edge steepness Suitable components in the said networks result in the control pulses passing only to the slave clocks themselves and not to the receiving elements, for example loudspeakers The additional signals are transmitted free from direct current, with the result that due to their relatively high frequency actuation of the slave clocks by an additional signal is excluded

Asynchronous data transmission system in loop data highway

Abstract: PURPOSE:To transmit a data asynchronously with a clock on a highway by assigning time slots of an optional number to one data and transmitting the data while being added with a signal representing whether a data in the time slot is effective or not. CONSTITUTION:An asynchronous terminal device 1 is incorporated with a clock asynchronous with a master clock frequency and activated by the clock and a transmission buffer 6 fetches a data from the terminal device 1 by using the clock. An optional number of time slots are assigned to the data fetched to the buffer 6 and transmitted while being added with a signal representing whether or not the data in the time slot is effective. An output of a gate 13 is fetched to a reception buffer 7 by using it as a write clock. The data fetched this time is limited to that with a time slot made effective by a clock (flag).

Input circuit for data signal and timing signal

Abstract: PURPOSE:To reduce the set-up time and the holding time of both data and timing signals by using a low-speed clock undergone the time shaping to a master clock to give the time shaping to both signals. CONSTITUTION:Both data and timing signal inputs API and APSY are read by a low-speed clock PCK and turned into a low-speed data signal output PI 1 and a low-speed timing signal output SY 1 respectively. The clock PCK undergoes the time shaping by a master clock MCK through an FF 12 and is turned into a clock PPCK. The both signals PI 1 and PY 1 undergo the time shaping through an FF 13 and an FF 14 respectively by the signal PPCK. Thus the data and timing signal outputs PI2 and SY2 are obtained. Then both signals APSY and API are readby the clock PCK and therefore both the holding time and the set-up time can be increased.

Accuracy monitor method of sampling cycle

Abstract: PURPOSE:To monitor the presence or absence of a fault with high accuracy by measuring the width of a sampling cycle by the time decided by the executing time and frequency of an instruction word of a program and comparing the measured value with a standard for decision. CONSTITUTION:A circuit device which fetches the input information by sampling consists of a crystal oscillation circuit 1 which produces the master clock signal, a dividing circuit 2 which divides the master clock signal to produce the sample signal, a sample holding circuit 3 which fetches the analog input information synchronously with the sample signal, an A/D converting circuit 4, a memory 5 and a primary arithmetic unit 6. Then a specific program for monitor of sampling cycle accuracy is stored to a memory of the unit 6. This action is repeated by making use of the processing idle time. The specific program includes an increment instruction, a cycle shift deciding instruction and a branching instruction with repeats both said increment and deciding instructions. Then the program is measured by the time decided by the executing time of an instruction word. This measured value is compared with the upper and lower limit levels of the deciding standard. Thus the presence or absence of a fault can be monitored with high accuracy.