Showing papers on "Master clock published in 1990"

An overview of clock synchronization

Abstract: A distributed system consists of a set of processors that communicate by message transmission and that do not have access to a central clock. Nonetheless, it is frequently necessary for the processors to obtain some common notion of time, where ~time :~ can mean either an approximation to real time or simply an integer-valued counter. The technique that is used to coordinate the notion of time is known as clock synchronization.

Clock distribution apparatus and processes particularly useful in multiprocessor systems

Abstract: Clock pulses from a master oscillator are distributed in a multiprocessor computer system so that they arrive at a large number of utilization points located in operating clusters of modules within extremely tight time tolerances of each other. The delays associated with each component, electrical or optical connection, cable or the like are determined by direct measurement or by using known standard characteristics. A time delay budget for each complete clock pulse path from the point of initial divergence from the master clock source to the final chip delivery point is logged and summed. Components capable of introducing predetermined amounts of time delay are incorporated in some or all clock pulse paths. These components are adjusted so as to balance out the differences determined from the clock path budgets. The clock paths are implemented in electrical components either alone or in combination with optical components, or in substantially all optical configurations. One arrangement for controlling optical skew includes an arrangement of optical elements physically displaceable in a coaxial direction relative to one another. Skew adjustment networks employ a unique composition of coarse and fine selectable delay arrays implemented either by electrical components, optical components, or a combination thereof.

System for synchronizing clocks between communication units by using data from a synchronization message which competes with other messages for transfers over a common communication channel

Abstract: In an arrangement for synchronizing data and other information in a computerized system which comprises a common serial data communication channel (212), two or several collaborating units (201) are arranged connectable to the channel, wherein a respective unit comprises a clock (207). A main clock is included in the system and the clock in one of the units can be used as main clock. The units with associated communication element and communication channel are arranged in such a manner that the time of the main clock can be transferred to the clocks of the other units. The clocks are arranged so that they can operate with a common time base. The units/communication elements comprise hard- and software or hardware which brings about the setting of a respective clock with predetermined accuracy in dependence on the main clock time.

VLSI clocking system using both overlapping and non-overlapping clocks

Abstract: A clocking methodology for VLSI chips which uses global overlapping clocks plus locally or remotely generated non-overlapping clocks. Two overlapping clocks and two non-overlapping clocks are thus available in each block of a chip for use as timing edges. The global overlapping clocks are used where possible to provide timing advantages, while the non-overlapping clocks are used to eliminate race conditions as data propagates down a pipeline of transparent registers. Generally, one non-overlapping clock has an edge which must fall before a clock edge of the other non-overlapping clock rises and an edge which must rise after a clock edge of the other non-overlapping clock falls. These signals may be applied to adjacent stages to prevent race conditions; however, the "dead" time between the falling of one clock edge and the rising of the other clock edge has performance costs. Overlapping clocks are used whenever such race conditions can be avoided, as at the ends of the register pipeline, with the resultant performance improvement. The non-overlapping clock signals are preferably derived from the overlapping clock signals inside each block rather than globally so that it is easier to control the skew between phases of the non-overlapping clock signals. Such use of local non-overlapping clock generators in each block also reduces the amount of capacitive loading on the global overlapping clock network, thereby allowing faster edges and smaller skews on the global overlapping clock which further improves the performance of critical timing paths which use the global overlapping clock.

Method for synchronizing the phase of clock signals of two clock generators in communications networks

Abstract: Method for synchronizing the phase of clock signals of two clock generators in communications networks. Using the present method, the phase relations of clock signals that are derived from oscillator clock signals in two clock generators are synchronized such that the phase relations of the clock signals coincide regardless of the distance between the two clock generators. To this end, one clock generator is defined as a reference clock generator and reference clock signals formed therein are communicated to the other further clock generator. In the latter, the generated further clock signals are synchronized with the incoming reference clock signals and the clock signals synchronized in this fashion are forwarded to the reference clock generator. In the latter, the phase deviation of the internally formed clock signals and of the incoming clock signals is measured and correction information is formed and forwarded to the other further clock generator. The phase relation of the clock signals is corrected in the other further clock generator in conformity with the correction information.

Phase-locked loop signal generation system with control maintenance

Abstract: A phase-locked loop system having as input a stable refernce clock signal and outputting a master clock signal. The phase of the stable reference clock signal is compared to that of the pre-scaled master clock signal and the difference represented by an analog error signal which is converted to a digital signal by an A/D converter (116). The digital signal is then transformed into an analog control signal by a D/A converter (120) and applied to a VCO (128) which generates the master clock signal, If the stable reference clock signal has degraded or is lost the A/D converter (116), which receives its sampling clock in part from the stable reference clock signal, stops sampling and thus stops producing digital signals. The last good digital signal is maintained, the last good analog control signal is maintained and thus the master clock signal is maintained.

Clock synchronization algorithm for address independent networks

Abstract: A distributed algorithm for clock synchronization in address independent networks such as token rings and token busses is described. Synchronization is accomplished by using the fastest clock in the network as the master clock against which all other clocks in the network are synchronized. An algorithm is implemented in which each node sends out a message to all the other nodes in the network when its timer times out to tell its time. If a node receives a message with a higher clock time before it has had an opportunity to send out its own message, that node assumes that it is not the fastest node and it will not send out its message. Provision is made for maximum and minimum delays that are expected within a particular network. It has been proven that after a few cycles, all nodes will be synchronized to the node with the fastest clock and that this node will be the only one to transmit its time.

Method and apparatus for setting clock signals to predetermined phases at remote broadcast sites in simulcast systems

Abstract: A coherency generator for providing signals to control the time and phase coherency of data information signals in an overlap region of a simulcast system that comprises a control site and a plurality of remote broadcast sites. A channel card located at each remote site derives from the information signals a master clock signal for synchronizing the broadcast of data information on an RF carrier. At substantially regular intervals a transmit section of the coherency generator transmits a synchronization command signal after detecting a predetermined sequence of ones or zeros. A receive section of the coherency generator issues a reset pulse to the remote site channel card upon detecting a predetermined pattern of values of a preselected data bit, and following detection of the synchronization command pulse. The reset pulse clears the memory elements of the channel card, setting the phase of the clock signal.

A method for radiotelephone autonomous registration.

Abstract: A cellular radiotelephone autonomous registration method. The radiotelephone attempts registration when a clock count transmitted by the system equals or exceeds the radiotelephone's threshold count. The radiotelephone then scans available channels for proper signal strength and attempts to seize that channel. If the channel seizure fails, the threshold count is updated with the clock count plus a random integer and the next channel seizure attempt is made when the next master clock value equals or exceeds this value. This method increases the length of time between failed channel seizure attempts, thereby decreasing the load on the radiotelephone's power source.

Implementation issues in clock synchronization

Abstract: We present some results from an experimental implementation of a recent clock synchronization algorithm. This algorithm was designed to overcome arbitrary processor failures, and to achieve optimal accuracy, i.e., the accuracy of synchronized clocks (with respect to real time) is as good as that specified for the underlying hardware clocks. Our system was implemented on a set of workstations on a local area broad-cast network. Initial results indicate that this algorithm can form the basis of an accurate, reliable, and practical distributed time service.

Phase adjustment circuit

Abstract: A phase adjustment circuit uses a broad band circuit for processing a plurality of high speed highway data comprising m bit frames The phase adjustment circuit provides a master frame pulse based on a frame pulse selected from respective frame pulses in the high speed highway and delayed in phase by the maximum amount and provides a master clock based on a high speed highway clock corresponding to the master frame pulse The phase adjustment circuit receives a plurality of high speed highway data by using the master clock and the master frame pulse

Method and apparatus for synchronously distribution digital signals in high speed systems

Abstract: Method and apparatus for ensuring synchronism among modules of a distributed digital system (DDS) to a master clock signal is disclosed. The master clock signal is distributed at a frequency f c /N, and circuitry associated with each module multiplies the distributed master clock signal by N to provide a desired sync frequency f c to each module.

Bit phase synchronizing circuit

Abstract: PURPOSE:To improve a malfunction margin and to reduce the power consumption by sampling an input data with an in-phase or opposite phase clock and selecting a clock phase without any data change point thereby synchronizing the phase. CONSTITUTION:A clock inputted from a terminal 2 is inputted to a clock phase selection circuit 4, from which an in-phase or opposite phase clock is outputted, a data inputted from a terminal 1 is extracted with a data change point detection circuit 3 by using the said clock to detect the change point of the data. A clock phase control circuit 5 outputs a signal to the clock phase selection circuit 4 to vary the clock phase and discriminates it that the synchronization is taken when no change point exists. Then a data extracted once by the data change point detection circuit 3 is extracted by an identification circuit 6 by using a master clock and outputs the data synchronously with the clock outputted to a terminal 8 to a terminal 7. Thus, the margin at malfunction is improved and the power consumption is reduced.

Digital phase-lock loop system with analog voltage controlled oscillator

Abstract: A phase-lock loop scheme which can be implemented in an application specific integrated circuit using CMOS elements is disclosed which is directed to controlling a plurality of slave gate array circuits such that each of the master gate array circuit and the slave gate array circuits are clocked at the same time and are within a fixed time delay from a device reference clock signal. The master gate array circuit receives the input clock synchronization signal from the master clock of the device containing the master and gate array circuits and produces an internal clock signal which is then sent to each of the slave gate array circuits, by means of equal delay paths. The phase-lock loop circuitry utilized by each of the gate arrays can be implemented on program logic array chips along with the logic which receives the synchronized clock signals generated by the respective phase-lock loops of each of the gate array chips. Both fixed and automatic gain and damping controls for the phase-lock loops are also disclosed.

Dynamically variable digital delay

Abstract: An ultrasound system (100) for investigating a subject (91) comprises a probe (102), a signal processing module (104), and an interconnecting cable (106). The probe includes an annular phased array transducer (120) defining multiple signal processing channels Ch1-CH12. The signal processing module includes a controller (106), a transmitter (110), a receiver (112), delay circuitry (114), and a video section (116). Within the delay circuitry, each signal processing channel includes an inphase branch and a quadrature branch. Each branch includes an analog-to digital converter (ADC 412, 422) and a delay first-in-first-out (FIFO 416, 426) memory. Dynamically variable delays are implemented by varying the sampling and FIFO input rates relative to constant FIFO output rates. The variable clock rates are derived by switching between phase-staggered replicas of a master clock MCLK, which has a rate at the nominal center frequency of the ultrasound signal prior to sampling. The timing circuit (700) used to derive the variable clock rate signal uses a focus FIFO (706) to serve as a timing buffer between the variable clock rate signal and the master clock signal. Inphase data streams from each channel are combined in a pipelined adder (314); quadrature data streams are similarly combined. An interpolator (318) permits accurate combinations of the summed inphase and quadrature data streams. The resulting combination is directed to the video section for output. Advantages of the disclosed system include low signal processing, memory and data rate requirements, resulting in a more reliable and economical high-performance ultrasound system.

Remote monitor controller

Abstract: PURPOSE:To improve accuracy for time matching at a slave-slave station without provision of a master clock for each slave station by allowing each slave station to set a time matching period time again at a period shorter than a time matching period time in a master station by an internal counter and sending the time synchronizing data to the slave-slave station for time matching. CONSTITUTION:When a slave station receives a time synchronizing data, the slave station B starts an internal timer 11 immediately and the time matching period time is set at a period shorter than the time matching period time in the master station immediately again. When the time is reached, it is informed to a transmission section 10. When an interrupt signal for time matching to the slave-slave station is inputted by the internal timer in the transmission section, the time synchronizing data comprising the HDLC procedure is generated and when the interrupt input signal at the time matching start point of time is inputted, the time synchronizing data is sent to a slave-slave station C and after the transmission, the transmission protocol with the slave-slave station is interrupted and the flag transmission by the HDLC procedure is started. When the interrupt signal is inputted, the transmission section applies transmission processing the execution data representing the start of execution according to the HDLC format. The slave-slave station receiving the signal applies time matching similar to a conventional slave station.

Method for synchronizing a clock, generated with the assistance of a counter, to a reference clock

Abstract: In order to replace a reference clock s R , as needed, and without phase shift, with another clock f, the latter clock must be synchronized to the reference clock in frequency and in phase. Since the reference clock can fail or can be disturbed, undesirable synchronizations often occur in such cases. An error-free, phase-wise optimal synchronization of the two clocks is achieved and synchronization is carried out as a rule only when a defined edge of the reference clock appears within a time range defined with reference to the clock f.

Method and apparatus for synchronizing multiple CD players

Abstract: A synchronization system for multiple CD players (12), (14), (16) and (18) includes a controller (20) that generates four separate sampling frequencies for input to the word clock inputs of the CD players. A master word clock provides a master clock signal that is input to CD player (12) and then multiplied by multiplier (40). The output of multiplier (40) is divided down by variable dividers (48), (50) and (52) to provide the sampling frequencies for the remaining CD players (14), (16), and (18). Each of the disks (54) has a header (80) disposed on the beginning of each of the program tracks. This header has a unique synchronization signal associated therewith that outputs data corresponding to the position of the output digital data. During output of the data associated with the header, a difference between positions of the different CD players is determined. This difference is stored in the controller (20) and then the divide ratios of each of the dividers (48), (50) and (52) adjusted to change the sampling frequency on the output thereof, resulting in a slipping of samples, until the difference between the sample frames of each of the CD players is set equal to zero.

Method for automatically setting autonomous radio clocks

Abstract: The method achieves the object of how it is possible for a day counter/calendar module in radio clocks to be expediently automatically loaded on first being installed or after a service. Advantages such as, e.g., short receiver on duration, abandonment of the use of special real-time transmitters, noise-free (fail-safe) mode of operation, independence of time-of-day limits, and the production of cost effective radio clocks are principally maintained if as many norms, introduced standards and existing networks in radio, telecommunication and data technologies or power supply are observed in the method. The method delivers a suitable, brief and relatively rare transmitter time signal in coded form and with a time reference. The devices required for this purpose in the radio clock for loading the day counter/calendar module are described.

An advanced test system architecture for synchronous and asynchronous control of mixed signal device testing

Abstract: The authors present a tester capable of generating and measuring real-time-managed mixed signals by means of a dual master clock and master/slave multi-sequencing. This tester can test devices under conditions very close to their real working environment. The tester thus readily enhances testing reliability and improves testing throughput promptly. A powerful software package, combined with a library-oriented application environment, eases the job of developing tests for mixed-signal devices. >

Apparatus and method for synchronizing the signal averaging clock of a Loran C. receiver to the clock of a Loran C. transmitter

Abstract: Radio signals containing Loran C pulses from stations from a desired chain are amplified, filtered and ensembled averaged in an acquisition memory which is accessible by a controlling microprocessor. By staggering the ensemble averaging of the first four pulses in a station pulse group in time with respect to the last four pulses of the same pulse group, cross correlating the composite pulses formed by averaging the first four and last four pulses of the station pulse group with the help of the microprocessor provides time skew information which is used to adjust the receiver's master clock to align it with the clock of the transmitter. By varying the amount of time stagger, an ever finer resolution adjustment range is achieved. When the staggered averaging cycle times would exceed the time between successive ensemble averaging cycles without stagger, then successive ensemble averaging cycle time is employed for master clock adjustment. Cross correlation of the composite pulse formed by averaging the eight pulses gathered during the most recent unstaggered averaging cycle with the composite pulse averaged from the eight pulses of the previous average cycle can then be used to yield clock skew information. As the receiver clock becomes more closely aligned to the transmitter clock, the ensemble averaging process improves.

Development of a GPS time comparison system and the GPS common-view measurements

Abstract: An L1 band (1575.42 MHz), C/A (coarse/acquisition) code GPS receiver for precise time comparisons has been developed. GPS measurements in common-view have been carried out between the Korea Standards Research Institute (KSRI) and the Communications Research Laboratory (CRL), Japan. The frequency stability of the KSRI master clock has been measured against the master clock of CRL for 50 d. The frequency stability is about 1 part in 10/sup 13/ for the averaging time of 4 d. >

Broad band circuit added with elastic memory function

Abstract: PURPOSE:To realize a high speed time division switch by latching a serial signal of an input highway by an individual clock for each highway after parallel conversion and applying serial conversion to an output with a multiplex parallel serial conversion section based on a master clock. CONSTITUTION:A serial signal of each highway is converted and outputted into k-bit parallel signal based on highway clocks #1-#k by parallel expansion sections 101-10k. The parallel output is latched simultaneously at a latch circuit 30 with a clock synchronized with the master clock from an internal control section 40. Thus, equal length and phase adjustment are applied. A conversion circuit 50 applies a latch output as the same input to apply time position conversion and outputs a serial signal by multiplex parallel/serial conversion.

Clock input circuit

Abstract: PURPOSE:To simplify the circuit by comparing an output of an integration circuit receiving a clock pulse with a prescribed duty ratio repeating the charge/ discharge at a prescribed time constant with a threshold level at the end of the pulse and outputting the pulse as it is or with inversion. CONSTITUTION:With an external master clock C1 having a narrow width inputted, even when an input potential of a comparator 6 with hysteresis charges a capacitor 4 when a MOSFET 3 is turned on while the level of the clock C1 is logical charge, the capacitor 4 is discharged by a MOSFET 2 turned on by an output of an inverter 1 and the output of the comparator 6 remains logical '0' and a wide pulse being the inversion of the clock C1 is outputted to a terminal 11. When an external master clock C2 with a wide width is inputted, the output of the comparator 5 is logical '1' or logical '0' but a D-FF 6 holds an output of the comparator 5 at the trailing of the clock C2, the level of a terminal Q of the FF6 is always logical '1' and the output 11 has a wide pulse. Thus, a pulse with a prescribed width is generated by a simple circuit.

A monitor for measuring noise radiated from a ship

Abstract: The system comprises a remote receiver 3 for receiving underwater noise, means to determine the range of the ship from the receiver, transmission means 4 to transmit noise and range information to the ship, and ship receiver means 16 to receive the transmitted noise and range information. The remote receiver 3 preferably includes an omni-directional hydrophone assembly. The remote receiver is suspended by a flexible cable 5 from a buoy 1 or float so as to be located at a preselected depth. The range is determined by including a master clock on the ship 20 and a synchronised clock 15 colocated with the remote receiver, the transmission means being arranged to transmit time signals from the synchronised clock and the ship receiver being arranged to compare the master clock time with the received time signals.

Method and apparatus for synchronized sweeping of multiple instruments

Abstract: Time/frequency skew between a plurality of simultaneously operated swept instruments (64,68) is minimized by sharing a common master clock signal among the instruments and resetting the phases of internal clocking signals in each instrument to known states. Once reset, the clocking signals in each of the instruments operate in tandem. Consequently, the triggering latency period among all the instruments is uniform and subsequent triggered sweeps begin at substantially the same instant, providing accurate sweep tracking among a plurality of instruments.

Image data processor

Abstract: PURPOSE:To prevent gradation properties or resolution from being lowered at the time of conversion of image data and obtain image data with high quality by subjecting binary data to pulse width modulation according to the density of multi-valued image data. CONSTITUTION:Upper order two bits (VD7, VD6) of a multi-valued image signal inputted to a demultiplexer 12 are used as a selection signal 24 for the demultiplexer 12. That is, density data for 256 gradations is divided into 4 hierarchical levels each of which corresponds to 6 bits (64 gradations), before being inputted to dither processing circuits 15-18. In each of the circuits 15-18, 6-bit density data is compared with a 8X8 dither matrix, and 1-bit signals D1-D4 are outputted respectively from the dither processing circuits. The signals D1-D4 are outputted after being converted into pulse signals which are obtained by multiplying by different integral numbers a pulse width modulation (PWM) clock signal 26 (PCLK) obtained by halving the frequency of a master clock signal CLK. An output from a logical circuit 23 is used as a driving signal 27 (LD) for actually driving a laser.

Musical sound synthesizing device

Abstract: PURPOSE:To simplify the constitution of the musical sound synthesizing device which changes in timbre with time by controlling the number of words of delay data corresponding to musical sound pitch. CONSTITUTION:A musical sound waveform from an initial waveform generator 1 is circulated in a digital filter 5 of each cycle and varied with time. The musical waveform circulated in the filter 5 is written in a first-in first-out FIFO 3 through a shift register 4 and then read out and outputted to a sound system 6. At this time, clock pulses phiO of a clock pulse generator 80 are passed intermittently through a gate 83 to generate master clock pulses phiG, which are frequency-divided by the number of bits per word of waveform memory ROMs 11-13 and the register 4 and inputted to an address counter 83 so as to control the delay time of the register 4 corresponding to the musical sound pitch. Consequently, the address variation and pulses phiG are synchronized with each other. A musical sound which varies in timbre with time is generated with the simple constitution.