Showing papers on "Master clock published in 1991"

Method for synchronizing a wide area network without global synchronizing

Abstract: A frequency-hopping packet communication system without a master clock or master control unit is based on use of a receiver's frequency hopping timing and identification to control communication. A frequency-hopping band plan, involving the number of channels and the pseudo-random pattern of frequency change and nominal timing of changes, is universally known to each node in the network. A transmitter acquires synchronization with a target node by use of information previously received from or about a target indicating timing of present idle frequency hop of the target receiver. Each receiving node establishes in each station or node a table of receiver frequency hopping sequence offsets (hop timing offsets) of each other node within its communication range, and each node announces its presence on each frequency in a packet with a hop timing offset indicator. The hop timing offset indicator is a key used to read a table to allow nodes to set themselves in synchronization with one another. A location indicator built into the address of each packet is used to randomize an ordered frequency-hopping table at each node. Frequency-hopping is implemented by the division of communicaton slots and the accumulation of slots into epochs, wherein each epoch equals the total number of available slots (number of channels times the number of time frames per channel). The transmitting node tracks the pre-established frequency-hopping pattern for its target receiver based on previously-acquired information.

Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like

Abstract: A method is provided for eliminating hold time violations in implementing high-speed logic circuits specified in circuit configuration data includes the steps of providing a synchronizer flip-flop device or latch corresponding to every flip-flop device or latch specified in the circuit configuration data. The synchronizer flip-flop is provided immediately upstream in the data path from its corresponding original user flip-flop device. A predetermined amount of delay is added to the user's original clock and data signals. A synchronizing clock signal generator provides a delayed synchronizer clock for each master clock in the circuit which is provided to each user flip flop.

Method and apparatus for communicating different categories of data in a single data stream

Abstract: A system for transmitting different categories of data in a single data stream generates program data, receiver control data, and program specific tag data for insertion into a single data stream. Program data is combined with receiver control data to form data groups. Headers are generated containing tag data. Each successive header is combined with a plurality of data groups to form a plurality of units. The data stream is constructed by joining successive units for transmission. A receiver for receiving the data stream detects the receiver control data and the tag data, and recovers the program data in response thereto. A program is reproduced from the recovered program data. The system runs off a master clock having a fixed frequency. Program data is sampled at a first rate that is a function of the master clock frequency. The receiver control data is sampled at a second rate that is a function of the first sampling rate. The tag data is sampled at a third rate that is a function of the second sampling rate. Preferably, the first sampling rate will be an integer factor of the master clock frequency, the second sampling rate will be an integer factor of the first rate and the third sampling rate will be an integer factor of the second rate.

A digital correlated double sampling circuit for sampling the output of an image sensor

Abstract: A digital correlated double sampling circuit employs three registers and a single clock signal to sample the output of a charge transfer device The first register samples the reset reference value on the falling edge of the master clock cycle while the remaining two registers sample on the rising edge The second register samples the image level and the third register samples the output of the first register, thus effecting a delay of the reset reference level The outputs of the second and third registers, that is, the image level and the reset reference level, are differenced to provide a noise-free image signal

Method for synchronizing interconnected digital equipment

Abstract: Optimized synchronization planning and clock distribution for a network of interconnected digital equipment is achieved by designating a network node at the highest stratum level as the master clock node, forming a group of all unassigned nodes connected to the assigned node or nodes, selecting subgroup of all nodes from the group wherein the subgroup includes all nodes having the highest stratum level of the group, limiting the subgroup to the nodes which have a desired characteristic when such nodes are included in the subgroup, determining the synchronization performance of each node in the subgroup according to a predetermined criterion, assigning one node from the subgroup as a clock timing receiver wherein the one node exhibits the best performance for nodes in the subgroup, and iterating the method at the forming step. In order to obtain an optimum synchronization plan, it is desirable to repeat the entire method described above for the complete set of nodes which are capable of being designated as a master clock node. When more than one node is capable of being considered as a master clock node, the synchronization planning method is then completed by computing the network synchronization perforamnce for each synchronization plan related to a different designated master clock node and choosing the synchronization plan which offers the best network synchronization performance as computed above.

Built-in self-test global clock drive architecture

Abstract: A BIST clock driver for providing memory elements in a combinational and sequential logic circuit with a global clock signal during user mode and a test clock signal during testing. The clock driver also supplies clock signals to memory circuits that have clock inputs supplied by random logic. The clock driver supplies the random logic with a global clock signal. A clock multiplexor receives the generated clock and the test clock signal and provides the memory element with the generated clock signal during user mode and the test clock during testing of the memory element.

Two-fail-operational fault-tolerant multiple clock system

Abstract: A multiple-fail-operational fault-tolerant clock having a plurality of interconnected and identical clock modules, that provides a fault tolerant clock signal despite some clock module failures. The clock incorporates fault-tolerant operational diagnostics so that a working clock module may be voted for supplying the output clock signal.

Apparatus and method for fractional frequency division

Abstract: The present invention provides fractional frequency dividers using inexpensive digital components in a relatively simple circuit for producing a substantially spectrally pure clock signal, free of significant time or phase jitter The synthesizer and method include a reference frequency register for providing a frequency set value, which frequency set value is proportional to the desired frequency, a summer, having a finite storage capacity, for adding the frequency set value to a stored summed value to form a new summed value which new summed value is stored as the summed value A carry signal is generated when the new summed value exceeds the finite storage capacity In that event, only that portion of the new summed value in excess of the finite storage capacity is stored as the summed value A variable time delay clock generator generates the desired clock signal so that each pulse is generated in response to the carry signal and delayed by a delay period equal to the period of a master clock signal minus a fraction of the master period This fraction is relative to both the summed value and the frequency set value In the preferred embodiment the frequency set value is equal to the desired frequency divided by the master frequency times a constant, which constant is related to the finite storage capacity and the fraction is equal to the summed value divided by the frequency set value

Impulse clock system

Abstract: A clock system of the impulse type consisting of stepper motor driven secondary clocks (16) and a master control (10). Each secondary clock (16) includes a stepper motor (22) directly driving the minute hand (26), an hour hand (28) driven by the minute hand (26), and an emitter (90) and detector (92) on opposite sides of a gear (50) of the movement and coacting with a window (50a) in the gear to determine the absolute position of the clock for comparison to the master control time. At five minutes before 6:00, the sensor, (64) of each secondary clock (16) is activated by a signal from the master control (10) and a series of reset pulses are thereafter transmitted to the secondary clocks (16) with each secondary clock stopping as the window (50a) in its drive train gear (50) moves into alignment with the emitter (90) and detector (92) of its sensor mechanism (64), whereafter all of the remaining clocks are moved to 6:00 by a rapid pulse train.

Telephone exchange apparatus with communication line clocking

Abstract: In a telephone exchange apparatus which accommodates digital communication liens and employs a slave synchronization system in which a clock is extracted from a signal received from the network, an exchange switch is operated in synchronism with the extracted clock so as to prevent data omission caused by a difference between operating frequencies of a network and an exchange apparatus. If there is a phase difference between a pre-switching clock and a post-switching clock when the extracted clocks are switched upon changing communication lines, the postswitching clock is delayed by the phase difference between the two clocks so as to cause the phase of the post-switching clock to coincide with the phase of the pre-switching clock.

Data processing system having four phase clocks generated separately on each processor chip

Abstract: A digital system generates a single-phase master clock (MC) and distributes it to multiple cards (1210, 1220, 1230, 1310, 1320, 1400) and chips incorporating the functional logic of the system. A circuit (1213, 1223, 1233, 1243, 1313, 1323, 1333) in each chip divides the single clock into four spaced clock phases at the same frequency as the master clock. The individual phases are then distributed to functional logic circuits (1211, 1221, 1231, 1311, 1321) within the same chip. The circuit generates the phases by detecting the midpoints of a triangular wave produced from the single-phase master clock.

Data referenced demodulation of multiphase modulated data

Abstract: A data referenced demodulator is provided for recovering differentially encoded multiphase modulated digital data such as QPSK modulated audio data. An analog carrier containing the differentially encoded QPSK data is converted to a digital waveform at an intermediate frequency that is a multiple of the QPSK bit frequency. The digital waveform is delayed in a shift register that samples the waveform at a clock rate which is a multiple of the intermediate frequency. Different stages of the shift register output the digital waveform one bit time earlier plus 45° and one bit time earlier minus 45°. These outputs of the shift register are multipled with the digital waveform using exclusive OR gates to provide differential QPSK detection. The shift register sampling clock is phase locked to a system master clock, which in turn is locked to the received data. In an illustrated embodiment, the sampling clock is 24 times the intermediate frequency, providing 15° phase resolution.

Master clock distributing method and apparatus using same

Abstract: A logic processing apparatus comprises a plurality of integrated circuits (6-1 - 6-n), a multi-phase clock generator (5) for distributing clock signals having different phases from one another to the respective integrated circuits (6-1 - 6-n), and a package (20), for air tight sealing the multi-phase clock generator (5) and the plurality of integrated circuits (6-1 - 6-n), which has an optical signal transmissible window for transmitting the master clock to the multi-phase clock generator (5) through the optical transmitting line (4).

Microprocessor synchronous timing system

Abstract: There is disclosed a timing system for use in a microprocessor for initiating microprocessor outputs onto an input sampling from an external bus in synchronism with a bus timing clock. The timing system is operative in a first mode for internally generating the bus timing clock and in a second mode for being driven from an externally generated bus timing clock. In the first mode, the timing system generates first and second inverse phase timing clocks responsive to an external clock source and independently generates the internally generated bus timing clock with the rising edges of the bus timing clock coinciding with the rising edges of the first microprocessor timing clock and the falling edges of the second microprocessor timing clock. In the second mode, the timing system generates the first and second microprocessor timing clocks in response to the externally generated bus timing clock. In both modes, the timing system initiates an output onto the bus upon the common assertion of the first microprocessor timing clock and the bus timing clock and initiates sampling of an input from the external bus upon the inverse assertion of the second microprocessor timing clock and the bus timing clock.

Interface circuit between a plurality of transmission lines and a high bit rate data terminal equipment

Abstract: A transmission line interface circuit receiving a plurality of channels of data (RDi) and a plurality of receiving clock signals (RCKi) respectively synchronized with the plurality of channels of data received from the respective transmission lines, allowing outputs of the plurality of channels of data (RDi') synchronized with a master clock signal (MCK) which is supplied from outside of the transmission line interface circuit, receiving a plurality of channels of data synchronized with the master clock signal (MCK), and outputting a plurality of transmitting clock signals (SCKi) and the plurality of channels of data (SDi) respectively synchronized with the plurality of transmitting clock signals (SCKi), contains: a plurality of first synchronization timing changing circuits (104R2, ··· 104Rn) for receiving the plurality of channels of data (RDi) synchronized with the respective receiving clock signals (RCKi), and making each bit of the respective channels of data synchronized with one (RCK1) of the plurality of receiving clock signals; and a plurality of second synchronization timing changing circuits (104S2, ··· 104Sn) for receiving the plurality of channels of data synchronized with the above one of the plurality of receiving clock signals, and synchronizing each bit of the plurality of channels of data with the corresponding receiving clock signals, respectively.

Time control method in computer networks

Abstract: A method for controlling time in hierarchically constructed computer networks with continuous synchronisation of clock modules, provided at the individual network levels (E1 to E3), to the time of a central main clock (HU) by means of messages, in which method time stamps can be issued by each clock module which, in addition to a clock-time field and a date field exhibit additional information fields relating to the synchronisation source (CLOCKNR), type of synchronisation, synchronisation delay and clock time resolution.

Efficient synchronization of clocks in a distributed system

Abstract: A probabilistic clock synchronization algorithm is proposed where processors in the system exchange time stamps and synchronize to a common clock value. Most of the previous algorithms for this problem have been based on a master-slave approach where all the slave processors synchronize to the clock value of a master. These algorithms are not distributed in nature and some of the assumptions made in these algorithms may become invalid if a large number of slaves try to synchronize with a master. The only distributed algorithm that is available was earlier proposed by A. Olson and K.G. Shin (1991). It is based on finding a cyclic path connecting the processors in the system and exchanging time stamp messages through this path. For the same level of synchronization accuracy, the proposed algorithm uses a much smaller number of messages. >

Clock generating apparatus, data transmitting/receiving apparatus and data transmitting/receiving method

Abstract: A data transmitting/receiving apparatus comprises a master clock signal and a slave clock signal which differ in phase with each other according to a basic clock signal. Serial data is input according to the produced master clock signal or slave clock signal, a protocol process is applied to the input serial data, and the serial data subjected to the protocol process is output according to the master clock signal or the slave clock signal. A start delimiter detecting signal is generated when a start delimiter indicating the first frame is detected in the input serial data and phases are exchanged between the master clock signal and the slave clock signal when there arises a shift on a bit boundary of the serial data when the start delimiter detecting signal is generated. The serial data is output according to the master clock signal or the slave clock signal having their phases exchanged with each other, thus the serial data is transmitted without delay despite a shift arising on the bit boundary of the serial data.

Synchronizing system in digital communication line

Abstract: A synchronizing system in a digital communication line comprises a plurality of local switches for storing at least one digital line and monitoring a first piece of busy information when a clock source is already present, the local switches, if a first new clock source occurs while the first busy information is indicating no busy state, being capable of transmitting a master right request to turn the busy information to the busy state and to specify the first new clock source as a master clock and, on receiving a master right specification with respect to the master right request, being capable of outputting the first new clock source as the master clock; and a master switch connected to the plurality local switches in a star manner, by a link transmission line for transmitting control information including the master clock, master right request and master right specification, for monitoring a second piece of busy information indicating a busy state, the master switch, if a second new clock source occurs while the second busy information is indicating no busy state, being capable of transmitting the second new clock source as a master clock and, if the second new clock source competes with the first new clock source in the local switches that has output the master right request, being capable of arbitrating the competition between the first and second new clock sources and selecting one of the clock sources to turn the busy information to the busy state and, if the first clock source is selected, outputting the master right specification to the local switches that have transmitted the master right request.

Operational analysis device of the scan path type having a single scanning clock and a single output phase for an integrated circuit

Abstract: The device comprises a first chain of scanning cells located at the stimulation input of each respective functional block of the integrated circuit and a second chain of scanning cells located at the assessment output of each respective functional block of the integrated circuit. Each cell comprises a master part, a slave part and switching circuit to alternately enable the master and slave parts under the control of respective master clock and slave clock signals coincident with opposite phases of a scanning clock signal having a substantially square wave. With each pair of chains of scanning cells there are associated clock generators to locally obtain the master and slave clocks from the scanning clock.

Video interface palette, systems and method

Abstract: A color palette selects a master clock from plural clock signals received at clock input terminals in response to a master clock selection control word received at control data terminals. A circuit forms a plurality of divided down clock signals from selected divide ratios of the master clock. A circuit selects a shift clock from among the divided down clock signals in response to at least some bits of an output clock selection control word received at the control data terminals. A circuit selectively enables and disables the shift clock in response to blanking data. A circuit selects a video clock from among the divided down clock signals in response to at least some bits of the output clock selection control word. A circuit synchronizes multiple bit words of color code received at color code input terminals with the master clock. A circuit outputs at least one memory recall address in response to receiving each multiple bit word of color code. A circuit stores color data words in a plurality of data storage locations, having associated memory recall addresses, and outputs a color data word upon receipt of an associated memory recall address. A circuit selectively writes color data words into these plural locations. A circuit synchronizes video control signals received at video control terminals with the master clock and provides the blanking data. A circuit selects for output between said color data words and true color data words received at said color code input terminals.

Sampling clock generating circuit for a-d conversion of a variety of video signals

Abstract: A sampling clock generating circuit generates a sampling clock which is used for the A-D conversion of a video signal. A master clock produced by a frequency synthesizer is demultiplied in frequency at dividing ratio NS by a programmable frequency demultiplier which is reset by the horizontal sync signal. The resulting sampling clock can have one of various frequencies depending on the combination of the frequency dividing ratio NM of the frequency synthesizer and the frequency dividing ratio NS of the programmable frequency demultiplier, so that it is fit for various video signals.

Digital communication system allowing time division multiplexing - sends fault alarm via all other exchange-interconnecting cables if cable fails from first exchange drawing clock signal from this cable

Abstract: After the failure of a clock signal delivering interconnect to an exchange, the next connected exchange sends on its own clock signal as well as a signal denoting the failure to all connecting lines. Clock priorities are compared at the following exchanges before establishing the new system synchronisation. One exchange can store the clock priority of the exchange delivering the clock signal serving as master priority. USE - Allows system to handle line breakdown, installation and priorities electrically.

Method and apparatus for grey level printing

Abstract: A method and apparatus for grey level printing includes a plurality of recording elements which are enabled for variable periods of time during a cycle of recording grey level pixels. For each recording element a comparator compares the count in a time-changing exposure counter with a multibit grey level data signal. The exposure counter is decremented/incremented by exposure clock pulses from a programmable exposure clock. The exposure clock includes a master clock and an address counter that provides an incremented address signal in response to each set of N pulses from the master clock. The address signal identifies a location in memory of a set of signals used to generate exposure clock pulses. The set of signals is output in parallel to a serial shift register and shifted out serially to form the exposure clock pulses for decrementing/incrementing the exposure counter.

Color palette timing and control with circuitry for producing an additional clock cycle during a clock disabled time period

Abstract: A clock control circuit 84 is provided which includes circuitry 98 for selecting a master clock from among at least two input clocks provided to clock control circuit 94, the selection made in response to master clock selection control signals. Circuitry 104 is coupled to circuitry for selecting 98 for providing at least first and second divided down clocks each being of a different divide ratio of the master clock. Circuitry 108 is coupled to circuitry for providing divided down clocks 104 for selecting an output clock from between at least the first and second divided down clocks in response to output clock selection control signals received by clock control circuit 84. Circuitry 120 is provided coupled to circuitry for selecting an output clock 108 for selectively controlling the output of the output clock, circuitry for controlling output clock 120 enabling output of the output clock in response to a first output clock control signal received by clock control circuitry 84 and disabling output of the output clock in response to a second output clock output control signal received by clock control circuit 84. Circuitry 120 is further operable to selectively output an additional output clock cycle in response to a control signal during a period when circuitry for controlling 120 has disabled output of the output clock.

Network synchronization unit for a telephone exchange

Abstract: In a telephone exchange apparatus which accommodates digital communication lines, and employs a slave synchronization system in which a clock is extracted from a signal received from the network. and an exchange switch is operated in synchronism with the extracted clock so as to prevent data omission caused by a difference between operation frequencies of a network and an exchange apparatus, if there is a phase difference between a pre-switching clock and a post-switching clock when the extracted clocks are switched upon changing of communication lines, the post-switching clock is delayed by the phase difference between the two clocks so as to cause the phase of the post-switching clock to coincide with the phase of the pre-switching clock.

Optical disk recording and reproducing device

Abstract: PURPOSE:To enable parallel concurrent recording and parallel concurrent reproducing with elimination of cross talk and to attain high speed data transfer as well as large cpacitization by using an optical head of plural convergent beams. CONSTITUTION:A clock for operating the device at the time of reproducing is extracted in a clock extracting circuit 12 by inputting either of regenerative signals from two photodetectors corresponding to two convergent beams. At the time of recording, the parallel concurrent recording is performed by using these two adjacent convergent beams according to a master clock. The two convergent beams are arranged to be separated from each other in order not to cause thermal interference at the time of recording. On the other hand, at the time of reproducing, the two regenerative signals are digitalized by A/D converters 3a and 3b with the clock from the circuit 12 respectively, and these signals are stored successively by an FIFO information storing means by a memory capacity. Across talk component to be superimposed from adjacent information tracks is contained in this information.

A novel design concept for small-skew clock LSIs with the self-delay-adjustment

Abstract: A novel concept for +or-50-ps-skew clock distribution LSIs for use in large computers is presented. The keys for obtaining this are the separated distribution of the frequency and phase of the master clock, and the detailed design of self-phase-adjustment circuits. The basic idea of the method is described, with emphasis on design formulae for clock signal delay times. Bipolar clock LSIs have been designed and tested. A clock skew time of +or-50 ps has been obtained with an adjustable phase range of 3.7 ns. >

Recording and reproducing disk device

Abstract: PURPOSE:To easily seek a target track again in case of a seek error by imbedding a particular pattern, which is different from each zone and can be recognized without using a master clock, in a prescribed position of each track. CONSTITUTION:With regard to a recording and reproducing disk device to which an M-CAV system is applied, a particular pattern (mirror surface) is set up in each prescribed position of individual tracks S, R and T to show which one of zones A-C a track of on-track due to a seek error belongs to when the seek error takes place over the zones A-C. Consequently, which one of the zones A-C the track presently under on-track belongs to is recognized, and a master clock corresponding to this is selected, so that an on-track address is detected, and the reseek for the target track directly from an on-track position is feasible. By this method, uncertainty at the time of selecting the master clock is diminished, and the processing time can be shortened.

Through-passing method in asynchronous equipment

Abstract: PURPOSE:To attain through-pass for an asynchronous equipment with small sized circuit constitution even when a serial/parallel conversion section is employed by constituting a frequency offset absorbing section with a memory, a transmission clock generating section, a phase comparator and a multiplex section. CONSTITUTION:The frequency offset absorbing section 10 is constituted of the memory 6, the phase comparator 8, a master clock generator 7-1, a clock generator 7-3, the multiplex section 9, an up-down counter 11 and a counter set section 12 and requires the serial/parallel conversion section 1. However, the circuit scale is smaller than that of a conventional frequency offset absorbing section composed of two termination units, a master clock generator, a clock generator and the multiplex section. Thus, an optical terminal station repeater system passing through to an asynchronous equipment is constituted with a small scale circuit.