Showing papers on "Master clock published in 1995"

Variable sample-rate dac/adc/converter system

Abstract: A digital oversampling noise-shaping system includes a digital noise-shaped clock signal generating circuit, including a DCO operating at a fixed master clock rate, that receives a digital input sample clock signal having an input sample rate and produces a noise-shaped clock signal having a variable rate with an average rate equal to a multiple of the input sample rate. In one embodiment, an interpolator is coupled to the clock signal generating circuit and receives the digital input samples at an input sample rate and, responsive to the noise-shaped clock signal, upsamples the digital input samples at the variable rate. A hold circuit repeats the interpolated samples at the master clock rate. A digital noise-shaping circuit, coupled to the hold circuit, performs digital noise-shaping on the repeated samples received from the hold circuit. In another embodiment, a decimator is coupled to the clock signal generating circuit. Digital input samples having an input sample rate are latched to the input of the decimator at a rate controlled by the noise-shaped clock signal. The clock signal generating circuit includes a PLL in one embodiment. The digital noise-shaping circuit, in one embodiment, includes sigma-delta modulator in which the downstream one of first and second integrators operates at a reduced multiple of a fixed master clock rate.

Accurate alignment of clocks in mixed-signal tester

Abstract: Asynchronously-generated digital and analog clocks in a mixed-signal test system are accurately aligned for repeatable and deterministic testing. A variable-frequency digital master clock signal is used in direct digital synthesis of an analog clock signal which is asynchronous to the master clock signal. A resync command inhibits the analog clock signal until the analog clock signal is in a desired phase relationship to the master clock signal. The analog clock signal is thus phase-aligned with the master clock signal in a known and deterministic relationship. The resync command also aligns the phase of the analog clock signal with the pattern of stimulus signals applied to the device under test. Aligning the analog clock signal with the master clock signal and with the stimulus pattern assures that test results are consistent from test-to-test. A phase-locked loop removes spurs from the synthesized analog clock signal. A jitter generator is provided for controlled jittering of the analog clock signal as needed for some types of test. An Nth occurrence counter allows for programmable introduction of an extra master-clock signal period in the test pattern when needed to avoid creating a metastable condition in the device under test.

Multiport analyzing, time stamp synchronizing and parallel communicating

Abstract: A plurality of digital transmission network analyzers are arranged to analyze and compare the appearance of a data packet on the plurality of ports of a network. Each analyzer has its own internal clock for time stamping of data packets in addition to other internal timing purposes. In order to synchronize the time stamping of the packet as it appears to each analyzer at a each different port, the clock outputs of the several analyzers are connected together; and a controlling CPU commands one of the analyzers to supply the master clock to the others. That master analyzer then commands the other analyzers to disable or disconnect their own clocks, thereby all of the analyzers involved in a given test are under timing control of the clock of the master analyzer. Packet headers and time stamps are transmitted between analyzers for comparison, analysis, and reporting to the controlling CPU. This analyzer intercommunication is done over a separate bus that interconnects all of the analyzers and the controlling CPU.

Disciplined time scale generator for primary reference clocks

Abstract: Methods and apparatus are disclosed for providing disciplined clock signals at a plurality of nodes located throughout a network. In the preferred embodiments, a plurality of clocks are ensembled to provide ensemble time base information. A universal clock signal such as from a global positioning satellite (GPS) or Loran receiver is also provided and the ensembled time information is disciplined to the frequency or the phase of the universal clock signal to provide syntonisation or synchronization throughout the network.

Method for monitoring the synchronization of clocks in computer networks

Abstract: A method for controlling clocks in computer networks of a hierarchical structure includes the continual synchronization of the clock modules provided in the individual network levels to the time of a central master clock by means of messages. Time stamps are output from each clock module. Besides a time-of-day field and a date field, these time stamps contain additional information fields relating to synchronization source, synchronization type, synchronization delay, and time-of-day resolution.

Multiport analyzing with time stamp synchronizing

Abstract: A plurality of digital transmission network analyzers are arranged to analyze and compare the appearance of a data packet on the plurality of ports of a network. Each analyzer has its own internal clock for time stamping of data packets in addition to other internal timing purposes. In order to synchronize the time stamping of the packet as it appears to each analyzer at a each different port, the clock outputs of the several analyzers are connected together; and a controlling CPU commands one of the analyzers to supply the master clock to the others. That master analyzer then commands the other analyzers to disable or disconnect their own clocks, thereby all of the analyzers involved in a given test are under timing control of the clock of the master analyzer. Packet headers and time stamps are transmitted between analyzers for comparison, analysis, and reporting to the controlling CPU. This analyzer intercommunication is done over a separate bus that interconnects all of the analyzers and the controlling CPU.

Clock generator using a state machine to switch between two offset clocks

Abstract: A simple structure for switching between two clock signals to produce an output without a glitch or short pulse. The invention is basically a three-input multiplexer controlled by a modified two-bit state machine. The state machine includes flip-flop memories which are driven by the two different clocks, as opposed to using a single clock as in a traditional state machine. The state machine output is used to control the three-input multiplexer, selecting between the first clock, the second clock and an intermediate high level signal during transition. The intermediate high level signal bridges the gap between pulses, eliminating any short glitches.

Three state phase detector

Abstract: A phase detector circuit receives both a reference clock signal and a sense clock signal and produces a synchronization signal if the sense and reference clock signals are in phase within a specified tolerance. A lead/lag signal is provided to a skew control circuit and accompanying delay circuits to increase or decrease the amount of delay on the reference clock signal and the sense clock signal if the two signals are not in phase within the specified tolerance. The sense clock signal is a feedback signal returned from logic circuitry, which originally receives the reference clock signal, which may be supplied by a master clock signal within a processor.

Master-slave multiplex communication system and PLL circuit applied to the system

Abstract: A sharp phase variation of a clock is suppressed when master/slave status of a first and second communication device is changed over. The first and second communication devices respectively include clock selection circuits and clock production circuits for producing a synchronous clock from the selected clock, respectively, and supply the selected clock as the synchronous clock to the other communication device which is a mating-side device. One of the first and the second communication devices is a reference selection side and becomes a slave side, and the other device is a mating synchronous clock selection side and becomes a master side. Respective data signals from the communication devices are bit multiplexed in a multiplexing device on the basis of the synchronous clock. The first communication device includes a delay circuit for delaying the mating-side synchronous clock by a phase difference between a clock transmitted from the selection circuit through the clock production circuit and a clock transmitted in the mating-side device from the selection circuit through the selection circuit and the clock production circuit. In this manner, both clocks inputted into the selection circuits are made synchronous by the delay processing, so that a sharp phase variation at the master/slave changeover is suppressed and the multiplexed output from the multiplexing device remains virtually undisturbed during a master/slave change over event.

Rf link control of satellite clocks

Abstract: A system and method for maintaining a precise time standard among a system of orbiting satellites is disclosed. In an illustrative embodiment (the figure), atomic clock data is circulated among the satellites (2, 4, 6) via RF crosslinks (10). Each satellite uses the received data as input to a Kalman process which acts to minimize the means squared error among the satellite clocks to form a set of 'ensemble clocks'. The resulting ensemble clock values are then transmitted (12) to an earth station (8) where an offset between the ensemble clocks and Universal Time is computed. The offset is transmitted (14) from the earth station to the satellites where it is used by the satellites to lock their on-board clocks to Universal Time, thereby creating a corrected system time. The corrected system time is transmitted, via RF crosslinks (10) to satellites not having operational on-board clocks. The satellites without atomic clocks employ phase locked loops to anchor their clocks to the corrected system time as it is received over the crosslinks.

Distributed global clock system

Abstract: A clock system for a distributed multiprocessor system includes a plurality of local clock circuits and a distribution network. The distribution network includes a plurality of interconnected routers. Each local clock circuit is associated with a processing node of the multiprocessor system. Each local clock circuit generates a global clock source signal, provides the global clock source signal to the distribution network, receives a global clock signal back from the distribution network, and generates a global time value based on a local clock signal and the global clock signal. The router is part of the distribution network of the multiprocessor system. The router receives the global clock source signals from each of the local clock circuits, selects one of the global clock source signals as the global clock signal and provides the global clock signal to the distribution network for distribution to each of the local clock circuits.

Synchronized DMT for multipoint-to-point communications on HFC networks

Abstract: This paper presents a method for synchronizing a large number of discrete-multitone-based modems for multipoint-to-point communications on hybrid fiber-coax (HFC) networks. Each newly-installed remote unit is first loop-timed to the central modem master clock. Ranging is then performed to determine the sample delay required to align at the central unit receiver the symbols transmitted by the remote with those transmitted by remote units already operating. Upon completing the synchronization procedure, the remote unit transmits a signal to train the central unit receiver so that the available upstream bandwidth can be used as efficiently as possible during steady-state operation.

System for memory unit receiving pseudo-random delay signal operative to access memory after delay and additional delay signal extending from termination of memory access

Abstract: This invention discloses a microprocessor device comprising an execution unit which is governed by a master clock signal and a repeatedly programmable master clock divider which is operative to divide the master clock signal. The microprocessor device is operative to execute instructions executed by an existing microprocessor, wherein said instructions being executed in a given number of machine cycles. Furthermore, the microprocessor includes a programmable instruction mapper containing a multiplicity of mapping schemes for controlling the microprocessor apparatus. A tamper-resistant execution device is included operative to execute instructions arriving from an instruction register. The microprocessor device also includes a pseudo-random access delay signal generator which generates a signal for determining the number of clock cycles elapsing from a memory access instruction cycle to actual memory access. Additionally, a method is also included for testing the contents and integrity of a condition signal within a single machine cycle.

Digital modulated clock circuit for reducing EMI spectral density

Abstract: A method and circuit spreads the narrow band emitted EMI of a clock signal. A first, high frequency, clock signal is received, for example, from an oscillator. The first clock signal is modulated, to produce a second clock signal, by inverting the first clock signal x times per L transitions of the first clock signal, where x and L are integers and x

Accurate alignment of clocks in mixed-signal tester

Abstract: Asynchronously-generated digital and analog clocks in a mixed-signal test system are accurately aligned for repeatable and deterministic testing. A variable-frequency digital master clock signal is used in direct digital synthesis of an analog clock signal which is asynchronous to the master clock signal. A resync command inhibits the analog clock signal until the analog clock signal is in a desired phase relationship to the master clock signal. The analog clock signal is thus phase-aligned with the master clock signal in a known and deterministic relationship. The resync command also aligns the phase of the analog clock signal with the pattern of stimulus signals applied to the device under test. Aligning the analog clock signal with the master clock signal and with the stimulus pattern assures that test results are consistent from test-to-test. A phase-locked loop removes spurs from the synthesized analog clock signal. A jitter generator is provided for controlled jittering of the analog clock signal as needed for some types of test. An Nth occurrence counter allows for programmable introduction of an extra master-clock-signal period in the test pattern when needed to avoid creating a metastable condition in the device under test.

Clock controller design in SuperSPARC II microprocessor

Abstract: This paper describes the SuperSPARC II clock controller. This controller allows the internal clock to be disabled during the chip's normal operation. Then any number of internal clock pulses can be issued in a controlled fashion. The clock can return to the free running mode after being disabled. All clock control is done in a way that produces no glitches on the internal clock signal The clock controller can be accessed through the IEEE 1149.1 interface, making it useful at the chip level and at the module or system level.

Unison, canon, and sluggish clocks in networks controlled by a synchronizer

Abstract: The effect of using a simple synchronizer on the performance of a directed, strongly connected, distributed network, is analysed. In this paper we assume that the time of message transmission is positive but negligible. It is shown that the synchronizer is sufficient to assure that a full rate of computation is achieved in networks with a global clock, in spite of the absence of a global start-up signal. In fact,unison is reached within linear time. A similar phenomenon occurs if there is no global clock, but all local clocks have the same rate. In case the local clocks do not have the same rate, it is shown that the computational rate is not slower than anysluggish clock; i.e., a clock such that between any two of its ticks, every local clock ticks at least once.

Method and system for automatic compensation of line delay in a clock distribution system

Abstract: The invention relates to a method and system for automatic compensation of line delay in a clock distribution system which comprises a clock signal generator (1) which supplies a master clock signal through a clock path (2) to a number of decentralized clock signal buffers (P1PN) According to the invention, the system further comprises a counter, or a similar device, which measures the propagation time of a measuring signal from the corresponding clock signal buffer to the end (B) of the line (3) and back

Hierarchical clocking system using adaptive feedback

Abstract: A clocking system for complex electronic devices is created in an hierarchial manner whereby the master clock pulse is provided to a plurality of digital pulse aligners which in turn provide phase aligned clock signals at the field replaceable unit level to either a slave clock or a digital phase aligner. The slave clock or the digital phase aligner at the field replaceable unit level in turn provides an aligned clock pulse to a timing node on respective chips. A third level of the hierarchy provides similarly aligned pulses to individual using-circuits on the chips of the system. The digital phase aligner, aligning the output pulse at the timing node of the next level with the reference pulses being provided to the digital phase aligner at each level, insures that the timing pulses arriving at the utilizing circuits are synchronously aligned with clock pulses of the master clock. The system provides dramatic simplification of replacement of either field replaceable units or individual components within field replaceable units. The system is self-phasing and self-correcting to accommodate timing misalignments caused by any variations in the timing delays at all levels, thereby reducing the jitter that must be accommodated.

Timing generator with multiple coherent synchronized clocks

Abstract: Automatic test equipment with programmable timing generators to generate digital signals and analog signals The digital timing generator can be programmed to generate timing signals with a resolution finer than that of the master clock of the timing generator Extremely fine resolution is achieved by specifying the numerator and denominator of a fractional portion of a period A similar arrangement is used to allow fine frequency resolution for the analog timing generator The fine resolution achievable with the timing generators allows the digital timing generator to be synchronized to the analog timing generator

Method and apparatus for generating and synchronizing a plurality of digital signals

Abstract: A hardware interface generates and synchronizes precisely timed digital signals. The hardware interface receives data bits and associated timing information for application to a Hardware Modeling Element (HME). Preferably there are at least two modules, each including a clock generating circuit which has an input for receiving a master clock signal, a divider circuit for generating therefrom a plurality of evenly timed internal clock signals, wherein a first one of the internal clock signals rises at the same time as the master clock signal, and a phase adjusting circuit for receiving a feedback control signal for adjusting a phase delay in accordance with a sensed throughput delay. Each module also includes a timing multiplexer which receives the internal clock signals and each having a plurality of data channels, each having approximately the same throughput delay. Each data channel also has an input for receiving a data bit, a controller for receiving the timing information which allows selection of the one internal clock signal which most closely matches the timing information, and an output port coupled to the HME. The timing multiplexer also has a dummy channel from which the sensed delay is determined. The sensed delay approximates the throughput delay. The dummy channel receives the first one of the internal clock signals and provides the feedback control signal. Finally, the hardware interface apparatus includes a timing adjustment control circuit for selectively delaying the output signal in one timing multiplexer to compensate for a slower throughput delay in another multiplexer.

Boosting voltage circuit used in active cycle of a semiconductor memory device

Abstract: A voltage boosting circuit for a semiconductor memory device has a clock generator for supplying a chip master clock determining an active state and a stand-by state in respective response to first and second states thereof, for generating a detector control signal a first delay time after the first state of the chip master clock is generated, and for generating a latch control signal a second delay time after the first state of the chip master clock is generated. A boosting voltage detector responds to the detector control signal and the latch control signal to generate a detecting signal indicative of a current state of a boosting voltage potential. First and second boosting voltage generators generate the boosting voltage potential, respectively operating in the stand-by state and active state in accordance with the detecting signal and delayed chip master clock signal.

Digital PLL circuit

Abstract: A phase control circuit (1) adjusts the width of a PLL clock signal so that a PLL clock signal generated from a master clock signal MCK is in synchronization with an EFM signal. A velocity detector (2, 3) detects offset in velocity by counting a pulse width of an EFM signal with a master clock signal MCK. The phase control circuit (1) alters the pulse width of a PLL clock signal according to the detected offset in velocity to alter the average frequency of a PLL clock signal in proportion to offset of the rotational speed.

Method for compensating time in transmitting unit and transmitting system

Abstract: A CPUA with a master clock sends a communication time count command to a CPUB whose time is to be compensated. In addition, the CPUA starts a timer. When the CPUA receives a reply to the communication time count command from the CPUB, the CPUA subtracts a predetermined time t that is from when the CPUB receives the communication count command until it sends a reply thereto from a count time T of the timer, so as to calculate the actual communication time between the CPUs. The CPUA notifies the CPUB whose time is to be compensated of the inter-CPU communication time and the time information counted according to the master clock. The CPUB compensates the time information counted by its internal clock according to the inter-CPU communication time and the time information received from the CPUA.

Ultra high availability clock chip

Abstract: A single reliable clock source that can be shared by all cards in a multiple card assembly. The clock delivers synchronous clock signals, so that there is no longer a need to provide crystal oscillators on each card, instead, a single non-interruptable clock source is shared by all cards. The clock is an Application Specific Integrated Circuit (ASIC), where single sources of failure have been removed by using redundant connection and majority logic. Thus, a plurality of selection means are redundantly coupled to receivers for selecting an oscillator signal to provide to phase-locked oscillators. Further, majority logic voters are redundantly coupled to the phase-locked oscillator to provide a clock output signal reflecting the state of the majority of the phase-locked oscillator signals. The clock includes three independent crystal oscillators, one clock ASIC, the wire and connectors which deliver the signals, and a 2×3 AND-OR majority logic on the receiving card. Each customer of the clock ASIC receives three signals from the clock ASIC and votes the three signals to create a local clock. Thus, failures at individual points do not prevent the delivery of the clock signal.

All-MOS precision differential delay line with delay a programmable fraction of a master clock period

Abstract: A write precompensation circuit includes a plurality of current-controlled delay buffers connected to form a delay line having selectable output taps. The precise delay of each delay buffer is controllable by a secondary control current derived from a master control current such that the precise delay is a precise percent of an oscillator period. The master control current is also used to control the period of a master write clock generated by a current-controlled ring oscillator of delay buffers. A write precompensation method includes steps of controlling current in delay buffers in a current-controlled ring oscillator used to generate a master write clock and current in delay buffers in a current-controlled delay line to maintain delays through delay buffers of the oscillator and the delay line in predetermined proportions to each other.

Clock distributing logic and clock skew control design method for designing clock distributing logic

Abstract: A clock distributing logic for distributing a clock signal in a circuit and reducing clock skew which occurs during the distributing of the clock signal in the circuit and a method for designing the same. The clock distributing logic includes at least two stages of clock amplifying gates for distributing the clock signal to source and sink sides of the circuit. Each of the at least two stages are successively connected to each other. Further, each of the at least two stages except a last stage includes clock amplifying gates of a same size providing a same driving ability. The last stage of clock amplifying gates includes clock amplifying gates of different sizes providing different driving abilities. The size of each clock amplifying gate of the last stage of clock amplifying gates is set to make the delay in distributing the clock signal in the circuit coincide with a desired clock signal distributing cycle.

Disc reproducing apparatus

Abstract: In a reproducing apparatus for an optical disc recorded at a constant linear velocity (CLV), so as to increase the reproducing access speed, a first clock generator for generating a reproducing clock corresponding to the transmission rate of a digital information signal, an oscillator for oscillating at a fixed frequency, a second clock generator for generating a master clock which is a reference of operations of a first controller for controlling the linear velocity, a digital signal processor, and a second controller for controlling the storage from the clock generated by the oscillator, a third clock generator for generating a master clock which is a reference of operations of the digital signal processor and the second controller without using the oscillator, and a switch for switching the master clock which is a reference of operations of the digital signal processor and the second controller to one of the clock by the second clock generator and the clock by the third clock generator are provided.

Frequency divider circuit

Abstract: PURPOSE:To provide an odd number frequency divider circuit simple in circuit configuration, easy to change a frequency division ratio and capable of obtaining the output of duty factor of 50%. CONSTITUTION:A master clock noninverting signal is given to each clock input CIN of odd number stages of flip-flops 11 of 2N-sets each in which data output Q of a pre-stage are given to a data input D of a post-stage and a data inverting output QB at a final stage is given to a data input D of a 1st stage and a master clock inverting signal is given to even number stages of flip-flops to form N-stages of Jhonson counters. Each data output of an N-th stage flip- flop and a 2N-th stage of flip-flop is given to an AND gate 13 and each data inverting output is given to an AND gate 14, in which data are ANDed. When the ANDed data are given to an OR gate 15, an output signal whose duty factor is 50% resulting from applying 1/N frequency division to a master clock is obtained.