Showing papers on "Master clock published in 1997"

Method and computer program product for synchronizing the processing of multiple data streams and matching disparate processing rates using a standardized clock mechanism

Abstract: A method and computer program product for synchronizing processing between two or more data streams (e.g., video and sound input) and for rate matching between two different hardware clocks that may drift with respect to one another (e.g., an originating clock represented in a timestamped data stream versus a clock actually rendering the data) in a system of interconnected software drivers running in kernel mode. The present invention overcomes the coordination complexity and inaccuracies in the prior art by providing a clocking mechanism in a system wherein multiple drivers having input and output connection pin instances are chained together. The clocking mechanism synchronizes between data streams by providing a master clock on an input pin instance of a driver that is used to synchronize with other input pin instances on other drivers and "slave" clocks. Synchronization is achieved through event notification or stream position queries so that corresponding frames of data in separate streams are rendered together (e.g., video frames with corresponding sound track). Rate matching is achieved through monitoring a physical clock progression in comparison with a series of data stream timestamps thereby allowing adjustments to match the different clock rates. A common physical clock (e.g., PC clock) can be used as a reference for a component to translate a particular clock time to a time shared by all components with a minimum of error.

Methods and apparatus for synchronization in a wireless network

Abstract: As part of a preferred communication protocol, base stations (12) which are synchronized to a PSTN (20) of a wireless communication network (10), periodically transmit a preamble. A remote detects the preamble and, upon verification of the data contained in the base station transmission, sets its counter to an initialized state based on the received preamble. An early/late analysis of each subsequently received base station timing pulse is used to adjust both the mobile station timing and to adjust the output frequency of the mobile station master clock and codec clock to effectively maintain end to end synchronization with the respective base station and the PSTN throughout the duration of an established communication link.

Broadband switch that manages traffic and method therefor

Abstract: A network ( 10 ) includes a broadband customer service module (B-CSM) ( 20 ). The B-CSM ( 20 ) includes a plurality of feeder interface cards (FICs) ( 36 ) and optical line cards (OLCs) ( 38 ) which are coupled together through a midplane assembly ( 34 ) so that each FIC ( 36 ) couples to all OLCs ( 38 ) and each OLC ( 38 ) couples to all FICs ( 36 ) through junctor groups ( 68 ). A reference clock which oscillates at a frequency slower than the data rate is routed with payload data so that it receives delays similar to those imposed on the payload data due to processing. At second stage switching fabrics ( 50 ) where data need to be extracted from signals flowing within the B-CSM ( 20 ), a clock regeneration circuit ( 32 ) generates a master clock signal oscillating at twice the data rate and phase synchronized to a delayed reference clock. A geometric compensation scheme corrects for timing skew which occurs when clocks and data are distributed to points or small areas from widely dispersed locations, and when clocks and data are distributed from points or small areas to widely dispersed locations. The B-CSM ( 20 ) ranks the junctor groups ( 68 ) according to signal occupancy and manages signal traffic to efficiently utilize the FICs ( 36 ) and to reduce the probability of signal blocking. The junctor groups ( 68 ) can include a number of bidirectional junctors. The bidirectional junctors are configured to carry upstream or downstream signals according to current upstream and downstream signal traffic volume.

System and method for adjusting time associated with medical event data

Abstract: A system synchronizes the time of a clock of an electronic physiological instrument with time of a remote time base. The electronic physiological instrument records medical event data and electronically associates event time with the event data While recording, or after recording, the medical event data, the electronic physiological instrument is placed in data communication with the remote time base over a data connection. The remote time base initially determines a reference time from a master clock. The remote time base also transmits a request to the electronic physiological instrument for a current time from a clock in the electronic physiological instrument. If a response is not received from the electronic physiological instrument within a first time period, the clock is not synchronized with the remote time base. If a response is received within the first time period, a time difference is determined between the reference time and the time transmitted from the electronic physiological instrument by subtracting the two times. The time difference is then electronically associated with the medical event data. Associating the time difference with the medical event data allows the time stamps in the event data to be corrected to provide meaningful event reconstruction and analysis independent of any time differences between the two clocks and any time delays incurred in receiving the time from the physiological instrument over the data connection.

Distributed clocking system

Abstract: A clocking mechanism with improved fault tolerance for synchronizing a distributed processing system includes a plurality of distributed clock sources. Each clock source may operate as a master clock for synchronizing the operations of the entire system or as a slave to an external clock while remaining available, in a backup capacity, to operate as a master clock in the event of a failure in the previous master clock. A clock selection mechanism is provided in each distributed switch element for selecting the best clock available to each switch element for synchronization. A failure recovery mechanism is provided with fast and automatic recovery in the event of a failure in a master clock. A data extraction mechanism is also provided capable of sampling a bit stream that is not phase-aligned, even in the presence of timing jitter and pulse width distortion, and having provisions for detecting a bit slip.

Broadband video switch that performs program merging and method therefor

Abstract: A network ( 10 ) includes a broadband customer service module (B-CSM) ( 20 ). The B-CSM ( 20 ) includes a plurality of feeder interface cards (FICs) ( 36 ) and optical line cards (OLCs) ( 38 ) which are coupled together through a midplane assembly ( 34 ) so that each FIC ( 36 ) couples to all OLCs ( 38 ) and each OLC ( 38 ) couples to all FICs ( 36 ) through junctor groups ( 68 ). Within the B-CSM ( 20 ) circuit switching is performed electrically at an STS-1 rate. A reference clock which oscillates at a frequency slower than the data rate is routed with payload data so that it receives delays similar to those imposed on the payload data due to processing. At second stage switching fabrics ( 50 ) where data need to be extracted from signals flowing within the B-CSM ( 20 ), a clock regeneration circuit ( 32 ) generates a master clock signal oscillating at twice the data rate and phase synchronized to a delayed reference clock. A geometric compensation scheme corrects for timing skew which occurs when clocks and data are distributed to points or small areas from widely dispersed locations, and when clocks and data are distributed from points or small areas to widely dispersed locations. A variation of the Q.931 signaling protocol is implemented to enable the B-CSM ( 20 ) to respond to a request from a second subscriber interface unit (SIU) ( 100 ) to view a video program currently being delivered to a first SIU ( 100 ). The second SIU ( 100 ) need not have access to the identity of the video program before sending the switching request.

Possible and Impossible Self-Stabilizing Digital ClockSynchronization in General Graphs

Abstract: We study digital clock synchronization for multiprocessor systems, where processors are triggered by a common clock pulse and communicate with others via shared memory. A self-stabilizing digital clock synchronization protocol for systems with a general communication graph is presented. The protocol can commence in an arbitrary non-consistent system state and converges to a legitimate state in which the clocks are synchronized and incremented by one in every subsequent pulse. To enhance the fault-tolerance of our protocol, we allow that during and following convergence processors may stop operating. Crash failures may partition the communication graph into several connected components. Our protocol synchronizes the clocks of the processors in every such connected component. For the case in which faulty processors can exhibit Byzantine behavior, we prove that there is no digital clock synchronization protocol that tolerates even one single faulty processor.

System for providing accurately time stamped vehicle operational messages following a real-time clock reset

Abstract: A system for providing accurately time stamped vehicle operational messages following a real-time clock reset includes a vehicle control computer having a processor, a memory and a real-time clock powered by a constant power source. The processor is operable to store a current value of the real-time clock in memory at engine shut down and to determine whether a clock reset event occurred since the previous engine operational cycle by testing a clock error flag in memory. If such a clock reset event occurred, the processor is operable to reset the real-time clock at the clock value stored at engine shut down and store this value in an error buffer of the memory. Upon establishment of communications with a time correction device having a master real-time clock, the processor is operable to determine whether the error buffer contains any clock values therein. If so, the processor is operable to correct the time stamps of all vehicle operational messages having time stamp values later than or equal to the clock value stored in the error buffer in accordance with the difference between the master clock value and the present value of the real-time clock, and to reset the real-time clock value to the master clock value.

Memory system with dynamic timing correction

Abstract: A memory system includes a memory controller and a bank of memory devices. The memory controller controls the memory devices through packets of control data and a master clock signal. Each of the memory devices includes an adjustable output timing vernier that can be adjusted in response to commands from the memory controller. The vernier output controls timing of output data relative to the master clock signal. As each memory device transmits data to the memory controller, the memory device also transmits an echo clock signal coincident with the data. The memory controller receives the echo clock signal and compares the echo clock signal to the master clock signal to identify shifts in timing of the echo clock signal. If the echo clock signal shifts by more than one vernier increment from the master clock signal, the master controller issues a command to the memory device to adjust the output vernier to correct the timing drift of the echo clock signal. By correcting the timing drift of the echo clock signal, the memory controller also corrects timing drift of the output data, thereby assuring that the data arrive at the memory controller coincident with edges of the master clock signal.

GPS-based Clock Synchronization in a Mobile, Distributed Real-Time System

Abstract: In a vehicle tracking system computers aboard moving vehicles determine periodically their geographical position and transmit it to a control center. This paper presents a commercial vehicle tracking system as an example of a distributed real-time system with mobile components and focuses on the issue of clock synchronization. The mobile components of the system obtain highly accurate timing information from the Global Positioning System which is used to synchronize their local clocks to UTC world time. Thus a tight clock synchronization is achieved without imposing additional load on the communication channels of the system.

Method and apparatus for synchronizing clocks coupled to network

Abstract: Many devices (in particular white goods or brown goods) in a household may contain a clock. Some systems allow connection of such devices and their related clocks to a common bus or network. The commands for controlling the clocks are in general limited to reading or writing a given time or to broadcasting the time of a given clock to one dedicated device or to the entire system or to a part of the system. In such known systems it is not specified in which manner a clock should react if it receives the time broadcast by another clock. It is possible to initialize all clocks to a given time, but due to tolerances in the different clocks, so achieved synchronization will not be maintained. Regular broadcasting by a special device master clock has the disadvantage of introducing one device with different capabilities. In case there are several master clocks, conflicts may occur and the advantages of a high precision clock will fade away if a lower precision master clock overrides it. In the present invention, only the clock with the highest precision broadcasts its time to the system, but whenever it fails the next lower precision clock takes over the broadcasting automatically. The broadcast periods are defined as factorial periods of a preselected time period. In an alternate embodiment, all devices broadcast the time with an equal period but with a different phase, and only if no broadcast was received in the preceding time period.

Digital-to-analog converter with power up/down transient suppression and automatic rate switching

Abstract: Power-up and power-down transient suppression are provided for an audio digital-to-analog converter with a single ended output to prevent annoying pops which accompany switching an audio system on and off. Power-up suppression is achieved by clamping an output signal to ground, driving the audio channel to ground, releasing the clamp and driving the audio channel gradually to its quiescent (zero signal) value. Power-down suppression is provided by using a positive feedback amplifier to accelerate current drain initiated by a constant current source used to bleed off the charge on output capacitor. The audio digital-to-analog converter sets operational mode based on ratios of a master clock to a channel selection clock.

System and method to control microprocessor startup to reduce power supply bulk capacitance needs

Abstract: A system for controlling a clock rate of a microprocessor which includes a core clock operatively coupled to the processor, the core clock providing the microprocessor with a core clock signal for clocking the processor. A power supply operatively coupled to the microprocessor provides power to the processor. An intelligent clock generating system provides the core clock with at least one clock signal of a plurality of clock signals to be used as the core clock signal, wherein the plurality of clock signals includes a master clock signal and at least one ramped clock signal.

Multi-channel architecture with channel independent clock signals

Abstract: Described is a multi-channel architecture (10) comprising a central master clock generator (40) for generating a central master clock signal (200) and a plurality of channels (20aa..20zz) connectable with inputs or outputs of a device (70). The multi-channel architecture (10) further comprises a channel master clock gate (150aa) assigned to a respective channel (20aa) of the plurality of channels (20aa..20zz), for receiving the central master clock signal (200) and for generating a channel clock signal (210aa) from the central master clock signal (200). The multi-channel architecture (10) can be used in a tester arrangement, and preferably in an IC tester. The described multi-channel architecture (10) allows to provide clock signals for each one of the channels independent of other channels, e.g. to apply a continuous clock signal in one channel while the clock signal in other channels might be changed, e.g. in order to receive new timing edges as references for testing a DUT.

Integrated circuit device with improved clock signal control

Abstract: A remote clock signal generation means is provided which allows a plurality of clock signals to be generated remotely at the "leaf" level thereby removing the need to have multiple clock signals at the system, or "tree" level. More particularly, this system is designed for use in an LBIST circuit featuring LSSD master-slave clock control. This disclosure teaches a clock control method and structure in which the master and slave clocks are generated directly from the system clock after the clock powering logic to thereby avoid intrusion or modification effects associated with logical manipulation of the clock signals.

Method and system for resynchronizing a phase-shifted received data stream with a master clock

Abstract: A method and system in a data processing system for resynchronizing a received data stream (58) with a master clock (72) having a master clock frequency, wherein the received data stream (58) is clocked with a received data clock (56) that is out of phase with the master clock (72) by an arbitrary number of degrees The master clock (72) and the received data clock (56) are compared (120, 204) at a frequency of a resynchronization clock for a predetermined number of times to produce comparison results (208) The resynchronization clock frequency may be less than the frequency of the master clock The comparison results are analyzed to produce a relative phase indicator (134) In response to the relative phase indicator exceeding, or being less than, a phase shift threshold (136, 210), the received data stream is reclocked (144) at a rising (212) or falling edge (214) of the master clock (72) to produce a resynchronized data stream (88), wherein the resynchronized data stream (88) is synchronized with the master clock (72) and contains the data of the received data stream (58)

Recovering a clock signal in a multimedia network using time stamps

Abstract: An apparatus and method allow two or more members of a network, connected in multipoint-multipoint manner, to synchronize their local service clocks. Overall synchronization is achieved as soon as every member within the network transports its own timing information to other members of the group, plus the maximum propagation delay between the group members, and accordingly minimizes the possibility of overruns and underruns at each node end. Such synchronization is implemented when all members of a network synchronize their internal clocks to a lowest clock frequency within the network.

Digital phase correcting apparatus

Abstract: The present invention relates to a digital phase correcting apparatus, including a phase comparator (100), a loop filter (110), and a digital controlled oscillator (120). The digital controlled oscillator (120) includes a phase clock signal generator (400), a multiplexer (410), an up/down counter (430), and a frequency divider (420). The phase clock signal generator (400) receives the master clock signal as an input and generates therefrom a plurality of clock signals having a phase difference of half a period of the master clock signal. The multiplexer (410) selects and outputs one of the clock signals generated in the phase clock signal generator (400). The up/down counter (430) receiving a phase lead/lag signal of the loop filter (110) and provides an output select signal for the multiplexer (410). The frequency divider divides the frequency of the clock signal output from the multiplexer and outputting the phase locked clock signal to the phase comparator. According to the present invention, it is possible to improve the degree of precision and the jitter characteristics of the PLL by a factor of two since the phase locked clock signal can be changed by a unit of a half period of the master clock signal.

Wait-free clock synchronization

Abstract: Multiprocessor computer systems are becoming increasingly important as vehicles for solving computationally expensive problems. Synchronization among the processors is achieved with a variety of clock configurations. A new notion of fault-tolerance for clock synchronization algorithms is defined, tailored to the requirements and failure patterns of shared memory multiprocessors. Algorithms in this class can tolerate any number of napping processors, where a napping processor can fail by repeatedly ceasing operation for an arbitrary time interval and then resume operation without necessarily recognizing that a fault has occurred. These algorithms guarantee that, for some fixed k, once a processor P has been working correctly for at least k time, then as long as P continues to work correctly, (1) P does not adjust its clock, and (2) P's clock agrees with the clock of every other processor that has also been working correctly for at least k time. Because a working processor must synchronize in a fixed amount of time regardless of the actions of the other processors, these algorithms are called wait-free. Another useful type of fault-tolerance is called self-stabilization: starting with an arbitrary state of the system, a self-stabilizing algorithm eventually reaches a point after which it correctly performs its task. Two wait-free clock synchronization algorithms are presented for a model with global clock pulses. The first one is self-stabilizing; the second one is not but it converges more quickly than the first one. The self-stabilizing algorithm requires each processor's communication register contents to be a part of the processor's state. This last requirement is proven necessary. A wait-free clock synchronization algorithm is also presented for a model with local clock pulses. This algorithm is not self-stabilizing.

Radio communication equipment and its method

Abstract: PROBLEM TO BE SOLVED: To prevent a cordless control channel from becoming impossible usage by means of the radiation of useless noise by previously stopping the oscillation of IC being a radiation noise source. SOLUTION: A control part stops the master clock of a picture processing part at the time of stand-by (S201). When a copy key is depressed, it is judged whether a cordless connecting device is using the control channel or not (S203) and copy usage disapproval is reported to a user at the time of under usage (S204). In the meantime, unless the control channel is under usage, the control part starts supplying electricity to the master clock of the picture processing part (S205) and stops the cordless connecting device (S206). When the cordless connecting device is used (S208) under the operation of the picture processing part (S207), it is reported to a user that copying is required to be interrupted, etc., when a cordless telephone set is used since copying is being executed. COPYRIGHT: (C)1999,JPO

Divide-by-one or divide-by-two qualified clock driver with glitch-free transitions between operating frequencies

Abstract: A method and system for a clock driver is described which can buffer an master clock directly, or generate a output clock signal having a balanced duty cycle which is the input clock frequency divided by a predetermined value. When a frequency control input, such as a rate signal, is switched, the clock output makes a glitchless transition from one frequency to the other. The clock driver includes a counter divider circuit with feedback to produce two signals related by a predetermined phase difference. The counter divider circuit employs predetermined logic delays by buffered gating controlled by the master clock, which produces two signals. These two signals act as "enable" control signals such that the timing of their rising and falling edges is arranged to never propagate through the clock divider circuit to become the edges of output clock. The master clock is gated with these two signals to provide two unbalanced signals which are synchronous to the input clock signal. In addition, these two unbalanced signals have waveforms such that they may then be logically combined to form a single, balanced signal in a glitchless manner. Furthermore, transitions between fast, slow, and disable modes of operation for such clock driver circuit are also synchronous with the master clock and glitchless.

High-resolution and broadband linear frequency-scanning signal resource

Abstract: The utility model discloses a high-resolution and broadband linear frequency-scanning signal resource which belongs to the field of digital analog circuit technology, comprising a direct digital frequency synthesizer DDS, the signal processing circuit of the direct digital frequency synthesizer DDS, a frequency scanning digital generator FPGA for field programmable gate array, a master clock phase-locked loop and a frequency mixing phase-locked loop unit. The utility model adopts novel modularized elements with high integral rate and integrally uses the circuit technologies of digital, analog circuit and high low frequency, which causes the utility model to satisfy the indicators with high performance of high resolution, wide frequency band, low phase noise linearity, etc.; the utility model has the advantages of stable and reliable performance, small size and low cost.

Synchronization message transmitting apparatus

Abstract: A synchronization message transmitting apparatus employs a synchronization message to synchronize a communication network. If an abnormality occurs in any part of the apparatus or on a clock in the apparatus, the apparatus detects the abnormality and prepares a synchronization message indicating that a frame to be transmitted must not be used for preparing a master clock. An opposite party that receives the frame with the synchronization message will not use the received frame for preparing a master clock.

Apparatus and method for operating clock sensitive devices in multiple timing domains

Abstract: In a digital signal processing system, such as a computer system, an apparatus for communicating digital signals in a plurality of operating domains. The first domain has first timing and control signals synchronized to a first clock. In response to an event, the apparatus dynamically transitions the operation of the synchronous memory to a second domain having second timing and control signals synchronized to a second clock. The first timing and control signals being different in frequency, shape, and protocol than the second timing and control signals. The first clock can be a processor clock to synchronize communication of address and data signals with a processor, and the second clock can be a system clock to synchronize communication of address and data signals with an asynchronous data processing device such as random access memory.

Clock snooping and its application in on-the-fly data race detection

Abstract: In this paper, we describe clock snooping, a novel logical clock update technique that improves the performance of classical logical clocks (scalar clocks, vector clocks, as well as matrix clocks). The basic idea of clock snooping is that logical clocks will not only get updated with information piggybacked on communication messages, but that processes can explicitly request the current value of the clock of another process, and use that information to resynchronize their own clock. The usefulness of this concept is shown in our on-the-fly race detection software.

Data transfer system and method

Abstract: The timing of digital signal sampling at a receiver is continuously adjusted relative to a master clock used to initiate sending, by controlling a phase difference between the receiver sampling clock and the master clock in accordance with feedback of an error signal determined by detecting deviation of sampling clock timing from desired reference timing during both start-up operation and normal operation. Propagation delay scattering in the individual devices is compensated for by setting the sampling clock at a desired reference timing at start-up. Propagation delay scattering caused by fluctuation during device operation is compensated for by detecting the deviation of the sampling clock timing from reference timing based on received digital signals during normal operation and then continuously correcting the sampling clock timing on the basis of the detection result.

Synchronous circuit with improved clock to data output access time

Abstract: A synchronous circuit, such as an SRAM, a DRAM or a programmable logic device, has internal circuitry, a master input latch clocked by a master clock generator, and a slave output latch clocked by a slave clock generator. The master input latch is rendered transparent prior to the start of system setup time so that information input signals can pass through the master input latch and undergo processing in the circuitry prior to the start of a system cycle. After correct and stable information output signals are generated by the internal circuitry, these signals are latched into the slave output latch as correct and stable output information. The master latch may be clocked from the latched to the transparent state before the slave latch is clocked from the transparent to the latched state, provided that the time period between these two transitions is less than the minimum processing time of the internal circuitry. By advancing the start of the internal signal processing by a time period equal to the system setup time, the system clock to data output access time is substantially shortened.

A time analyzer having an improved interpolator with temperature compensation

Abstract: A time analyzer (10) having an improved interpolator with temperature compensation. The time analyzer of the present invention can be operated in a wide range of temperatures without need of recalibration in the field. The device includes hardware for making a coarse time measurement. A fine time measurement is obtained by interpolating with a cycle of the master clock. A temperature correction look up table (54) is produced which incorporates information unique to each analyzer. Information stored in the look up table of each instrument is used to correct time measurement for enhanced precision.

Network element for use in synchronous digital communications system and central clock generator

Abstract: The network elements NE1, . . . , NE6 of a synchronous digital communications system must be synchronized with each other without the possibility of clock loops occurring. A network node NODE contains network elements NE1, . . . , NE6 and a central clock generator SASE. The network elements transmit clock signals 2M to the clock generator, which contain a clock of a message signal STM-N and a quality indicator (SSM) contained in the message signal which reflects the accuracy of the clock. The clock generator selects one of the clock signals 2M as the reference clock REF and informs the control installation STE which of the clock signals it has selected and the degree of accuracy of this clock signal. On the basis of this message STAT the control installation gives instructions ANW to the network elements with respect to the quality indicator which the network elements are to transmit to their outputs.