Showing papers on "Master clock published in 2001"

Apparatus and method for trellis encoding data for transmission in digital data transmission systems

Abstract: A system for bidirectional communication of digital data between a central unit and a remote unit wherein the need for tracking loops in the central unit has been eliminated. The central unit transmitter generates a master carrier and a master clock signal which are used to transmit downstream data to the remote units. The remote units recover the master carrier and master clock and synchronize local oscillators in each remote unit to these master carrier and master clock signals to generate reference carrier and clock signals for use by the remote unit receiver. These reference carrier and clock signals are also used by the remote unit transmitters to transmit upstream data to the central unit. The central unit receiver detects the phase difference between the reference carrier and clock signals from the remote units periodically and adjusts the phase of the master carrier and master clock signals for use by the central unit receiver to receive the upstream data.

Method of controlling data sampling clocking of asynchronous network nodes in a frame-based communications network

Abstract: A method of controlling data sampling clocking of asynchronous network nodes, each asynchronous network node having a local clock and transmitting and receiving packets to and from an asynchronous network according to an asynchronous network media access protocol. An asynchronous network node capable of transmitting and receiving packets on the asynchronous network is designated as a master node. Each non-master asynchronous network node which desires to synchronously transport packets across the asynchronous network is designated as a slave node. A master node clock of the master node is synchronized with a slave node clock of each slave node. Each slave node clock is continuously corrected compared with the master node clock to smooth slave clock error to an average of zero compared with the master clock as a reference using timestamp information from the master node. A derivative clock at the slave node is derived from the continuously correcting each slave node clock to control data sampling at the slave node.

System and method for acquiring data

Abstract: A system for acquiring, and displaying, data such as physiological data, from a plurality of data connection devices, each of which monitor one or more different parameters and output data at different sampling frequencies based on their own system clocks. The system receives the data signals at different sampling frequencies and associates each sample of each signal with a time stamp derived from a single master clock. Low rate and high rate data are treated differently. Low rate data is associated with the current value of the master clock, where as high rate data is time stamped by giving the first sample a time stamp equal to the current value of the current master clock, subsequent samples being given an estimated time stamp based on the expected interval between samples derived from the sampling frequency of the data collection device, and the timescale given to the first example. The estimated time stamp may be periodically corrected, and the estimation calculation can be improved by correcting the value used for the interval between samples. The different signals can be displayed together on a display aligned with respect to a time axis. The system can display, the data in two different timescales, one showing a few seconds of data and one showing a few hours of data. The data traces are scrolled across the time axis, new data being added to one end of the trace.

Method for clock synchronization between nodes in a packet network

Abstract: A method and system for synchronizing clocks in a packet network that includes a master node and at least one slave node that communicate with one another is disclosed. A timer value from a master clock is retrieved upon transmission of a first packet to the slave node. The timer value and an associated code are subsequently sent to the slave node in a subsequent packet. After receiving the first packet, the slave node, retrieves a timer value from a slave clock and associates it with an identifying code of the first packet. After receiving the subsequent packet, the slave node relates the timer values and adjusts a clock value of the slave clock accordingly. An interrupt scheme may be used to implement the retrieval of the timer values.

System and methods for generating trusted and authenticatable time stamps for electronic documents

Abstract: A trusted time infrastructure system provides time stamps for electronic documents from a local source. The system comprises a trusted master clock (204), a trusted local clock (206), and a network operations center (210). The trusted master clock and network operations center are located within secure environments controlled by a trusted third party. The trusted local clock may be located in an insecure environment. The trusted master clock is certified to be synchronized with an accepted time standard, such as a national time server (202). The trusted local clock, which issues time stamps, is certified to be synchronized with the trusted master clock. Time stamps and certifications are signed by the issuing device using public key cryptography to enable subsequent authentication. The network operations center logs clock certifications and responds to requests for authentication of time stamps.

Method of providing synchronous transport of packets between asynchronous network nodes in a frame-based communications network

Abstract: A method of providing synchronous transport of packets between asynchronous network nodes. An asynchronous network node capable of transmitting and receiving packetson the asynchronous network is designated as a master node. Each non-master asynchronous network node which desires to synchronously transport packets across the asynchronous network is designated as a slave node. Best arrival times for packets transmitted from slave nodes to the master node are communicated from the master node to the slave nodes. Bestpacket assembly times for packets to be transmitted by the particular slave node to the master node in the future for the packets to be received by the master node at future master clock referenced best arrival times are determined. Packets for transmission at slave nodes are prepared and transmitted according to determined future bestpacket assembly time information.

Clock generation systems and methods

Abstract: A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; a wireless transceiver transmitting and receiving at a frequency based on a wireless clock input; and a controller having a plurality of clock outputs each coupled to the clock inputs of the processing units and the wireless clock input, the clock outputs being generated from a common master clock.

Distributed system time synchronization including a timing signal path

Abstract: A distributed system with a timing signal path for increased precision in time synchronization among distributed system clocks. A distributed system according to the present teachings includes a master clock coupled to a timing signal path and a set of slave clocks coupled to the timing signal path. The master clock includes means for generating a timing signal on the timing signal path in response to time events associated with the master clock. The slave clocks include means for adjusting their local time in response to the timing signal received via the timing signal path.

Method and apparatus for crossing clock domain boundaries

Abstract: A method and apparatus that expands the data envelope of captured data to a predetermined number of clocks cycles. The predetermined number of clock cycles is large enough to ensure that an internally generated master clock edge remains within the data envelope over the entire operating range. This way, captured data remains valid and can be properly transferred to the master clock domain from a capture clock domain despite temperature and voltage variations that may effect the timing of the memory device.

Regeneration of program clock reference data for mpeg transport streams

Abstract: A system for providing an accurate time reference for multiple input and output digital video signals of a transcoder (100) that is particularly suited for use with MPEG data. The multiple streams are synchronized with a single master system time clock (155) at the transcoder (100). Timing data from the master clock is compared to timing data from packets that are input to the transcoder to determine an offset (120, 130). In particular, timing data, such as a program clock reference (PCR) field, is recovered from packets (104) of different channels that are input to the transcoder (122, 132). For each channel, timing data is then provided for packets (106) that are output from the transcoder based on the offset and timing data of the master clock (155) at the respective output times. In particular, the adjusted timing data is determined as a sum of the offset and an associated hardware error, less a delay (PcrSysDla) associated with the transcoder, which includes a lookahead delay and a buffer delay. The associated hardware error represents an error of the master clock and/or a system time clock of an encoder that encoded the particular channel.

Apparatus, method and system for synchronizing slave system operations to master system clocking signals in a master-slave asynchronous communication system

Abstract: A method for synchronizing a slave system and a master system, the method including the steps of providing a slave clock signal based on a communicated master clock signal, providing a time frame in the slave system, wherein the time frame is defined by a minimum time and a maximum time, and a phase of the slave clock signal corresponds to an actual time, determining if the slave clock signal is in the time frame, and regulating the slave clock signal, if it is not in the time frame, so that the slave clock signal occurs within the time frame.

An apparatus system and method for synchronizing a clock with a master time service

Abstract: A clock (12) is provided for synchronizing with a master time service (16). The clock (12) includes a microprocessor (18) configured to obtain time code data from the master time service (16), process the time code data, and initiate a time keeping function. The clock (12) further includes a time indicator (24) connected to the microprocessor (18). The time indicator (24) displays a time corresponding to the time code data.

Two-conductor bidirectional digital seismic telemetry interface

Abstract: A two-conductor bidirectional digital telemetry interface between a seismic sensor acquisition/conversion module (40) and a seismic data collection module (20). The data collection module is configured as a master electronics device and the sensor acquisition/conversion module is configured as a slave electronics device in the telemetry system. The master device provides power to the slave device over the two conductors (36). The master device transmits portions of a digital seismic data packet to the master at a different second time in a fixed-duration frame. The frames are transmitted at regular intervals. The outbound commands and inbound data are encoded by block codes. A phase-locked loop (54) in the slave is locked to a master clock (35) in the master by deriving a clock and a sync point from the block-coded commands it receives from the master. The block code representing each command bit minimizes dc drift and provides a level transition in the command that can be used to maintain synchronism between master and slave.

Apparatus and method for receiving upstream data transmissions from multiple remote transmitters

Abstract: A system for bidirectional communication of digital data between a central unit and a remote unit wherein the need for tracking loops in the central unit has been eliminated. The central unit transmitter generates a master carrier and a master clock signal which are used to transmit downstream data to the remote units. The remote units recover the master carrier and master clock and synchronize local oscillators in each remote unit to these master carrier and master clock signals to generate reference carrier and clock signals for use by the remote unit receiver. These reference carrier and clock signals are also used by the remote unit transmitters to transmit upstream data to the central unit. The central unit receiver detects the phase difference between the reference carrier and clock signals from the remote units periodically and adjusts the phase of the master carrier and master clock signals for use by the central unit receiver to receive the upstream data.

Chronobiology--Reducing Time

Abstract: The physiology and behavior of mammals are subject to daily oscillations. These oscillations are driven by a master clock in the suprachiasmatic nucleus (SCN) of the brain9s hypothalamus and by clocks in most other cell types that contain many of the same protein components. But what regulates the activity of these clocks? The answer, according to Schibler et al., reporting in their Perspective on new work from McKnight9sgroup, may lie in cellular metabolism. It turns out that two crucial clock proteins (transcription factors that switch on target genes involved in circadian oscillations) are regulated in vitro by the ratio between reduced and oxidized forms of the respiratory chain electron carrier NAD that fluctuate according to the metabolic state of the cell.

Method for synchronizing generation and consumption of isochronous data

Abstract: A method of synchronizing the generation and consumption of isochronous data in a computer system. In one embodiment, a computer system implements a method comprising providing a plurality of clocks to a plurality of isochronous sinks or sources configured to generate or consume the isochronous data, outputting a master clock signal to the plurality of isochronous sinks or sources, synchronizing said clocks to said master clock signal so that the generation or consumption of the isochronous data is synchronized to said master clock signal, outputting said master clock signal to an interrupt controller, and generating an interrupt based on said master clock signal, wherein a processor schedules one or more tasks that generate or consume data based on said interrupt. The isochronous sinks or sources may also be synched to a multiple of the master clock signal.

Method and interface for glitch-free clock switching

Abstract: A clock switching technique allows selecting an input clock signal from two clock sources. The two clock sources are asynchronous to one another and a clock select signal is used to determine which of the clocks will be switched onto the clock output line. The clock select signal is asynchronous to both clock sources and can be either from a programmable bit implemented under software control or as a single signal generated from some other logic block. The technique guarantees that the switching to the desired clock based on the binary value of the clock select signal onto the clock line is glitch-free. The clock switching technique is independent of the two clock source frequencies as well as the system clock frequency.

Technique for removal of picket fence effect in PET imaging systems

Abstract: A method and apparatus for eliminating the picket fence effect in PET scanners where the scanner includes a master clock and an event processing circuit that generates time stamps during each clock cycle, the scanner also including a coincidence detector that compares the time stamps during each clock cycle to identify coincidence events, the method including the steps of, for consecutive master clock cycles, identifying an overlap period that includes a portion of a first of the master cycles adjacent a second of the master cycles, adding an overlap period that occurs during the overlap period to the second of the master cycles to generate an extended cycle, identifying overlap events that occur during the overlap period in the first of the master cycles, copying the overlap events to the overlap period in the extended second cycle and performing a comparison of the events in the extended cycle to identify coincidence event pairs

Digital-data receiver synchronization method and apparatus

Abstract: An improved digital-data receiver synchronization apparatus and method is provided wherein memory devices in the receiver such as phase-lock loops are provided with composite phase-frequency detectors, mutually cross-connected comparison feedback means, or both, to provide robust reception of digital data signals. The apparatus and method are preferably utilized with synchronous architecture wherein a single master clock is used to provide frequency signals to the memory devices, and also can be used with asynchronous architecture. The apparatus and method provide fast lock-up times in moderately to severely noisy conditions and have improved tolerances to clock asymmetries.

Bit interleaved data serial interface

Abstract: A shared wire serial interface between two devices that share a system clock and a single bi-directional serial data line. The clock drives both the system and the interface and is provided over a single clock wire. One device operates as a master, the other as a slave. Since master and slave share the same clock, clock drift error will be zero. Although the start of a data transfer is asynchronous with regard to the system clock, the data transfer itself, is synchronous. In one embodiment, the bit transfer rate is ⅛ th the system clock speed in one example and is generated by a state machine, however, any divide may be used. The state machine also signals the output enablers which interleave the data bits on the serial data line. The flow of data on a single data line of the interface is bi-directional in that data from the master is bit interleaved with data from the slave. Due to the bit interleaving of data between master and slave, the master can simultaneously shift a command out of its register while shifting in a reply from a previous command. A one bit tri-state period separates each data bit.

System and method for synchronizing a base station in a distributed radio system

Abstract: There is disclosed a system and method for synchronizing a base station within a distributed radio system. A communication network is provided utilizing gigabit ethernet protocols and media. A global positioning system (GPS) is installed onboard one of a plurality of base stations. The single GPS, without the necessity for a holdover oscillator, is used to synchronize a plurality of the base stations within the network by transmitting a clock signal via the gigabit ethernet media to each base station. The gigabit Ethernet signal is tapped by a clock recovery circuit, present on each base station and the recovered signal serves as a master clock signal for the base station as well as a reference clock for the transmit and receive section.

Base station transceiver to radio network controller synchronization filtering function

Abstract: A method that initiates several time synchronization passes between clock slave components and a clock master component in a wireless telecommunications system is provided. For every pass, each clock slave component generates and transmits a first timing cell to the clock master. The first timing cell contains a transmission time based on the clock slave component's clock. Upon receipt of the first timing cell, the clock master generates and transmits to the clock slave component a second timing cell containing the time the clock master received the first timing cell and the time the master transmitted the second timing cell. Upon receipt of the second timing cell, the clock slave component will obtain its reception time and calculate a transmission delay based on the reception time and the timing information contained in the timing cells. Each clock slave component utilizes a filtering function to drop information from a synchronization pass that may have undesirable data due to processing and other delays. The filtering function will also restart the synchronization process whenever a calculated transmission delay is smaller than the best delay. This allows the process to accurately hone in on the proper delay experienced between each clock slave component and the clock master. After timing information from a predetermined number of time synchronization passes has been obtained, each clock slave component uses an average transmission delay to synchronize its time to the clock master time.

Phased array antenna data re-alignment

Abstract: A digital phased array antenna data processing system comprises an antenna array having a plurality of antenna elements connected to an analog-to-digital converter for digitizing received signals. Each analog-to-digital converter is connected to the output of a clock time delay unit also connected to the output of a master clock. The time delay digitized output of the analog-to-digital converter is applied to a data time delay unit for a realignment updated signal from the elements of the antenna.

System and method for synchronizing clock dividers in a wireless network

Abstract: A wireless network includes a plurality of base stations that provide a wireless communication capability for a plurality of mobile stations. Each base station includes a local clock unit with a clock divider that generates local clock signals from a master clock signal received from a master clock source. The base stations are partitioned into a plurality of clusters. A sync pulse is propagated to each base station of the wireless network in order to reset their respective clock dividers. resetting of the clock dividers provides synchronization of local clock signals among the base stations. The sync pulse is propagated to all bases stations within a first cluster wherein one of the base stations in the first cluster is also a member of a second cluster. The base station that is part of the first and second clusters then propagates the sync pulse to other base stations in the second cluster and so on until the sync pulse has been delivered to all base stations in the wireless network.

System and method for synchronizing multiple phase-lock loops or other synchronizable oscillators without using a master clock signal

Abstract: A system and method for synchronizing a plurality of synchronizable oscillators are disclosed The method includes monitoring a respective output signal of each synchronizable oscillator, each output signal having a respective frequency, generating a synchronization signal based on the output signal having the highest frequency of all of the output signals, and providing the synchronization signal to all of the synchronizable oscillators

Synchronization of a multi-mode base station using a common system clock

Abstract: A method for synchronizing a multi-mode base station using one clock, when the systems to be synchronized are a GSM-type telecommunications system, for instance a GSM or EDGE system, and a WCDMA-type telecommunications system. In the method, the clock of the WCDMA-type system or a multiple thereof is selected as the system clock of the multi-mode base station, the system clock of the GSM-type system is implemented using multiples of the frequency of the selected clock, and the frame structure of the GSM-type system is synchronized at intervals of thirteen frames or a multiple of thirteen frames.

Base site and method for GPS-based regional time synchronization

Abstract: To address the need for an apparatus and method of economically synchronizing base sites ( 110 - 113 ) in wireless communication systems, the present invention provides a GPS-based solution for synchronizing slave sites ( 111 - 113 ) to a regional master site ( 110 ). In general, the master site reports to the slave sites information indicating the timing variance of GPS satellites ( 101 - 105 ). The slave sites then use this information in combination with information they collect from the same satellites to periodically resynchronize their clocks to the master clock.

Method and apparatus for clock synchronization using quantum mechanical non-locality effects

Abstract: A method for synchronizing a master clock to a slave clock located in master and slave devices communicating with one another via a laser signal beam and a communications channel, each of the devices including a homodyne detector for determining a respective correlation pattern with respect to a phase tuned local oscillator includes steps for recording master and slave correlation patterns while the signal beam cycles between first and second operating modes, transmitting the master correlation pattern and associated first and second times at which the signal beam shifted between the first and second operating modes and between the second and first operating modes over the communications channel, comparing a portion of the master correlation pattern between the first and second times to the slave correlation pattern to thereby determine the time offset between the master and slave correlation patterns, and applying the time offset to the slave clock. A corresponding clock synchronization system is also described.

Methods and apparatus for generating high-frequency clocks deterministically from a low-frequency system reference clock

Abstract: A method and apparatus for maintaining clock phase alignment among system modules of a fault-tolerant computing system. In one embodiment, a low-frequency system reference clock signal is distributed to all system modules where it is multiplied to generate higher-frequency local clock signals. All local clock signals are then synchronized to the rising edge of the reference clock signal and the first rising edge in relation to a timing event is also identified.

System architecture and method for synchronization of real-time clocks in a document processing system

Abstract: A system architecture and method are provided for synchronizing the slave clock of one or more resources with the master clock of a controller in a document processing system. The method includes: a) saving a value of the master clock ( 615 ); b) generating a discrete clock synchronization interrupt signal and distributing the interrupt signal to the resource(s) via the control bus ( 625 ); c) receiving the interrupt signal at each resource ( 630 ) and saving a value of the slave clock ( 640 ); d) sending a message to the controller via a network to request the value saved for the master clock ( 645 ); e) sending the value to the resource ( 660 ); f) receiving the value ( 665 ); and g) subtracting the value saved for the slave clock from the value saved for the master clock to determine an error value between the clocks ( 690 ) and using the error value in an adjustment algorithm to synchronize the slave clock with the master clock ( 695 ).