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Showing papers on "Master clock published in 2002"


Patent
06 Feb 2002
TL;DR: In this article, a slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate.
Abstract: Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.

163 citations


Patent
24 Jul 2002
TL;DR: In this paper, an improved clock synchronization algorithm for a distributed system intended for real-time applications is presented, by performing at the same time an offset correction and a clock read correction at each node of the distributed system.
Abstract: The present invention provides an improved clock synchronization algorithm for a distributed system intended for real time applications by performing at the same time an off-set correction and a clock read correction at each node of the distributed system. Expensive oscillators can be avoided and synchronization can be established faster and with higher precision.

153 citations


Patent
Stephen H. Strong1
10 Sep 2002
TL;DR: In this paper, a master box is connected with at least one slave box and the ports on the connected boxes are logically grouped in domains, and the master box generates a clock signal that is adjusted and distributed to the slave boxes.
Abstract: Systems and methods for synchronizing time stamp counters of ports in a domain and for starting, stopping and triggering the ports in the domain at substantially the same time. A master box is connected with at least one slave box and the ports on the connected boxes are logically grouped in domains. The master box generates a clock signal that is adjusted and distributed to the slave boxes. The clock signal thus received by the slave boxes drives a clock multiplier that in turn drives the time stamp counters of the ports in the domains across the respective boxes. The time stamps of ports within a domain are synchronized because they are driven by the clock signal from the master box. The ports in a particular domain can be started, stopped and triggered using control signals that are similarly distributed from the master box to the slave boxes.

86 citations


Patent
07 Nov 2002
TL;DR: In this article, a clock synchronization method and apparatus is disclosed for use in a communication system including a plurality of wireless nodes communicatively coupled via a wireless network, each of the plurality of nodes having a local time base, and one of the nodes being designated as a master node having a master clock against which the local time bases are synchronized.
Abstract: A clock synchronization method and apparatus is disclosed for use in a communication system including a plurality of wireless nodes communicatively coupled via a wireless network, each of the plurality of wireless nodes having a local time base, and one of the plurality of wireless nodes being designated as a master node having a master time base which serves as a master clock against which the local time bases are synchronized. The clock synchronization method includes the steps of periodically transmitting synchronization frames to the plurality of non-master nodes so as to adjust the slave clocks associated with the respective non-master nodes. The synchronization frames are distributed from the master node at near-periodic intervals and includes a cycle time value that corresponds to the end of the previously transmitted synchronization frame. The slave clocks (i.e., non-master nodes) receiving the synchronization frame determine the cycle time value at the point of reception of the synchronization frame and adjusts their clocks by calculating a difference value between the received cycle time and a previously saved local cycle time value.

73 citations


Patent
05 Jul 2002
TL;DR: In this article, the clock shift, clock drift and propagation delay values are calculated using a series of message exchanges and control algorithms between a selected reference node and a client node in a wireless network, then uses these values to synchronize the client node clock to the reference node clock.
Abstract: A system and method for establishing and maintaining node clock synchronization in a wireless network The system and method calculates the clock shift, clock drift and propagation delay values using a series of message exchanges and control algorithms between a selected reference node and a client node in a wireless network, then uses these values to synchronize the client node clock to the reference node clock

67 citations


Patent
17 Dec 2002
TL;DR: In this paper, a controller that is linearly responsive to an input voltage provides continuously adjustable control of the width of a periodically repeating digital pulse, thereby achieving a linear voltage to duty-cycle ratio transfer function.
Abstract: A controller that is linearly responsive to an input voltage provides continuously adjustable control of the width of a periodically repeating digital pulse, thereby achieving a linear voltage to duty-cycle ratio transfer function. The circuit of the present invention includes a master clock input, a ratio control voltage input, a controlled duty cycle clock output, a high gain amplifier configured as an integrator having differential inputs, each equipped with a low pass filter, a controlled current source, a resettable timing capacitor, a threshold detector and a reference pulse generator.

57 citations


Patent
20 Mar 2002
TL;DR: In this paper, a system and method for synchronizing clocks related to telecommunications throughout a point-to-multipoint optical network utilizes downstream data timed using a high frequency transmission clock received from a central office CO (102) to distribute timing information of a central telecom-based clock (316) to remote terminals (ONU).
Abstract: A system and method for synchronizing clocks related to telecommunications throughout a point-to-multipoint optical network utilizes downstream data timed using a high frequency transmission clock received from a central office CO (102) to distribute timing information of a central telecom-based clock (316) to remote terminals (ONU). In an exemplary embodiment, the point-to-multipoint optical network system is an Ethernet-based passive optical network PON system that operates in accordance with a Gigabit Ethernet standard. The timing information of the central telecom-based clock (316) is extracted from the downstream data (220) at each remote terminal (ONU) by recovering the high frequency transmission clock (322) and then, deriving a reference clock, which is synchronized with the central telecom-based clock (316), from the recovered transmission clock. The reference clock is then used to generate one or more telecom-related clocks (318) that are needed by the remote terminal (ONU). The system and method allows telecom-related clocks throughout the system to be synchronized in an efficient and cost-effective manner.

52 citations


Patent
14 Nov 2002
TL;DR: In this article, the authors propose a method for time synchronization using dynamic thresholds, which includes calculating a latency (104) of the time synchronization message and estimating an adjustment (106) that may be made to the internal clock in response to the message.
Abstract: Methods and apparatus for time synchronization using dynamic thresholds. A method for synchronizing network elements includes receiving at a network element a time synchronization message (102) sent from a master clock element. The network element includes an internal clock to be synchronized with a master clock of the master clock element. The method includes calculating a latency (104) of the time synchronization message. The method includes estimating an adjustment (106) that may be made to the internal clock in response to the time synchronization message. The method includes determining whether the latency calculated is less than the adjustment estimated (108). The method includes adjusting the internal clock (110) when the latency calculated is less than the adjustment estimated.

48 citations


Book
01 Nov 2002
TL;DR: Noise Characteristics in Circuits and Devices.
Abstract: If you need an in-depth understanding of the digital clock technologies used in building today's telecommunications networks, this authoritative and practical book is a smart choice. Providing you with critical details on the PLL (phase-locked Loop) technique for clock synchronization and generation, and the DDS (direct digital synthesizer) technique for clock generation, the book helps you achieve synchronization in high-speed networks and frequency stabilization in portable equipment. Covering both wired and wireless networks, the book looks at the combination of circuits and systems to give you a more thorough understanding of important design requirements. You learn important phase lock circuit design techniques, and how to select commercially available equipment for your projects in the field. A comprehensive presentation of frequency generation helps you make system/circuit design fluent and efficient. The book includes over 165 illustrations and 146 equations that support major topics.

44 citations


Proceedings ArticleDOI
08 Apr 2002
TL;DR: This work proposes a scheme in which each synchronous module has both an incoming and an outgoing clock signal, which have been obtained by opening the module's ring oscillator, and demonstrates the technique in the context of processors and memories.
Abstract: We present a method for synchronizing pausible clocks in GALS (Globally Asynchronous, Locally Synchronous) systems. In contrast to most conventional GALS schemes the method is not based on including in each ring oscillator a synchronizing element (such as for instance an arbiter) which on one side can pause the clock and on the other side offers a handshake interface. Instead, we propose a scheme in which each synchronous module has both an incoming and an outgoing clock signal, which have been obtained by opening the module's ring oscillator. Since these clock signals also behave as handshake signals, handshake circuits can be used to synchronize the clocks. We demonstrate the technique in the context of processors and memories. All the designs have been simulated and showed functionally correct.

40 citations


Patent
20 Dec 2002
TL;DR: In this paper, a system and method for clock synchronization in a network having one or more asynchronous data links is provided. But the clock signal is propagated through, at the physical layer, a sequence of network devices linking a source network device to a destination network device of the network.
Abstract: A system and method for clock synchronization in a network having one or more asynchronous data links is provided. A clock signal is propagated through, at the physical layer, a sequence of network devices linking a source network device to a destination network device of the network. Each asynchronous data link between the source network device and the destination network device is adapted to receive an incoming clock signal from the previous network device and then provide a clock signal synchronized to the received clock signal to the next network device of the sequence. At the same time, each network device of an asynchronous segment of the network can continue to transmit packets of data asynchronously. By locking the link-based frequency on a per link bases, the receiver clocks located at the edge of a network can be tied directly to a primary source located in the core network.

Patent
02 Oct 2002
TL;DR: In this article, a method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain is presented, where the first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive domain.
Abstract: A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.

Patent
Zhen Liu1, Cathy H. Xia1, Li Zhang1
29 May 2002
TL;DR: In this paper, several algorithms are provided to estimate and remove relative clock skews from delay measurements based on the computation of convex hulls, which are linear in the number of measurement points for the case with no clock resets.
Abstract: Several algorithms are provided to estimate and remove relative clock skews from delay measurements based on the computation of convex hulls. The algorithms are linear in the number of measurement points for the case with no clock resets. For the more challenging case with clock resets, i.e., the clocks are reset to some reference times during the measurement period, linear algorithms are provided to identify the clock resets and derive the best clock skew lines. The algorithms are also extended to environments in which at least one of the clocks is controlled by Network Time Protocol. These algorithms can also be extended for active clock synchronization to replace or further improve Network Time Protocol.

Patent
13 Sep 2002
TL;DR: In this paper, a method and system for avoiding variance in transmission times of real-time, packet-based communications is disclosed, which allow data sources to independently establish their respective transmission timings so as to avoid these collisions, without a need for a master clock shared between all of the data sources.
Abstract: A method and system for avoiding variance in transmission times of real-time, packet-based communications is disclosed. Transmissions such as voice and videoconferencing generally require a substantially constant delivery rate in order to be satisfactory to end users. When occurring via a packet-based network, such transmissions often experience unacceptable levels of variation in delay in their transmission times, and this variation in delay is known as jitter. One cause of jitter relates to collisions between packets generated by a first source and sent via a packet transport medium and other packets, generated by one or more other sources and transmitted by the same transport medium. The method and system disclosed allow data sources to independently establish their respective transmission timings so as to avoid these collisions, without a need for a master clock shared between all of the data sources. By operating in such a peer-to-peer manner, the data sources establish a reduction in jitter in a manner that is reliable, efficient, inexpensive, scaleable, and easy to implement.

Patent
12 Nov 2002
Abstract: A symmetric glitch free clock multiplexing circuit allows the input clock to a digital or analog processing unit to be switched from one frequency to the other at any moment during the operation, assuming the respective clocks themselves are stable. There exist no restrictions on the clocks or the switch control signal to be synchronous in any fashion. This circuit guarantees a glitch free output and also prevents short cycling of the output clock. Since all the related clocks and switch control signal are asynchronous, this circuit further eliminates meta-stability problems. Its symmetrical architecture allows the circuit to function with the output clock being switched from slow clock to fast clock and vise versa. More importantly, the complete switch over only takes two cycles of the targeted clock in the best case once the active clock is turned off, when switching from slow to fast clock; and four target clock cycles in the worst case once the active clock is turned off, when switching from fast to slow clock.

Patent
05 Jul 2002
TL;DR: In this paper, the primary master clock within one of the plurality of nodes provides a clock signal for the embedded clock signal, for use with the TDM protocol, where each node has a network interface component connected to a communication network.
Abstract: A communications system within a vehicle, typically an airplane, is provided. In one embodiment, the communications system comprises a plurality of nodes and wherein each node has a network interface component connected to a communication network. The communication network is configured to communicate data in a serial, time-division multiplexed (TDM) format using an embedded clock signal. Further, a primary master clock within one of the plurality of nodes provides a clock signal for the embedded clock signal for use with the TDM protocol. At least one input device is connected to one of the nodes and converts analog input to a digital format at a sample rate determined by the primary master clock. Additionally, at least one output device is also connected to one of the nodes and output device also converts digital data to an analog format at the same sample rate determined by the primary master clock.

Patent
Scott B. Guthery1
11 Sep 2002
TL;DR: In this paper, an anti-tearing algorithm for data consistency protection in case either power or master clock signal is removed from the limited resource computer before a write operation is complete is presented.
Abstract: A limited resource computer such as one based upon an integrated circuit card (“smart card”) or embedded processor novely employs a full hierarchical file system consistent with desktop and laptop computers, thereby enabling the full execution of application programs. This hierarchical file system contains both files and directories and is consistent with the following limited resource computer considerations: small code size for implementation; compact representation; robust to errors due to loss of power and/or master clock signal; fast access and retrieval; and being appropriate for memory-only storage. Along with doubly linking each of the memory blocks, the present invention also includes an “anti-tearing” algorithm for data consistency protection in case either power or the master clock signal is removed from the limited resource computer before a write operation is complete. The anti-tearing algorithm is operative to ensure that data residing in any object of the hierarchical file system is either in: (1) the state it was in before an atomic write operation was commended with respect to such object; or (2) in the state it will be in after completion of the atomic write operation.

Patent
01 Mar 2002
TL;DR: In this paper, a two-stage interpolation system is proposed to detect, sample, and receive synchronous data streams and eliminate the need for corresponding external synchronization clocks for each data stream.
Abstract: A method, system, and device capable of generating one or more clocks internally to detect, sample, and receive synchronous data streams and eliminate the need for corresponding external synchronization clocks for each data stream. One aspect of the clock generator provides a two-stage interpolation system. In a first stage, two clocks are selected which accurately detect a calibration data sample. In a second stage, a single, fine-tuned, clock is synthesized by interpolating the two selected clocks.

Patent
18 Oct 2002
TL;DR: In this article, a system and method for synchronizing clocks related to telecommunications across an unsynchronized point-to-point network connection utilizes downstream data timed using a high frequency transmission clock to transfer timing information of a central telecom-based clock from a first network node to a second network node.
Abstract: A system and method for synchronizing clocks related to telecommunications across an unsynchronized point-to-point network connection utilizes downstream data timed using a high frequency transmission clock to transfer timing information of a central telecom-based clock from a first network node to a second network node. In an exemplary embodiment, the point-to-point network connection is an Ethernet-based connection that operates in accordance with a Gigabit Ethernet standard. The timing information of the central telecom-based clock is extracted from the transmitted data at the second network node by recovering the high frequency transmission clock and then, deriving a reference clock, which is synchronized with the central telecom-based clock, from the recovered transmission clock. The reference clock is then used to generate one or more telecom-related clocks that are used by the second network node.

Patent
Paul J. Huelskamp1
10 Jun 2002
TL;DR: In this article, the authors present a system for writing data efficiently between a fast clock domain and a slow clock domain, where a processor that performs firmware routines and a hardware that performs certain device operations is always on to operate in the slow domain.
Abstract: A system for writing data efficiently between a fast clock domain and a slow clock domain. In one embodiment, a processor that performs firmware routines is clocked by a fast clock that is turned on when a prescribed event occurs to operate in the fast clock domain in conjunction with hardware that performs certain device operations that is clocked by a slow clock that is always on to operate in a slow clock domain. Writing data from the processor to the hardware involves determining if a bit is to be written to a register of the slow clock domain in synchrony with a transition of the slow clock, stopping the fast clock to pause operation of the processor, writing the bit to the register of the slow clock domain upon a succeeding slow clock transition, and starting the fast clock to resume operation of the processor.

Patent
14 Aug 2002
TL;DR: In this article, the phase comparator forwards the phase or frequency difference of the network transfer rate and the source sample rate to the destination port, which then generates a local clock equivalent to the source which then compiles audio data being played at the same rate in which it was sampled at the source.
Abstract: A communication system, source and destination ports of the communication system, and methodology is provided for transporting data in one of possibly three different ways. Data is transported across the network at a frame sample rate that can be the same as or different from the sample rate or master clock within the source port or the destination port. If the sample rate of the source port is known, the sample rate of the destination port can be created using a PLL within the destination port and simply employing a phase comparator in the source port. The phase comparator forwards the phase or frequency difference of the network transfer rate and the source sample rate to the destination port, which then generates a local clock equivalent to the source which then compiles audio data being played at the same rate in which it was sampled at the source. Where economically feasible, sample rate conversion can be used at the source. However, sample rate conversion at the destination is preferred if the source sample rate is forwarded across the network relative to the frame transfer rate of the synchronous network. The sample rate converter simply produces a play rate from the transmitted information at the destination. Again, however, sample rate conversion compares relative phase difference changes similar to the phase difference compared in the digital PLL mode. As a further alternative, sample rates within the source and destination ports can be derived from the network frame rate using fractional dividers in the source and destination ports.

Patent
20 Dec 2002
TL;DR: In this article, the clock synchronization problem is described for a system including N clocks at least three and at most N-1 of which are master candidate clocks, and a start message is broadcast from the fastest master candidate clock.
Abstract: clock synchronization is described for a system including N clocks at least three and at most N-1 of which are master candidate clocks. A start message is broadcast from the fastest master candidate clock. From each of the master candidate clocks, a response message including the local time of receipt of the start message according to the clock in question is broadcast. Using the information representing the times of receipt of the start message, the median master clock is selected and becomes the master clock. The master clock determines the clock synchronisation error for each master candidate clock, using the information representing the times of receipt of the start message. If any such clock synchronisation error is excessive the master clock declassifies the clock in question as a master candidate clock and classifies another clock as a master candidate clock.

Patent
Masashi Oki1
18 Sep 2002
TL;DR: In this article, a DA converter includes fs detection means for detecting an input sampling frequency fs of digital data by using a sampling clock LRCK and a master clock xfso.
Abstract: A DA converter includes fs detection means for detecting an input sampling frequency fs of digital data by using a sampling clock LRCK and a master clock xfso, an oversampling digital filter for oversampling the digital data on the basis of the input sampling frequency fs, fs change detection means for detecting a change in the input sampling frequency fs, and mute control means for muting the data to be DA-converted on the basis of the detection result of the fs change detection means.

Patent
06 Sep 2002
TL;DR: In this paper, the phase-delayed domain counter (40) output is combined with a programmable offset value chosen based on the phase delay of the clock distribution system, which is used to insure that communication between logic in the clock generation clock domain and Logic in the phasedelayed clock domain occurs deterministically on the correct clock edge for a range of clock frequencies.
Abstract: A clock distribution and control system (10) includes one counter (30) in a clock generation domain and another counter (40) in a phase-delayed clock domain. The phase-delayed domain counter (40) output is combined with a programmable offset value chosen based on the phase delay of the clock distribution system. The result is used to insure that communication between logic in the clock generation clock domain and logic in the phase-delayed clock domain occurs deterministically on the correct clock edge for a range of clock frequencies.

Patent
06 Nov 2002
TL;DR: In this article, a clock architecture employing redundant clock synthesizers is described, where the first clock board may monitor a phase difference between a first crystal clock signal and a feedback clock signal.
Abstract: A clock architecture employing redundant clock synthesizers is disclosed. In one embodiment, a computer system includes first and second clock boards. The first clock board may act as a master, generating a system clock signal, while the second clock board acts as a slave. The first clock board may monitor a phase difference between a first crystal clock signal and a feedback clock signal. If the phase difference exceeds a limit, the first crystal clock signal may be inhibited, preventing the first clock board from generating the system clock signal. The second clock board may monitor the system clock board in reference to a feedback clock signal. If the second clock board detects a predetermined number of consecutive missing clock edges, it may enable a second crystal clock signal, which may be used to generate a system clock signal.

01 Jan 2002
TL;DR: The background for the difficulty—metastability—and new solutions to two different problems: the synchronizer, which synchronizes a signal that can change at an arbitrary time into an asynchronous handshaking domain; and an asynchronous clock-pulse generator, are reviewed.
Abstract: The increasing complexity of modern VLSI systems has caused designers to reevaluate the ageold decision of using a single, central clock and instead turn to asynchronous or globally asynchronous, locally synchronous (GALS) designs. Communication between synchronous and asynchronous subsystems is difficult to do reliably and efficiently. In this paper, we review the background for the difficulty—metastability—and study new solutions to two different problems: (1) the synchronizer, which synchronizes a signal that can change at an arbitrary time into an asynchronous handshaking domain; and (2) an asynchronous clock-pulse generator. The most difficult aspect of computer design has always been timing. Many early computers (e.g., the ILLIAC and the DEC PDP-6) were asynchronous; these systems’ designers felt that asynchronous machines were modular because timing issues could be localized to small parts of the machines. As late as the 1980s, asynchronous bus protocols were still common (such as DEC’s UNIBUS and the original SCSI protocol, which is still supported by modern SCSI devices). But the difficulties of crossing from one clock domain to another spelled doom for asynchronous protocols, at least in small systems such as PCs, and today the standard approach is to provide the system designer with a hierarchy of clocks, all driven through “gearboxes” by a single central master. (The gearboxes are circuits that generate slave clocks, which are rational multiples of the master clock.) In larger systems, such as local-area networks, this is impossible, and such systems must cope with having several independent clock domains. The trend in VLSI is that the chips get larger, the clocks get faster, and everything gets more complicated. We can expect that tomorrow’s chips will look like today’s local-area networks: the number of clock cycles required to get from one end of the die to the other will increase dramatically. This means that the gearbox approach will become more and more difficult to maintain, because a single wire might span several clock cycles, and the designer will find it difficult to ensure that, for instance, setup and hold times are maintained. A way to deal with the increasing design complexity of VLSI systems is to bring back asynchrony. Several groups have had considerable success with entirely asynchronous systems [19, 4, 20, 5]; others have pursued the globally asynchronous, locally synchronous (GALS) paradigm, first suggested by Chapiro in 1984 [3]. In either case, the issue of interfacing synchronous and asynchronous domains arises. The authors are with the Computer Science Department of the California Institute of Technology, Pasadena, CA 91125, U.S.A. Synchronous and asynchronous design methodologies are based on a simple principle: design composable subsystems in such a way that if the subsystems’ environments satisfy certain assumptions, then the subsystems themselves will present such environments to their neighbors. For synchronous systems, these assumptions take the form of the circuits’ having to maintain legal logic levels within certain setup and hold times. One might think that “asynchronous” circuits naturally make weaker demands on their environments since the clock has been removed. This is not necessarily so. In all asynchronous design methodologies, the synchronous level and timing requirements are replaced by certain handshaking requirements—requirements on the ordering of signal transitions. This means that sampling a signal from a synchronous system within the asynchronous framework is fraught with difficulty, much like the converse operation of sampling an asynchronous signal within the synchronous framework. With care, however, an asynchronous system can sample an unsynchronized signal with zero probability of synchronization failure. We shall review the main source of trouble: metastability; secondly, we shall investigate efficient solutions to a few typical problems: (1) the synchronizer problem, which is concerned with “absorbing” an arbitrarily varying signal into a four-phase signalling scheme; and (2) implementation of an asynchronous timer without introducing metastability.

Patent
11 Jan 2002
TL;DR: In this article, a comparator for comparing the phase of the first and second synchronisation signals of a video signal generator is provided, and a means for applying the master clock signal to the second output in place of the slave clock signal when the synchronising signals from the first-and second-synch signals are in phase.
Abstract: Apparatus for synchronising a plurality of independent video signal generators comprises a first input ( 12 ) for receiving field or frame synchronising signals from a first video signal generator, a second input ( 14 ) for receiving field or frame synchronising signals from a second video signal generator, a comparator ( 13 ) for comparing the phase of the first and second synchronisation signals, a master clock generator ( 1 ), a slave clock generator ( 4 ), the slave clock generator ( 4 ) having a frequency different from that of the master clock generator ( 1 ), means for applying the master clock signal to a first output ( 7 ) for application to the first video signal generator, means for applying the slave clock signal to a second output ( 9 ) for application to the second video signal generator, and means ( 5 ) for means for applying the master clock signal to the second output ( 9 ) in place of the slave clock signal when the synchronising signals from the first and second synchronising signals are in phase. A second comparator ( 3 ) is provided for comparing the phase of the master clock ( 1 ) and the slave clock ( 4 ) so that the operation of the means ( 5 ) for applying the master clock ( 1 ) to the second output ( 9 ) is dependent also on the master ( 1 ) and slave ( 4 ) clocks being in phase.

Patent
31 Jan 2002
TL;DR: In this article, a clock selection circuit for selecting between two clock sources has been proposed, which includes interlock circuitry that ensures that at any given time only one clock is enabled to the output.
Abstract: A clock selection circuit for selecting between two clock sources. The clock selection circuit has two independent clock inputs, CLK 1 and CLK 2 , where no assumptions are made regarding frequency or phase relationship between the two clocks inputs. Two asynchronous inputs, START 1 and START 2 (both active high), are used to start and stop the clocks. As long as one clock is active, the START signal of the other clock will not have any effect. The invention includes interlock circuitry that ensures that at any given time only one clock is enabled to the output. Disabling the corresponding START signal disables the clock signal.

Patent
14 Aug 2002
TL;DR: In this article, a design for testability (DFT) structure is used to provide partitioning of a master clock into multiple clock signals each associated with a corresponding one of the levels of self-loops, so as to permit breaking of the feedback loops other than the selfloops.
Abstract: Techniques for testing a sequential circuit comprising a plurality of flip-flops or other types of registers. The circuit is first configured such that substantially all feedback loops associated with the registers, other than one or more self-loops each associated with a corresponding one of the registers, are broken. Test patterns are then generated for application to the circuit. The test patterns are applied to the circuit in conjunction with partitioned clock signals each of which is associated with a corresponding level of the circuit containing at least one of the self-loops. In an illustrative embodiment, a design for testability (DFT) structure is used to provide partitioning of a master clock into multiple clock signals each associated with a corresponding one of the levels of self-loops, so as to permit breaking of the feedback loops other than the self-loops. The registers of the circuit may be arranged in the particular levels by assigning a first one of the levels to each register which is fed only by primary inputs (PIs) of the circuit, and then assigning to level i+1 every register that is fed by other registers whose maximum level is i, where i=1, 2, . . . d, and d is the sequential depth of the circuit. In addition, each of the levels of registers may have multiple groups of registers associated therewith, with each of the groups being subject to clocking by one of the partitioned clock signals through the operation of group selection circuitry.

Patent
Takashi Kono1
05 Sep 2002
TL;DR: In this article, a DLL circuit generates first and second internal clocks delayed by appropriate quantities from an external clock, and generates third and fourth internal clocks capable of driving a data output circuit after a CAS latency.
Abstract: A DLL circuit generates first and second internal clocks delayed by appropriate quantities from an external clock, and generates third and fourth internal clocks capable of driving a data output circuit after a CAS latency from the first and second internal clocks on the basis of an internal signal. A repeater recovers signal levels of the third and fourth internal clocks and outputs the third and fourth internal clocks as DLL clocks. The data output circuit takes in read data using the DLL clocks outputted from the repeater, and outputs the read data to an outside in a half cycle synchronously with the DLL clocks. In this way, a circuit area of a semiconductor memory device can be reduced by generating the DLL clocks in a prior stage to the data output circuit.